/**
 * @file  gpio-fp.h
 * @brief GPIO API for Fastcall driver(Fingerprint)
 *
 * Copyright (c) 2014-2015 Samsung Electronics Co., Ltd.
 *
 * This software is proprietary of Samsung Electronics.
 * No part of this software, either material or conceptual may be copied
 * or distributed, transmitted, transcribed, stored in a retrieval system
 * or translated into any human or computer language in any form by any means,
 * electronic, mechanical, manual or otherwise, or disclosed to third parties
 * without the express written permission of Samsung Electronics.
 */

#ifndef __GPIO_FP_H__
#define __GPIO_FP_H__

#ifdef __cplusplus
extern "C" {
#endif

/************************************************************************/
/* Virtual address for SFRs                                             */
/************************************************************************/
#define FP_SFR_VA_BASE	    0x90000
#define FP_TZPC_SPI_SFR_VA		(FP_SFR_VA_BASE)
#define FP_TZPC_GPIO_SFR_VA	(FP_SFR_VA_BASE + 0x1000)
#define FP_GPIO_SFR_VA	    (FP_SFR_VA_BASE + 0x2000)

#define FP_RET_SUCCESS			0
#define FP_RET_FAILED			-1
#define FP_RET_UNUSED_FUNCTION	-2

#define FP_SPI_PROTECTION_DONE			(0x1 << 0)
#define FP_USI_I_MODE_PROTECTION_DONE	(0x1 << 1)
#define FP_GPIO_PROTECTION_DONE			(0x1 << 2)

/* This feature setting must be the #undef in release build mode */
/* This feature can be used when AP is setup for the first time. */
#undef FP_TEST_PROTECTION_FUNCTION

/************************************************************************/
/* TZPC control                                                         */
/************************************************************************/
#define FP_MODE		0x1
#define FP_TZPC_SECURE	0x0

#if defined(CONFIG_EXYNOS7420) || defined(CONFIG_EXYNOS5433) \
	|| defined(CONFIG_EXYNOS7580) || defined(CONFIG_EXYNOS8890) \
	|| defined(CONFIG_EXYNOS7870) || defined(CONFIG_EXYNOS7880) \
	|| defined(CONFIG_EXYNOS7570) || defined(CONFIG_EXYNOS8895) \
	|| defined(CONFIG_EXYNOS7885) || defined(CONFIG_EXYNOS9810)
#define FP_GPIO_PROTECTION
#endif
#if defined(CONFIG_EXYNOS9810)
#define FP_TZPC_SPI_SFR_BASE			FP_TZPC_USI00_SFR_BASE
#define FP_TZPC_SPI_DECPROT_NUM			FP_TZPC_DECPROTCLR
#define FP_TZPC_SPI_DECSTAT_NUM			FP_TZPC_DECPROTSTAT
#define FP_TZPC_SPI_DECPROT_BIT			FP_TZPC_USI00_CH0_M

#define FP_TZPC_USI_SFR_BASE			FP_TZPC_USI00_SFR_BASE
#define FP_TZPC_USI_DECPROT_NUM			FP_TZPC_DECPROTCLR
#define FP_TZPC_USI_DECSTAT_NUM			FP_TZPC_DECPROTSTAT
#define FP_TZPC_USI_DECPROT_BIT			FP_TZPC_USI00_I_MODE_M
#if defined(FP_GPIO_PROTECTION)
#define FP_TZPC_GPIO_SFR_BASE			FP_TZPC_PERIC0_0_SFR_BASE
#define FP_TZPC_GPIO_DECPROT_NUM		0x0000
#define FP_TZPC_GPIO_DECSTAT_NUM		0x0000
#define FP_TZPC_GPIO_DECPROT_BIT		FP_TZPC_GPIO_PERIC0_M
#endif	/* FP_GPIO_PROTECTION */

#elif defined(CONFIG_EXYNOS8895)
#define FP_TZPC_SPI_SFR_BASE			FP_TZPC13_SFR_BASE
#define FP_TZPC_SPI_DECPROT_NUM			FP_TZPC_DECPROT2CLR
#define FP_TZPC_SPI_DECSTAT_NUM			FP_TZPC_DECPROT2STAT
#define FP_TZPC_SPI_DECPROT_BIT			FP_TZPC_USI00_CH0_M

#define FP_TZPC_USI_SFR_BASE			FP_TZPC3_SFR_BASE
#define FP_TZPC_USI_DECPROT_NUM			FP_TZPC_DECPROT3CLR
#define FP_TZPC_USI_DECSTAT_NUM			FP_TZPC_DECPROT3STAT
#define FP_TZPC_USI_DECPROT_BIT			FP_TZPC_USI00_I_MODE_M
#if defined(FP_GPIO_PROTECTION)
#define FP_TZPC_GPIO_SFR_BASE			FP_TZPC_PERIC0_0_SFR_BASE
#define FP_TZPC_GPIO_DECPROT_NUM		0x0000
#define FP_TZPC_GPIO_DECSTAT_NUM		0x0000
#define FP_TZPC_GPIO_DECPROT_BIT		FP_TZPC_GPIO_PERIC0_M
#endif	/* FP_GPIO_PROTECTION */

#elif defined(CONFIG_EXYNOS8890)
#define FP_TZPC_SPI_SFR_BASE			FP_TZPC12_SFR_BASE
#define FP_TZPC_SPI_DECPROT_NUM			FP_TZPC_DECPROT0CLR
#define FP_TZPC_SPI_DECSTAT_NUM			FP_TZPC_DECPROT0STAT
#define FP_TZPC_SPI_DECPROT_BIT			FP_TZPC_SPI4_M
#if defined(FP_GPIO_PROTECTION)
#define FP_TZPC_GPIO_SFR_BASE			FP_TZPC11_SFR_BASE
#define FP_TZPC_GPIO_DECPROT_NUM		FP_TZPC_DECPROT1CLR
#define FP_TZPC_GPIO_DECSTAT_NUM		FP_TZPC_DECPROT1STAT
#define FP_TZPC_GPIO_DECPROT_BIT		FP_TZPC_GPIO_ESE_M
#endif	/* FP_GPIO_PROTECTION */

#elif defined(CONFIG_EXYNOS7885)
#define FP_TZPC_SPI_SFR_BASE			0x100F0000
#define FP_TZPC_SPI_DECPROT_NUM			FP_TZPC_SECUCONPROT9CLR
#define FP_TZPC_SPI_DECSTAT_NUM			FP_TZPC_SECUCONPROT9STAT
#define FP_TZPC_SPI_DECPROT_BIT			FP_TZPC_SPI1_M
#if defined(FP_GPIO_PROTECTION)
#define FP_TZPC_GPIO_SFR_BASE			0x139B2000
#define FP_TZPC_GPIO_DECPROT_NUM		0x0004
#define FP_TZPC_GPIO_DECSTAT_NUM		0x0004
#define FP_TZPC_GPIO_DECPROT_BIT		FP_TZPC_GPIO_TOM_M
#endif	/* FP_GPIO_PROTECTION */

#elif defined(CONFIG_EXYNOS7880) || defined(CONFIG_EXYNOS7870)
#define FP_TZPC_SPI_SFR_BASE			FP_TZPC2_SFR_BASE
#define FP_TZPC_SPI_DECPROT_NUM			FP_TZPC_DECPROT2CLR
#define FP_TZPC_SPI_DECSTAT_NUM			FP_TZPC_DECPROT2STAT
#define FP_TZPC_SPI_DECPROT_BIT			FP_TZPC_SPI1_M
#if defined(FP_GPIO_PROTECTION)
#define FP_TZPC_GPIO_SFR_BASE			FP_TZPC4_SFR_BASE
#define FP_TZPC_GPIO_DECPROT_NUM		FP_TZPC_DECPROT0CLR
#define FP_TZPC_GPIO_DECSTAT_NUM		FP_TZPC_DECPROT0STAT
#define FP_TZPC_GPIO_DECPROT_BIT		FP_TZPC_GPIO_ESE_M
#endif	/* FP_GPIO_PROTECTION */

#elif defined(CONFIG_EXYNOS7570)
#define FP_TZPC_SPI_SFR_BASE			FP_TZPC2_SFR_BASE
#define FP_TZPC_SPI_DECPROT_NUM			FP_TZPC_DECPROT2CLR
#define FP_TZPC_SPI_DECSTAT_NUM			FP_TZPC_DECPROT2STAT
#define FP_TZPC_SPI_DECPROT_BIT			FP_TZPC_SPI0_M
#if defined(FP_GPIO_PROTECTION)
#define FP_TZPC_GPIO_SFR_BASE			FP_TZPC4_SFR_BASE
#define FP_TZPC_GPIO_DECPROT_NUM		FP_TZPC_DECPROT0CLR
#define FP_TZPC_GPIO_DECSTAT_NUM		FP_TZPC_DECPROT0STAT
#define FP_TZPC_GPIO_DECPROT_BIT		FP_TZPC_GPIO_ESE_M
#endif	/* FP_GPIO_PROTECTION */

#elif defined(CONFIG_EXYNOS7580)
#define FP_TZPC_SPI_SFR_BASE			FP_TZPC3_SFR_BASE
#define FP_TZPC_SPI_DECPROT_NUM			FP_TZPC_DECPROT2CLR
#define FP_TZPC_SPI_DECSTAT_NUM			FP_TZPC_DECPROT2STAT
#define FP_TZPC_SPI_DECPROT_BIT			FP_TZPC_SPI2_M
#if defined(FP_GPIO_PROTECTION)
#define FP_TZPC_GPIO_SFR_BASE			FP_TZPC3_SFR_BASE
#define FP_TZPC_GPIO_DECPROT_NUM		FP_TZPC_DECPROT1CLR
#define FP_TZPC_GPIO_DECSTAT_NUM		FP_TZPC_DECPROT1STAT
#define FP_TZPC_GPIO_DECPROT_BIT		FP_TZPC_GPIO_ESE_M
#endif	/* FP_GPIO_PROTECTION */

#elif defined(CONFIG_EXYNOS7420)
#define FP_TZPC_SPI_SFR_BASE			FP_TZPC12_SFR_BASE
#define FP_TZPC_SPI_DECPROT_NUM			FP_TZPC_DECPROT3CLR
#define FP_TZPC_SPI_DECSTAT_NUM			FP_TZPC_DECPROT3STAT
#define FP_TZPC_SPI_DECPROT_BIT			FP_TZPC_SPI4_M
#if defined(FP_GPIO_PROTECTION)
#define FP_TZPC_GPIO_SFR_BASE			FP_TZPC13_SFR_BASE
#define FP_TZPC_GPIO_DECPROT_NUM		FP_TZPC_DECPROT1CLR
#define FP_TZPC_GPIO_DECSTAT_NUM		FP_TZPC_DECPROT1STAT
#define FP_TZPC_GPIO_DECPROT_BIT		FP_TZPC_GPIO_ESE_M
#endif	/* FP_GPIO_PROTECTION */

#elif defined(CONFIG_EXYNOS5433) || defined(CONFIG_EXYNOS5430)
#define FP_TZPC_SPI_SFR_BASE			FP_TZPC5_SFR_BASE
#define FP_TZPC_SPI_DECPROT_NUM			FP_TZPC_DECPROT0CLR
#define FP_TZPC_SPI_DECSTAT_NUM			FP_TZPC_DECPROT0STAT
#define FP_TZPC_SPI_DECPROT_BIT			FP_TZPC_SPI2_M
#if defined(FP_GPIO_PROTECTION)
#define FP_TZPC_GPIO_SFR_BASE			FP_TZPC12_SFR_BASE
#define FP_TZPC_GPIO_DECPROT_NUM		FP_TZPC_DECPROT2CLR
#define FP_TZPC_GPIO_DECSTAT_NUM		FP_TZPC_DECPROT2STAT
#define FP_TZPC_GPIO_DECPROT_BIT		FP_TZPC_GPIO_FINGER
#endif	/* FP_GPIO_PROTECTION */

#elif defined(CONFIG_EXYNOS5422) || defined(CONFIG_EXYNOS5420)
#define FP_TZPC_SPI_SFR_BASE			FP_TZPC3_SFR_BASE
#define FP_TZPC_SPI_DECPROT_NUM			FP_TZPC_DECPROT2CLR
#define FP_TZPC_SPI_DECSTAT_NUM			FP_TZPC_DECPROT2STAT
#define FP_TZPC_SPI_DECPROT_BIT			FP_TZPC_SPI1_M

#endif


/************************************************************************/
/* GPIO control                                                         */
/************************************************************************/
#define FP_GPIO_HIGH	0x1
#define FP_GPIO_LOW	0x0

#if defined(CONFIG_EXYNOS9810)
#define FP_GPIOCON_MASK				0x0000FFFF // [15:0]
#define FP_GPIODAT_MASK				0x0000000F // [3:0]
#define FP_GPIOPUD_MASK				0x0000FFFF // [15:0]
#define FP_GPIODRV_MASK				0x0000FFFF // [15:0]
#define FP_GPIOCONPDN_MASK			0x000000FF // [7:0]
#define FP_GPIOPUDPDN_MASK			0x0000FFFF // [15:0]

#define FP_GPIO_SFR_BASE			FP_GPIO_PERIC0_SFR_BASE
#define FP_USI_I_MODE_SFR_BASE		FP_USI00_I_MODE_SFR_BASE
#define FP_USI_I_MODE_SFR			FP_USI00_I_MODE_SFR
#define FP_USI_I_MODE_VALUE			0x2
#define FP_GPIOCON_INIT_VALUE		0x2222 // nSS|MISO|MOSI|CLK
#define FP_GPIODAT_INIT_VALUE		0x0000 // undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE		0x3011 // PU|NP|PD|PD
#define FP_GPIODRV_INIT_VALUE		0x1111 // 2x|2x|2x|2x
#define FP_GPIOCON_INIT_VALUE_OFF	0x1011 // OUTPUT|INPUT|OUTPUT|OUTPUT
#define FP_GPIODAT_INIT_VALUE_OFF	0x0000 // low|undef|low|low
#define FP_GPIOPUD_INIT_VALUE_OFF	0x0100 // NP|PD|NP|NP
#define FP_GPIODRV_INIT_VALUE_OFF	0x1111 // 2x|2x|2x|2x
#define FP_GPIOCONPDN_VALUE			0x0020 // out0|input|out0|out0
#define FP_GPIOCONPDN_CSHIGH_VALUE	0x0060 // out1|input|out0|out0
#define FP_GPIOPUDPDN_VALUE			0x0100 // NP|PD|NP|NP
#define FP_GPIOCON_CSSET_VALUE		0x1011 // OUTPUT|INPUT|OUTPUT|OUTPUT
#define FP_GPIOPUD_CSSET_VALUE		0x0100 // NP|PD|NP|NP

#elif defined(CONFIG_EXYNOS8895)
#define FP_GPIOCON_MASK				0x0000FFFF // [15:0]
#define FP_GPIODAT_MASK				0x0000000F // [3:0]
#define FP_GPIOPUD_MASK				0x000000FF // [7:0]
#define FP_GPIODRV_MASK				0x000000FF // [7:0]
#define FP_GPIOCONPDN_MASK			0x000000FF // [7:0]
#define FP_GPIOPUDPDN_MASK			0x000000FF // [7:0]

#define FP_GPIO_SFR_BASE			FP_GPIO_PERIC0_SFR_BASE
#define FP_USI_I_MODE_SFR_BASE		FP_USI00_I_MODE_SFR_BASE
#define FP_USI_I_MODE_SFR			FP_USI00_I_MODE_SFR
#define FP_USI_I_MODE_VALUE			0x4 // SPI
#define FP_GPIOCON_INIT_VALUE		0x2222 // CLK|nSS|MOSI|MISO
#define FP_GPIODAT_INIT_VALUE		0x0000 // undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE		0x00FF // PU|PU|PU|PU
#define FP_GPIODRV_INIT_VALUE		0x0055 // 2x|2x|2x|2x
#define FP_GPIOCON_INIT_VALUE_OFF	0x0000 // INPUT|INPUT|INPUT|INPUT
#define FP_GPIODAT_INIT_VALUE_OFF	0x0000 // undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE_OFF	0x0055 // PD|PD|PD|PD
#define FP_GPIODRV_INIT_VALUE_OFF	0x0055 // 2x|2x|2x|2x
#define FP_GPIOCONPDN_VALUE			0x0082 // input|out0|out0|input
#define FP_GPIOCONPDN_CSHIGH_VALUE	0x0092 // input|out1|out0|input
#define FP_GPIOPUDPDN_VALUE			0x0041 // PD|NP|NP|PD
#define FP_GPIOCON_CSSET_VALUE		0x0110 // INPUT|OUT|OUT|INPUT
#define FP_GPIOPUD_CSSET_VALUE		0x0041 // PD|NP|NP|PD

#elif defined(CONFIG_EXYNOS8890)
#define FP_GPIO_SFR_BASE			FP_GPIO_ESE_SFR_BASE
#define FP_GPIOCON_INIT_VALUE		0x12222 // Output|MOSI|MISO|CS_N|CLK
#define FP_GPIODAT_INIT_VALUE		0x00000 // undef|undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE		0x01FF // PD|PU|PU|PU|PU
#define FP_GPIODRV_INIT_VALUE		0x0492 // 1x|3x|3x|3x|3x
#define FP_GPIOCONPDN_VALUE			0x0320 // Previous State|out0|input|out0|out0
#define FP_GPIOPUDPDN_VALUE			0x0010 // NP|NP|PD|NP|NP
#define FP_GPIOCONPDN_CSHIGH_VALUE	0x0324 // Previous State|out0|input|out1|out0

#elif defined(CONFIG_EXYNOS7885)
#define FP_GPIOCON_MASK				0x0000FFFF // [15:0]
#define FP_GPIODAT_MASK				0x0000000F // [3:0]
#define FP_GPIOPUD_MASK				0x0000FFFF // [15:0]
#define FP_GPIODRV_MASK				0x0000FFFF // [15:0]
#define FP_GPIOCONPDN_MASK			0x000000FF // [7:0]
#define FP_GPIOPUDPDN_MASK			0x0000FFFF // [15:0]

#define FP_GPIO_SFR_BASE			FP_GPIO_TOP_SFR_BASE
#define FP_GPIOCON_INIT_VALUE		0x2222 // MOSI|MISO|CS_N|CLK
#define FP_GPIODAT_INIT_VALUE		0x0000 // undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE		0x3333 // PU|PU|PU|PU
#define FP_GPIODRV_INIT_VALUE		0x2222 // 3x|3x|3x|3x
#define FP_GPIOCON_INIT_VALUE_OFF	0x0000 // INPUT|INPUT|INPUT|INPUT
#define FP_GPIODAT_INIT_VALUE_OFF	0x0000 // undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE_OFF	0x1111 // PD|PD|PD|PD
#define FP_GPIODRV_INIT_VALUE_OFF	0x2222 // 3x|3x|3x|3x
#define FP_GPIOCONPDN_VALUE			0x0020 // out0|input|out0|out0
#define FP_GPIOPUDPDN_VALUE			0x0101 // NP|PD|NP|PD
#define FP_GPIOCON_CSSET_VALUE		0x1011 // OUT|INPUT|OUT|OUT
#define FP_GPIOPUD_CSSET_VALUE		0x1101 // PD|PD|NP|PD
#define FP_GPIOCONPDN_CSHIGH_VALUE	0x0024 // out0|input|out1|out0

#elif defined(CONFIG_EXYNOS7880)
#define FP_GPIOCON_MASK				0x0000FFFF // [15:0]
#define FP_GPIODAT_MASK				0x0000000F // [3:0]
#define FP_GPIOPUD_MASK				0x000000FF // [7:0]
#define FP_GPIODRV_MASK				0x00000FFF // [11:0]
#define FP_GPIOCONPDN_MASK			0x000000FF // [7:0]
#define FP_GPIOPUDPDN_MASK			0x000000FF // [7:0]

#define FP_GPIO_SFR_BASE			FP_GPIO_ESE_SFR_BASE
#define FP_GPIOCON_INIT_VALUE		0x2222 // MOSI|MISO|CS_N|CLK
#define FP_GPIODAT_INIT_VALUE		0x0000 // undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE		0x00FF // PU|PU|PU|PU
#define FP_GPIODRV_INIT_VALUE		0x0492 // 3x|3x|3x|3x
#define FP_GPIOCON_INIT_VALUE_OFF	0x0000 // INPUT|INPUT|INPUT|INPUT
#define FP_GPIODAT_INIT_VALUE_OFF	0x0000 // undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE_OFF	0x0055 // PD|PD|PD|PD
#define FP_GPIODRV_INIT_VALUE_OFF	0x0492 // 3x|3x|3x|3x
#define FP_GPIOCONPDN_VALUE			0x0020 // out0|input|out0|out0
#define FP_GPIOPUDPDN_VALUE			0x0010 // NP|PD|NP|NP
#define FP_GPIOCON_CSSET_VALUE		0x1011 // OUT|INPUT|OUT|OUT
#define FP_GPIOPUD_CSSET_VALUE		0x0051 // PD|PD|NP|PD
#define FP_GPIOCONPDN_CSHIGH_VALUE	0x0024 // out0|input|out1|out0

#elif defined(CONFIG_EXYNOS7870)
#define FP_GPIO_SFR_BASE			FP_GPIO_ESE_SFR_BASE
#define FP_GPIOCON_INIT_VALUE		0x02222 // INPUT|MOSI|MISO|CS_N|CLK
#define FP_GPIODAT_INIT_VALUE		0x00000 // undef|undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE		0x01FF // PD|PU|PU|PU|PU
#define FP_GPIODRV_INIT_VALUE		0x0080 // 1x|1x|3x|1x|1x
#define FP_GPIOCON_INIT_VALUE_OFF	0x00000 // INPUT|INPUT|INPUT|INPUT|INPUT
#define FP_GPIODAT_INIT_VALUE_OFF	0x00000 // undef|undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE_OFF	0x0155 // PD|PD|PD|PD|PD
#define FP_GPIODRV_INIT_VALUE_OFF	0x0492 // 1x|3x|3x|3x|3x
#define FP_GPIOCONPDN_VALUE			0x0220 // input|out0|input|out0|out0
#define FP_GPIOPUDPDN_VALUE			0x0110 // PD|NP|PD|NP|NP
#define FP_GPIOCON_CSSET_VALUE		0x1011 // INPUT|OUT|INPUT|OUT|OUT
#define FP_GPIOPUD_CSSET_VALUE		0x0151 // PD|PD|PD|NP|PD
#define FP_GPIOCONPDN_CSHIGH_VALUE	0x0224 // input|out0|input|out1|out0

#elif defined(CONFIG_EXYNOS7570)
#define FP_GPIO_SFR_BASE			FP_GPIO_ESE_SFR_BASE
#define FP_GPIOCON_INIT_VALUE		0x02222 // INPUT|MOSI|MISO|CS_N|CLK
#define FP_GPIODAT_INIT_VALUE		0x00000 // undef|undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE		0x01FF // PD|PU|PU|PU|PU
#define FP_GPIODRV_INIT_VALUE		0x0080 // 1x|1x|3x|1x|1x
#define FP_GPIOCON_INIT_VALUE_OFF	0x0000 // INPUT|INPUT|INPUT|INPUT|INPUT|
#define FP_GPIODAT_INIT_VALUE_OFF	0x0000 // undef|undef|undef|undef|undef
#define FP_GPIOPUD_INIT_VALUE_OFF	0x0155 // PD|PD|PD|PD|PD
#define FP_GPIODRV_INIT_VALUE_OFF	0x0000 // 1x|1x|1x|1x|1x
#define FP_GPIOCONPDN_VALUE			0x0220 // input|out0|input|out0|out0
#define FP_GPIOPUDPDN_VALUE			0x0110 // PD|NP|PD|NP|NP
#define FP_GPIOCON_CSSET_VALUE		0x1011 // INPUT|OUT|INPUT|OUT|OUT
#define FP_GPIOPUD_CSSET_VALUE		0x0151 // PD|PD|PD|NP|PD
#define FP_GPIOCONPDN_CSHIGH_VALUE	0x0224 // input|out0|input|out1|out0

#elif defined(CONFIG_EXYNOS7580)
#define FP_GPIO_SFR_BASE			FP_GPIO_ESE_SFR_BASE
#define FP_GPIOCON_INIT_VALUE		0x2222
#define FP_GPIODAT_INIT_VALUE		0x0000
#define FP_GPIOPUD_INIT_VALUE		0x00FF
#define FP_GPIODRV_INIT_VALUE		0x0200
#define FP_GPIOCONPDN_VALUE			0x0020
#define FP_GPIOPUDPDN_VALUE			0x0010

#elif defined(CONFIG_EXYNOS7420)
#define FP_GPIO_SFR_BASE			FP_GPIO_ESE_SFR_BASE
#define FP_GPIOCON_INIT_VALUE		0x12222
#define FP_GPIODAT_INIT_VALUE		0x00000
#define FP_GPIOPUD_INIT_VALUE		0x01FF
#define FP_GPIODRV_INIT_VALUE		0x02FF // 2x|4x|4x|4x|4x
#define FP_GPIOCONPDN_VALUE			0x0320
#define FP_GPIOPUDPDN_VALUE			0x0010
#define FP_GPIOCONPDN_CSHIGH_VALUE	0x0324 // out0|input|out1|out0
/* GPIO values without OCP_EN(in case OCP_EN is NC) */
#define FP_GPIOCON_WO_OCP			0x02222
#define FP_GPIOPUDPDN_WO_OCP		0x0110

#elif defined(CONFIG_EXYNOS5433) || defined(CONFIG_EXYNOS5430)
#if defined(CONFIG_EXYNOS5433)
#define FP_GPIO_SFR_BASE			FP_GPIO_FINGER_SFR_BASE
#else	/* CONFIG_EXYNOS5430 */
#define FP_GPIO_SFR_BASE			FP_GPIO_PERIC_SFR_BASE
#endif
#define FP_GPIOCON_INIT_VALUE		0x2222
#define FP_GPIODAT_INIT_VALUE		0x0000
#define FP_GPIOPUD_INIT_VALUE		0x0055
#define FP_GPIODRV_INIT_VALUE		0x2222
#define FP_GPIOCONPDN_VALUE			0x0020
#define FP_GPIOPUDPDN_VALUE			0x0010

#elif defined(CONFIG_EXYNOS5422) || defined(CONFIG_EXYNOS5420)
#define FP_GPIO_SFR_BASE			FP_GPIO_BLOCK_SFR_BASE
/* TODO : GPIO Control is needed for these chipsets? */
#endif

enum fp_test_case {
	FP_TEST_SPI_PROTECTION = 1,
	FP_TEST_GPIO_PROTECTION,
	FP_TEST_SET_GPIO_INIT,
	FP_TEST_SAVE_GPIO,
	FP_TEST_SAVE_GPIO_CS_HIGH,
	FP_TEST_RESOTRE_GPIO,
	FP_TEST_SET_SPI_CS,
};

#define FP_PROJECT_ZERO				1 //ZERO
#define FP_PROJECT_NOBLE_ZERO2		2 //NOBLE, ZERO2
#define FP_PROJECT_2016A			3 //A5XE, A7XE
#define FP_PROJECT_HERO				4 //HERO, HERO2
#define FP_PROJECT_GRACE			5 //GRACE
#define FP_PROJECT_A3Y17			6 //A3Y17
#define FP_PROJECT_A5Y17_A7Y17		7 //A5Y17, A7Y17
#define FP_PROJECT_DREAM			8 //DREAM

static int projectname = 0;

/* For TZPC */
uint32_t fp_set_tzpc_secure(fastcall_registers_t regs, uint32_t pin_conf);

/* GPIO */
uint32_t fp_set_gpio_init(fastcall_registers_t regs);
uint32_t fp_save_gpio_regs(fastcall_registers_t regs);
uint32_t fp_save_gpio_regs_cs_high(fastcall_registers_t regs);
uint32_t fp_restore_gpio_regs(fastcall_registers_t regs);
uint32_t fp_set_gpio_btp_ocp(fastcall_registers_t regs, uint32_t gpio_dat_bit);
uint32_t fp_disable_gpio_btp_ocp(fastcall_registers_t regs);
uint32_t fp_set_spi_cs(fastcall_registers_t regs);

uint32_t fp_test_fastcall_function(fastcall_registers_t regs);

#ifdef __cplusplus
}
#endif

#endif