/** * @file regs-cmu.h * @brief CMU register file for driver * * Copyright (c) 2012 Samsung Electronics Co., Ltd. */ #ifndef __REGS_CMU_H__ #define __REGS_CMU_H__ #if defined(CONFIG_EXYNOS5410) #define CMU_G2D_SFR_BASE 0x10018000 #define CMU_TOP_SFR_BASE 0x10020000 #define CMU_CDREX_SFR_BASE 0x10030000 #define CLK_GATE_IP_G2D (0x800) #define CLK_GATE_IP_GSC0 (0x910) #define CLK_GATE_IP_GSC1 (0x920) #define CLK_GATE_IP_DISP1 (0x928) #define CLK_GATE_IP_MFC (0x92C) #define CLK_GATE_IP_PERIS (0x960) #define CLK_GATE_BUS_CDREX (0x700) #elif defined(CONFIG_EXYNOS5420) || defined(CONFIG_EXYNOS5422) #define CMU_G2D_SFR_BASE 0x10018000 #define CMU_TOP_SFR_BASE 0x10020000 #define CMU_CDREX_SFR_BASE 0x10030000 #define CLK_SRC_TOP5 (0x214) #define CLK_GATE_BUS_G2D (0x700) #define CLK_GATE_IP_G2D (0x800) #define CLK_GATE_IP_GSCL0 (0x910) #define CLK_GATE_IP_GSCL1 (0x920) #define CLK_GATE_IP_DISP1 (0x928) #define CLK_GATE_IP_MFC (0x92C) #define CLK_GATE_IP_PERIS (0x960) #define CLK_GATE_BUS_CDREX (0x700) #define CLK_GATE_BUS_CDREX1 (0x704) #elif defined(CONFIG_EXYNOS5433) || defined(CONFIG_EXYNOS7420) || defined(CONFIG_EXYNOS7580) ||\ defined(CONFIG_EXYNOS7870) || defined(CONFIG_EXYNOS7880) || defined(CONFIG_EXYNOS7570) #define CMU_G2D_SFR_BASE 0x12460000 #define CMU_IMEM_SSS_SFR_BASE 0x11060000 #define CMU_TOP_SFR_BASE 0x10030000 #define CMU_MFC_SFR_BASE 0x15280000 #define CMU_HEVC_SFR_BASE 0x14F80000 #define CMU_GSCL_SFR_BASE 0x13CF0000 #define CMU_DISP_SFR_BASE 0x13B90000 #define CLK_GATE_IP_G2D0 (0xB00) #define CLK_GATE_IP_G2D1 (0xB04) #define CLK_GATE_IP_G2D_SMMU_G2D (0xB08) #define CLK_GATE_IP_IMEM_SSS (0xB0C) #define CLK_GATE_IP_IMEM_SMMU_SSS (0xB18) #define CLK_GATE_IP_IMEM_SLIM_SSS (0xB10) #define CLK_GATE_IP_IMEM_SMMU_SLIM_SSS (0xB1C) #define CLK_GATE_IP_MFC0 (0xB00) #define CLK_GATE_IP_MFC1 (0xB04) #define CLK_GATE_IP_SMMU_MFC (0xB08) #define CLK_GATE_IP_HEVC0 (0xB00) #define CLK_GATE_IP_HEVC1 (0xB04) #define CLK_GATE_IP_SMMU_HEVC (0xB08) #define CLK_GATE_IP_GSCL0 (0xB00) #define CLK_GATE_IP_GSCL1 (0xB04) #define CLK_GATE_IP_SMMU_GSCL0 (0xB08) #define CLK_GATE_IP_SMMU_GSCL1 (0xB0C) #define CLK_GATE_IP_SMMU_GSCL2 (0xB10) #define CLK_GATE_IP_DISP0 (0xB00) #define CLK_GATE_IP_DISP1 (0xB04) #define CLK_GATE_IP_PERIS0 (0xB00) #define CLK_GATE_IP_PERIS1 (0xB04) #elif defined(CONFIG_EXYNOS8890) || defined(CONFIG_EXYNOS8895) || defined(CONFIG_EXYNOS9810) ||\ defined(CONFIG_EXYNOS7885) #define CMU_G2D_SFR_BASE 0x12460000 #define CMU_DISP0_SFR_BASE 0x13AD0000 #define CMU_G3D_SFR_BASE 0x14AA0000 #define CMU_IMEM_ACLK_SSS_SFR_BASE 0x11060000 #define CMU_IMEM_PCLK_SSS_SFR_BASE 0x1106B000 #define CMU_TOP_SFR_BASE 0x10570000 #define CMU_MFC_SFR_BASE 0x15280000 #define CMU_MSCL_SFR_BASE 0x150D0000 #define CMU_DISP1_SFR_BASE 0x13F00000 #define CMU_RTC_SFR_BASE 0x10040000 #define CLK_RTC_ACLK (0x80C) #define CLK_RTC_PCLK (0x90C) #define CLK_RTC_SCLK (0xA0C) #define CLK_G2D_SFW_ACLK (0x818) #define CLK_G2D_SFW_PCLK (0x918) #define CLK_MSCL_ACLK (0x800) #define CLK_MSCL_PCLK (0x900) #define CLK_MSCL0_SFW_ACLK (0x808) #define CLK_MSCL0_SFW_PCLK (0x908) #define CLK_MSCL1_SFW_ACLK (0x810) #define CLK_MSCL1_SFW_PCLK (0x910) #define CLK_ENABLE_SCLK_MSCL (0xA00) #define CLK_IMEM_SSS_ACLK (0x80C) #define CLK_IMEM_SSS_PCLK (0x904) #define CLK_IMEM_SLIM_SSS_ACLK (0x810) #define CLK_IMEM_SLIM_SSS_PCLK (0x910) #define CLK_MFC_ACLK (0x800) #define CLK_MFC0_SFW_ACLK (0x808) #define CLK_MFC1_SFW_ACLK (0x810) #define CLK_MFC_PCLK (0x900) #define CLK_MFC0_SFW_PCLK (0x908) #define CLK_MFC1_SFW_PCLK (0x910) #define CLK_DISP0_ACLK (0x800) #define CLK_DISP0_RO_SFW_ACLK (0x80C) #define CLK_DISP0_RW_SFW_ACLK (0x810) #define CLK_DISP0_PCLK (0x900) #define CLK_DISP0_RO_SFW_PCLK (0x90C) #define CLK_DISP0_RW_SFW_PCLK (0x910) #define CLK_DISP1_ACLK (0x800) #define CLK_DISP1_PCLK (0x900) #define CLK_G3D_SFW_ACLK (0x800) #define CLK_G3D_SFW_PCLK (0x900) #endif #endif /* __REGS_CMU_H__ */