/** * @file gpio-mst.h * @brief Contains common definitions for GPIO control * * Copyright (c) 2014 Samsung Electronics Co., Ltd. */ #ifndef __REGS_GPIO_MST_H__ #define __REGS_GPIO_MST_H__ #define VA_GPJ0 (0x81000) #define VA_GPJ1 (0x82000) #define VA_GPF3 (0x83000) #define VA_CMU_PERIC1 (0x84000) #define VA_TZPC13 (0x85000) #define TRACK_DATA (0x86000) #define VA_TZPC_PERIC (0x87000) //MST_EN #if defined(CONFIG_EXYNOS7420) #define GPJ0_BASE (0x14CD0000) #elif defined(CONFIG_EXYNOS7580) #define GPJ0_BASE (0x138D0000) #elif defined(CONFIG_EXYNOS7870) #define GPJ0_BASE (0x139D0000) #elif defined(CONFIG_EXYNOS7880) #define GPJ0_BASE (0x139D0000) #elif defined(CONFIG_EXYNOS7885) #define GPJ0_BASE (0x139B0000) #elif defined(CONFIG_EXYNOS8890) #define GPJ0_BASE (0x14CD0000) #elif defined(CONFIG_EXYNOS8895) #define GPJ0_BASE (0x10980000) #elif defined(CONFIG_EXYNOS9810) #define GPJ0_BASE (0x13A80000) #endif #if defined(CONFIG_EXYNOS8895) #define GPJ0CON (0x160) #define GPJ0DAT (0x164) #define GPJ0PUD (0x168) #define GPJ0DRV_SR (0x16C) #define GPJ0CON_PDN (0x170) #define GPJ0PUD_PDN (0x174) #elif defined(CONFIG_EXYNOS9810) #define GPJ0CON (0x00) #define GPJ0DAT (0x04) #define GPJ0PUD (0x08) #define GPJ0DRV_SR (0x0C) #define GPJ0CON_PDN (0x10) #define GPJ0PUD_PDN (0x14) #elif defined(CONFIG_EXYNOS7885) #define GPJ0CON (0xE0) #define GPJ0DAT (0xE4) #define GPJ0PUD (0xE8) #define GPJ0DRV_SR (0xEC) #define GPJ0CON_PDN (0xF0) #define GPJ0PUD_PDN (0xF4) #else #define GPJ0CON (0x0) #define GPJ0DAT (0x4) #define GPJ0PUD (0x8) #define GPJ0DRV_SR (0xC) #define GPJ0CON_PDN (0x10) #define GPJ0PUD_PDN (0x14) #endif #define EXT_INT40_CON (0x700) #define EXT_INT40_FLTCON0 (0x800) #define EXT_INT40_FLTCON1 (0x804) #define EXT_INT40_MASK (0x900) #define EXT_INT40_PEND (0xA00) #define EXT_INT_GRPPRI (0xB00) #define EXT_INT_PRIORITY (0xB04) #define EXT_INT_SERVICE (0xB08) #define EXT_INT_SERVICE_PEND (0xB0C) #define EXT_INT_GRPFIXPRI (0xB10) #define EXT_INT40_FIXPRI (0xB14) //MST_DATA #if defined(CONFIG_EXYNOS7420) #define GPJ1_BASE (0x14CE0000) #elif defined(CONFIG_EXYNOS7580) #define GPJ1_BASE (0x138D0000) #elif defined(CONFIG_EXYNOS7870) #define GPJ1_BASE (0x139D0000) #elif defined(CONFIG_EXYNOS7880) #define GPJ1_BASE (0x139D0000) #elif defined(CONFIG_EXYNOS7885) #define GPJ1_BASE (0x139B0000) #elif defined(CONFIG_EXYNOS8890) #define GPJ1_BASE (0x14CE0000) #elif defined(CONFIG_EXYNOS8895) #define GPJ1_BASE (0x10980000) #elif defined(CONFIG_EXYNOS9810) #define GPJ1_BASE (0x13A80000) #endif #if defined(CONFIG_EXYNOS8895) #define GPJ1CON (0x160) #define GPJ1DAT (0x164) #define GPJ1PUD (0x168) #define GPJ1DRV_SR (0x16C) #define GPJ1CON_PDN (0x170) #define GPJ1PUD_PDN (0x174) #elif defined(CONFIG_EXYNOS9810) #define GPJ1CON (0x00) #define GPJ1DAT (0x04) #define GPJ1PUD (0x08) #define GPJ1DRV_SR (0x0C) #define GPJ1CON_PDN (0x10) #define GPJ1PUD_PDN (0x14) #elif defined(CONFIG_EXYNOS7885) #define GPJ1CON (0x80) #define GPJ1DAT (0x84) #define GPJ1PUD (0x88) #define GPJ1DRV_SR (0x8C) #define GPJ1CON_PDN (0x90) #define GPJ1PUD_PDN (0x94) #else #define GPJ1CON (0x0) #define GPJ1DAT (0x4) #define GPJ1PUD (0x8) #define GPJ1DRV_SR (0xC) #define GPJ1CON_PDN (0x10) #define GPJ1PUD_PDN (0x14) #endif //MST_PWR_EN #if defined(CONFIG_EXYNOS7420) #define GPF3_BASE (0x14870000) #define GPF3CON (0x80) #define GPF3DAT (0x84) #define GPF3PUD (0x88) #define GPF3DRV_SR (0x8C) #define GPF3CON_PDN (0x90) #define GPF3PUD_PDN (0x94) #elif defined(CONFIG_EXYNOS7580) #define GPF3_BASE (0x139C0000) #define GPF3CON (0x120) #define GPF3DAT (0x124) #define GPF3PUD (0x128) #define GPF3DRV_SR (0x12C) #define GPF3CON_PDN (0x130) #define GPF3PUD_PDN (0x134) #elif defined(CONFIG_EXYNOS7870) #define GPF3_BASE (0x139B0000) #define GPF3CON (0x120) #define GPF3DAT (0x124) #define GPF3PUD (0x128) #define GPF3DRV_SR (0x12C) #define GPF3CON_PDN (0x130) #define GPF3PUD_PDN (0x134) #elif defined(CONFIG_EXYNOS7880) #define GPF3_BASE (0x139B0000) #define GPF3CON (0x240) #define GPF3DAT (0x244) #define GPF3PUD (0x248) #define GPF3DRV_SR (0x24C) #define GPF3CON_PDN (0x250) #define GPF3PUD_PDN (0x254) #elif defined(CONFIG_EXYNOS7885) #define GPF3_BASE (0x139B0000) #define GPF3CON (0x180) #define GPF3DAT (0x184) #define GPF3PUD (0x188) #define GPF3DRV_SR (0x18C) #define GPF3CON_PDN (0x190) #define GPF3PUD_PDN (0x194) #elif defined(CONFIG_EXYNOS8890) #define GPF3_BASE (0x10E60000) #define GPF3CON (0x0) #define GPF3DAT (0x4) #define GPF3PUD (0x8) #define GPF3DRV_SR (0xC) #define GPF3CON_PDN (0x10) #define GPF3PUD_PDN (0x14) #elif defined(CONFIG_EXYNOS8895) #define GPF3_BASE (0x10980000) #define GPF3CON (0x160) #define GPF3DAT (0x164) #define GPF3PUD (0x168) #define GPF3DRV_SR (0x16C) #define GPF3CON_PDN (0x170) #define GPF3PUD_PDN (0x174) #elif defined(CONFIG_EXYNOS9810) #define GPF3_BASE (0x10830000) #define GPF3CON (0xC0) #define GPF3DAT (0xC4) #define GPF3PUD (0xC8) #define GPF3DRV_SR (0xCC) #define GPF3CON_PDN (0xD0) #define GPF3PUD_PDN (0xD4) #endif #define PERIC1_BASE (0x14c80000) #define PCLK_PERIC1 (0x900) #define PCLK_GPIO_NFC_ENABLE (1 << 24) #define PCLK_GPIO_TOUCH_ENABLE (1 << 25) /* CON */ #define CON_INPUT (0x0) #define CON_OUTPUT (0x1) #define CON_FUNC (0x2) #define CON0_SET(x) ((x) << (0)) #define CON1_SET(x) ((x) << (4)) #define CON2_SET(x) ((x) << (8)) #define CON3_SET(x) ((x) << (12)) #define CON4_SET(x) ((x) << (16)) #define CON5_SET(x) ((x) << (20)) #define CON6_SET(x) ((x) << (24)) #define CON7_SET(x) ((x) << (28)) /* DAT */ #define HIGH (1) #define LOW (0) #define DAT0_SET(x) ((x) << (0)) #define DAT1_SET(x) ((x) << (1)) #define DAT2_SET(x) ((x) << (2)) #define DAT3_SET(x) ((x) << (3)) #define DAT4_SET(x) ((x) << (4)) #define DAT5_SET(x) ((x) << (5)) #define DAT6_SET(x) ((x) << (6)) #define DAT7_SET(x) ((x) << (7)) #define DAT0_GET(x) (((x) << (0)) >> (0)) #define DAT1_GET(x) (((x) << (1)) >> (1)) #define DAT2_GET(x) (((x) << (2)) >> (2)) #define DAT3_GET(x) (((x) << (3)) >> (3)) #define DAT4_GET(x) (((x) << (4)) >> (4)) #define DAT5_GET(x) (((x) << (5)) >> (5)) #define DAT6_GET(x) (((x) << (6)) >> (6)) #define DAT7_GET(x) (((x) << (7)) >> (7)) /* PUD & PUDPDN */ #define PULL_DISABLED (0x0) #define PULL_DOWN (0x1) #define PULL_UP (0x3) #define PUD0_SET(x) ((x) << (0)) #define PUD1_SET(x) ((x) << (2)) #define PUD2_SET(x) ((x) << (4)) #define PUD3_SET(x) ((x) << (6)) #define PUD4_SET(x) ((x) << (8)) #define PUD5_SET(x) ((x) << (10)) #define PUD6_SET(x) ((x) << (12)) #define PUD7_SET(x) ((x) << (14)) /* DRV SR */ #define DRV_1X (0x0) #define DRV_2X (0x2) #define DRV_3X (0x1) #define DRV_4X (0x3) #define FAST_SLEW_RATE (0x0) #define SLOW_SLEW_RATE (0x1) #define DRV_SR0_SET(x,y) (((x) << (0)) || ((y) << (16))) #define DRV_SR1_SET(x,y) (((x) << (2)) || ((y) << (17))) #define DRV_SR2_SET(x,y) (((x) << (4)) || ((y) << (18))) /* CONPDN */ #define OUTPUT_0 (0x0) #define OTUPUT_1 (0x1) #define INPUT (0x2) #define PREVIOUS_STATE (0x3) #define CONPDN0_SET(x) ((x) << (0)) #define CONPDN1_SET(x) ((x) << (2)) #define CONPDN2_SET(x) ((x) << (4)) #define CONPDN3_SET(x) ((x) << (6)) #define CONPDN4_SET(x) ((x) << (8)) #define CONPDN5_SET(x) ((x) << (10)) #define CONPDN6_SET(x) ((x) << (12)) #define CONPDN7_SET(x) ((x) << (14)) /* TZPC Access Control */ #if defined(CONFIG_EXYNOS7420) #define TZPC13_BASE 0x10080000 #define DECPROT0STAT 0x800 #define DECPROT0SET 0x804 #define DECPROT0CLR 0x808 #elif defined(CONFIG_EXYNOS7580) #define TZPC13_BASE 0x10130000 // TZPC3 BASE #define DECPROT0STAT 0x80C // DECPROT1Stat #define DECPROT0SET 0x810 // DECPROT1Set #define DECPROT0CLR 0x814 // DECPROT1Clr #elif defined(CONFIG_EXYNOS7870) || defined(CONFIG_EXYNOS7880) #define TZPC13_BASE 0x10040000 // TZPC4 BASE #define DECPROT0STAT 0x800 //DECPROT0Stat #define DECPROT0SET 0x804 //DECPROT0Set #define DECPROT0CLR 0x808 //DECPROT0Clr #elif defined(CONFIG_EXYNOS7885) /* TZPC_PERIC 0x139B0000 OFFSET 0x2004 Because of 4KB mapping, TZPC_PERIC_BASE should be 0x139B2000 */ #define TZPC_PERIC_BASE 0x139B2000 #define MST_OFFSET 0x4 #elif defined(CONFIG_EXYNOS8890) #define TZPC13_BASE 0x100E0000 // TZPC11 BASE #define DECPROT0STAT 0x80C // DECPROT1Stat #define DECPROT0SET 0x810 // DECPROT1Set #define DECPROT0CLR 0x814 // DECPROT1Clr #elif defined(CONFIG_EXYNOS8895) //need to be fixed /* TZPC_PERIC1_2 0x10980000 OFFSET 0x2008 Because of 4KB mapping, TZPC_PERIC_BASE should be 0x10982000 */ #define TZPC_PERIC_BASE 0x10982000 #define MST_OFFSET 0x8 #elif defined(CONFIG_EXYNOS9810) // todo!!! /* TZPC_PERIC 0x13A80000 OFFSET 0x2000 Because of 4KB mapping, TZPC_PERIC_BASE should be 0x13A82000 */ #define TZPC_PERIC_BASE 0x13A82000 #define MST_OFFSET 0x0 #endif #define GPIO_NFC (1 << 5) #define GPIO_TOUCH (1 << 6) #if defined(CONFIG_EXYNOS7420) #define GPIO_MST (1 << 0) // to avoid build error #elif defined(CONFIG_EXYNOS7580) #define GPIO_MST (1 << 3) //GPIO_TOUCH[3] #elif defined(CONFIG_EXYNOS7870) || defined(CONFIG_EXYNOS7880) #define GPIO_MST (1 << 2) //GPIO_TOUCH[2] #elif defined(CONFIG_EXYNOS7885) #define GPIO_MST_EN (1 << 28) #define GPIO_MST_DATA (1 << 2) #elif defined(CONFIG_EXYNOS8890) #define GPIO_MST (1 << 3) //GPIO_NFC[3] #elif defined(CONFIG_EXYNOS8895) #define GPIO_MST_EN (1 << 25) #define GPIO_MST_DATA (1 << 26) #elif defined(CONFIG_EXYNOS9810) // todo!!! #define GPIO_MST_EN (1 << 7) #define GPIO_MST_DATA (1 << 6) #endif #define GPIO_MST_NUM 2 #define GPIO_MST_REG_NUM 17 static unsigned int gpio_offset[17] = { 0x0, /* con */ 0x4, /* dat */ 0x8, /* pud */ 0xC, /* drv_sr */ 0x10, /* con_pdn */ 0x14, /* pud_pdn */ 0x700, /* ext_int_con */ 0x800, /* ext_int_fltcon0 */ 0x804, /* ext_int_fltcon1 */ 0x900, /* ext_int_mask */ 0xA00, /* ext_int_pend */ 0xB00, /* ext_int_grppri */ 0xB04, /* ext_int_priority */ 0xB08, /* ext_int_service */ 0xB0C, /* ext_int_service_pend */ 0xB10, /* ext_int_grpfixpri */ 0xB14 /* ext_int_fixpri */ }; #endif /* __REGS_GPIO_MST_H__ */