/** * @file regs-tzasc.h * @brief TZASC register file for driver * * Copyright (c) 2012 Samsung Electronics Co., Ltd. */ #ifndef __REGS_TZASC_H__ #define __REGS_TZASC_H__ #if defined(CONFIG_4X12) #define TZASC0_SFR_BASE 0x10700000 #elif defined(CONFIG_EXYNOS5410) || defined(CONFIG_EXYNOS5420) || defined(CONFIG_EXYNOS5422) #define TZASC0_SFR_BASE 0x10D40000 #elif defined(CONFIG_EXYNOS5260) #define TZASC0_SFR_BASE 0x10C40000 #elif defined(CONFIG_EXYNOS5430) || defined(CONFIG_EXYNOS5433)|| defined(CONFIG_EXYNOS3475) #define TZASC0_SFR_BASE 0x10410000 #elif defined(CONFIG_EXYNOS3470) #define TZASC0_SFR_BASE 0x10700000 #elif defined(CONFIG_EXYNOS3472) || defined(CONFIG_EXYNOS3250) #define TZASC0_SFR_BASE 0x10600000 #elif defined(CONFIG_EXYNOS4415) #define TZASC0_SFR_BASE 0x10520000 #elif defined(CONFIG_EXYNOS7420) || defined(CONFIG_EXYNOS8890) #define TZASC0_SFR_BASE 0x10810000 #elif defined(CONFIG_EXYNOS7580) || defined(CONFIG_EXYNOS7880) || defined(CONFIG_EXYNOS7885) #define TZASC0_SFR_BASE 0x10410000 #elif defined(CONFIG_EXYNOS7870) || defined(CONFIG_EXYNOS7570) #define TZASC0_SFR_BASE 0x10420000 #elif defined(CONFIG_EXYNOS8895) #define TZASC0_SFR_BASE 0x16040000 #elif defined(CONFIG_EXYNOS9810) #define TZASC0_SFR_BASE 0x1B840000 #endif #define TZ_CONFIGURATION 0x000 #define TZ_ACTION 0x004 #define TZ_LD_RANGE 0x008 #define TZ_LD_SELECT 0x00C #define TZ_INT_STATUS 0x010 #define TZ_INT_CLEAR 0x014 #define TZ_FAIL_ADDR_LOW_R0 0x040 #define TZ_FAIL_ADDR_HIGH_R0 0x044 #define TZ_FAIL_CTRL_R0 0x048 #define TZ_FAIL_ID_R0 0x04C #define TZ_FAIL_ADDR_LOW_W0 0x050 #define TZ_FAIL_ADDR_HIGH_W0 0x054 #define TZ_FAIL_CTRL_W0 0x058 #define TZ_FAIL_ID_W0 0x05C #define TZ_FAIL_ADDR_LOW_R1 0x060 #define TZ_FAIL_ADDR_HIGH_R1 0x064 #define TZ_FAIL_CTRL_R1 0x068 #define TZ_FAIL_ID_R1 0x06C #define TZ_FAIL_ADDR_LOW_W1 0x070 #define TZ_FAIL_ADDR_HIGH_W1 0x074 #define TZ_FAIL_CTRL_W1 0x078 #define TZ_FAIL_ID_W1 0x07C #define TZ_FAIL_ADDR_LOW_R2 0x080 #define TZ_FAIL_ADDR_HIGH_R2 0x084 #define TZ_FAIL_CTRL_R2 0x088 #define TZ_FAIL_ID_R2 0x08C #define TZ_FAIL_ADDR_LOW_W2 0x090 #define TZ_FAIL_ADDR_HIGH_W2 0x094 #define TZ_FAIL_CTRL_W2 0x098 #define TZ_FAIL_ID_W2 0x09C #define TZ_FAIL_ADDR_LOW_R2 0x080 #define TZ_FAIL_ADDR_HIGH_R2 0x084 #define TZ_FAIL_CTRL_R2 0x088 #define TZ_FAIL_ID_R2 0x08C #define TZ_FAIL_ADDR_LOW_W2 0x090 #define TZ_FAIL_ADDR_HIGH_W2 0x094 #define TZ_FAIL_CTRL_W2 0x098 #define TZ_FAIL_ID_W2 0x09C #if defined(CONFIG_EXYNOS8890) || defined(CONFIG_EXYNOS8895) || defined(CONFIG_EXYNOS9810) #define TZRS_LOW0 0x500 #elif defined(CONFIG_EXYNOS7885) #define TZRS_LOW0 0x100 #else #define TZRS_LOW0 0x100 #endif #define TZRS_LOW1 0x110 #define TZRS_LOW2 0x120 #define TZRS_LOW3 0x130 #define TZRS_LOW4 0x140 #define TZRS_LOW5 0x150 #define TZRS_LOW6 0x160 #define TZRS_LOW7 0x170 #define TZRS_LOW8 0x180 #define TZRS_HIGH0 0x104 #define TZRS_HIGH1 0x114 #define TZRS_HIGH2 0x124 #define TZRS_HIGH3 0x134 #define TZRS_HIGH4 0x144 #define TZRS_HIGH5 0x154 #define TZRS_HIGH6 0x164 #define TZRS_HIGH7 0x174 #define TZRS_HIGH8 0x184 #define TZRS_ATTR0 0x108 #define TZRS_ATTR1 0x118 #define TZRS_ATTR2 0x128 #define TZRS_ATTR3 0x138 #define TZRS_ATTR4 0x148 #define TZRS_ATTR5 0x158 #define TZRS_ATTR6 0x168 #define TZRS_ATTR7 0x178 #define TZRS_ATTR8 0x188 #define TZ_ITCRG 0xE00 #define TZ_ITIP 0xE04 #define TZ_ITOP 0xE08 /* Configuration */ #define TZ_ADDR_WIDTH_35BIT (0x22 << 8) #define TZ_REGION_9 (0x8 << 0) /* Action */ #define TZ_REACT_LOW_OKAY (0x0 << 0) #define TZ_REACT_LOW_DECERR (0x1 << 0) #define TZ_REACT_HIGH_OKAY (0x2 << 0) #define TZ_REACT_HIGH_DECERR (0x3 << 0) /* lockdown range */ #define TZ_LD_ENABLE (0x1 << 31) #define TZ_LD_DISABLE (0x0 << 31) #define TZ_LD_REGION_0 (0x0 << 0) #define TZ_LD_REGION_1 (0x1 << 0) #define TZ_LD_REGION_2 (0x2 << 0) #define TZ_LD_REGION_3 (0x3 << 0) #define TZ_LD_REGION_4 (0x4 << 0) #define TZ_LD_REGION_5 (0x5 << 0) #define TZ_LD_REGION_6 (0x6 << 0) #define TZ_LD_REGION_7 (0x7 << 0) #define TZ_LD_REGION_8 (0x8 << 0) /* lockdown select */ #define TZ_LD_RANGE_RO (0x1 << 0) #define TZ_LD_RANGE_RW (0x0 << 0) /* int status - read only */ #define TZ_OVERRUN_W3 (0x1 << 15) #define TZ_STATUS_W3 (0x1 << 14) #define TZ_OVERRUN_R3 (0x1 << 13) #define TZ_STATUS_R3 (0x1 << 12) #define TZ_OVERRUN_W2 (0x1 << 11) #define TZ_STATUS_W2 (0x1 << 10) #define TZ_OVERRUN_R2 (0x1 << 9) #define TZ_STATUS_R2 (0x1 << 8) #define TZ_OVERRUN_W1 (0x1 << 7) #define TZ_STATUS_W1 (0x1 << 6) #define TZ_OVERRUN_R1 (0x1 << 5) #define TZ_STATUS_R1 (0x1 << 4) #define TZ_OVERRUN_W0 (0x1 << 3) #define TZ_STATUS_W0 (0x1 << 2) #define TZ_OVERRUN_R0 (0x1 << 1) #define TZ_STATUS_R0 (0x1 << 0) /* fail control */ #define TZ_FAIL_CNTL_WRITE_ACCESS (0x1 << 24) #define TZ_FAIL_NON_SECURE_ACCESS (0x1 << 21) #define TZ_FAIL_PRIVILEGED_ACCESS (0x1 << 20) /* region setup */ #define TZ_BASE_ADDRESS_MASK (0xFFFF << 16) /* region attribute */ #define TZ_AP_SHIFT (28) #define TZ_SIZE_SHIFT (4) #define TZ_SUBREGION_SHIFT (8) #define TZ_REGION_ENABLE (0x1 << 0) #define TZ_REGION_DISABLE (0x0 << 0) #define TZ_MIN_REGION_SIZE_SHIFT (16) /* 64KB */ #if defined(CONFIG_EXYNOS3472) || defined(CONFIG_EXYNOS7580) || defined(CONFIG_EXYNOS3475) ||\ defined(CONFIG_EXYNOS3250) || defined(CONFIG_EXYNOS8890) || defined(CONFIG_EXYNOS7870) ||\ defined(CONFIG_EXYNOS7570) || defined(CONFIG_EXYNOS8895) || defined(CONFIG_EXYNOS9810) #define TZ_INTERLEAVING_SHIFT (0) /* 1 channels */ #elif defined(CONFIG_EXYNOS7880) || defined(CONFIG_EXYNOS7885) #define TZ_INTERLEAVING_SHIFT (1) /* 2 channels */ #elif defined(CONFIG_EXYNOS7420) #define TZ_INTERLEAVING_SHIFT (2) /* 4 channels */ #else #define TZ_INTERLEAVING_SHIFT (1) /* 2 channels */ #endif #define TZ_INTERLEAVING_SHIFT2 (12) /* integration test logic */ #define TZ_ITCRG_ENABLE (0x1 << 0) #define TZ_ITCRG_DISABLE (0x0 << 0) /* itip secure boot lock - Read only */ #define TZ_ITIP_SEC_BOOT_LOCK (0x1 << 0) /* itop secure boot lock - Read only */ #define TZ_ITOP_SEC_BOOT_LOCK (0x1 << 0) #define TZASC_64KB_SHIFT 16 #define TZASC_SIZE_ALIGN (1 << TZASC_64KB_SHIFT) #define TZASC_BASE_ALIGN (1 << TZASC_64KB_SHIFT) #endif /* __REGS_TZASC_H__ */