/** * @file gpio-mst.h * @brief Contains common definitions for GPIO control * * Copyright (c) 2020 Samsung Electronics Co., Ltd. */ // [ EXYNOS Chipset #if defined(EXYNOS) #ifdef S5E8825 /* MST_EN*/ #define MST_EN_BASE (0x10040000) #define EN_CON (0x40) #define EN_DAT (0x44) #define EN_PUD (0x48) #define EN_DRV (0x4C) /* MST_DATA */ #define MST_DATA_BASE (0x10040000) #define DATA_CON (0x40) #define DATA_DAT (0x44) #define DATA_PUD (0x48) #define DATA_DRV (0x4C) #elif S5E9925 /* MST_EN*/ #define MST_EN_BASE (0x14E30000) #define EN_CON (0x20) #define EN_DAT (0x24) #define EN_PUD (0x28) #define EN_DRV (0x2C) /* MST_DATA */ #define MST_DATA_BASE (0x14E30000) #define DATA_CON (0x20) #define DATA_DAT (0x24) #define DATA_PUD (0x28) #define DATA_DRV (0x2C) #elif EXYNOS2100 /* MST_EN*/ #define MST_EN_BASE (0x10430000) #define EN_CON (0x100) #define EN_DAT (0x104) #define EN_PUD (0x108) #define EN_DRV (0x10c) /* MST_DATA */ #define MST_DATA_BASE (0x10430000) #define DATA_CON (0x100) #define DATA_DAT (0x104) #define DATA_PUD (0x108) #define DATA_DRV (0x10c) #elif EXYNOS9830 /* MST_EN*/ #define MST_EN_BASE (0x10730000) #define EN_CON (0x40) #define EN_DAT (0x44) #define EN_PUD (0x48) #define EN_DRV (0x4c) /* MST_DATA */ #define MST_DATA_BASE (0x10730000) #define DATA_CON (0x40) #define DATA_DAT (0x44) #define DATA_PUD (0x48) #define DATA_DRV (0x4c) #elif EXYNOS9820 /* MST_EN*/ #define MST_EN_BASE (0x10830000) #define EN_CON (0x00) #define EN_DAT (0x04) #define EN_PUD (0x08) #define EN_DRV (0x0C) /* MST_DATA */ #define MST_DATA_BASE (0x10830000) #define DATA_CON (0x00) #define DATA_DAT (0x04) #define DATA_PUD (0x08) #define DATA_DRV (0x0C) #elif EXYNOS7904 #ifdef A30 /* MST_EN*/ #define MST_EN_BASE (0x139B0000) #define EN_CON (0x140) #define EN_DAT (0x144) #define EN_PUD (0x148) #define EN_DRV (0x14C) /* MST_DATA */ #define MST_DATA_BASE (0x139B0000) #define DATA_CON (0x140) #define DATA_DAT (0x144) #define DATA_PUD (0x148) #define DATA_DRV (0x14C) #else /* A40 */ /* MST_EN*/ #define MST_EN_BASE (0x13430000) #define EN_CON (0x40) #define EN_DAT (0x44) #define EN_PUD (0x48) #define EN_DRV (0x4C) /* MST_DATA */ #define MST_DATA_BASE (0x13430000) #define DATA_CON (0x40) #define DATA_DAT (0x44) #define DATA_PUD (0x48) #define DATA_DRV (0x4C) #endif #elif EXYNOS9630 /* MST_EN*/ #define MST_EN_BASE (0x10040000) #define EN_CON (0x40) #define EN_DAT (0x44) #define EN_PUD (0x48) #define EN_DRV (0x4C) /* MST_DATA */ #define MST_DATA_BASE (0x10040000) #define DATA_CON (0x40) #define DATA_DAT (0x44) #define DATA_PUD (0x48) #define DATA_DRV (0x4C) #elif EXYNOS9610 /* MST_EN*/ #define MST_EN_BASE (0x11C20000) #define EN_CON (0x1C0) #define EN_DAT (0x1C4) #define EN_PUD (0x1C8) #define EN_DRV (0x1CC) /* MST_DATA */ #define MST_DATA_BASE (0x11C20000) #define DATA_CON (0x1A0) #define DATA_DAT (0x1A4) #define DATA_PUD (0x1A8) #define DATA_DRV (0x1AC) #else //TBD for next chipset #endif // ] /* CON */ #define CON_INPUT (0x0) #define CON_OUTPUT (0x1) #define CON_FUNC (0x2) #define CON0_SET(x) ((x) << (0)) #define CON1_SET(x) ((x) << (4)) #define CON2_SET(x) ((x) << (8)) #define CON3_SET(x) ((x) << (12)) #define CON4_SET(x) ((x) << (16)) #define CON5_SET(x) ((x) << (20)) #define CON6_SET(x) ((x) << (24)) #define CON7_SET(x) ((x) << (28)) /* DAT */ #define DAT0_SET(x) ((x) << (0)) #define DAT1_SET(x) ((x) << (1)) #define DAT2_SET(x) ((x) << (2)) #define DAT3_SET(x) ((x) << (3)) #define DAT4_SET(x) ((x) << (4)) #define DAT5_SET(x) ((x) << (5)) #define DAT6_SET(x) ((x) << (6)) #define DAT7_SET(x) ((x) << (7)) #define DAT0_GET(x) (((x) << (0)) >> (0)) #define DAT1_GET(x) (((x) << (1)) >> (1)) #define DAT2_GET(x) (((x) << (2)) >> (2)) #define DAT3_GET(x) (((x) << (3)) >> (3)) #define DAT4_GET(x) (((x) << (4)) >> (4)) #define DAT5_GET(x) (((x) << (5)) >> (5)) #define DAT6_GET(x) (((x) << (6)) >> (6)) #define DAT7_GET(x) (((x) << (7)) >> (7)) /* PUD & PUDPDN */ #define PULL_DISABLED (0x0) #define PULL_DOWN (0x1) #define PULL_UP (0x3) #define PUD0_SET(x) ((x) << (0)) #define PUD1_SET(x) ((x) << (4)) #define PUD2_SET(x) ((x) << (8)) #define PUD3_SET(x) ((x) << (12)) #define PUD4_SET(x) ((x) << (16)) #define PUD5_SET(x) ((x) << (20)) #define PUD6_SET(x) ((x) << (24)) #define PUD7_SET(x) ((x) << (28)) /* CONPDN */ #define OUTPUT_0 (0x0) #define OTUPUT_1 (0x1) #define INPUT (0x2) #define PREVIOUS_STATE (0x3) #define CONPDN0_SET(x) ((x) << (0)) #define CONPDN1_SET(x) ((x) << (2)) #define CONPDN2_SET(x) ((x) << (4)) #define CONPDN3_SET(x) ((x) << (6)) #define CONPDN4_SET(x) ((x) << (8)) #define CONPDN5_SET(x) ((x) << (10)) #define CONPDN6_SET(x) ((x) << (12)) #define CONPDN7_SET(x) ((x) << (14)) #elif defined(MTK) // [ MTK Chipset // ------------------------------------------------------------------------------------------------------------------------------ /* CON */ #define CON_INPUT (0x0) #define CON_OUTPUT (0x1) #define CON_FUNC (0x2) #define CON_SET(x, offset) ((x) << (offset)) #define DAT_SET(x, offset) ((x) << (offset)) #ifdef MT6769T /* MT6769T Base Address */ // Copied from //RIO/Mojito/Common/android/vendor/mediatek/proprietary/trustzone/atf/v1.6/plat/mediatek/mt6768/include/platform_def.h #define IO_PHYS 0x10000000 #define GPIO_BASE (IO_PHYS + 0x00005000) // Copied from //RIO/Mojito/Common/android/vendor/mediatek/proprietary/custom/Customization_Kit_buildspec/Raphael-da/platform/MT6768/inc/register_base.h /* MST_EN (gpio21)*/ #define MST_EN_BASE GPIO_BASE #define EN_CON (0x000) #define EN_DAT (0x100) #define EN_PUD (0x2230) //dummy #define EN_DRV (0x10c) // dummy /* MST_DATA (gpio23)*/ #define MST_DATA_BASE GPIO_BASE #define DATA_CON (0x000) #define DATA_DAT (0x100) #define DATA_PUD (0x2230) // dummy #define DATA_DRV (0x10c) // dummy #define CON_EN_OFFSET 21 // EN #define DAT_EN_OFFSET 21 #define CON_DATA_OFFSET 23 // DATA #define DAT_DATA_OFFSET 23 #elif MT6853 /* MT6853 Base Address */ #define IO_PHYS 0x10000000 #define GPIO_BASE (IO_PHYS + 0x00005000) /* MST_EN (gpio40)*/ #define MST_EN_BASE GPIO_BASE #define EN_CON (0x010) #define EN_DAT (0x110) #define EN_PUD (0x0050) //dummy #define EN_DRV (0x0000) // dummy /* MST_DATA (gpio39)*/ #define MST_DATA_BASE GPIO_BASE #define DATA_CON (0x010) #define DATA_DAT (0x110) #define DATA_PUD (0x0050) // dummy #define DATA_DRV (0x0000) // dummy #define CON_DATA_OFFSET 7 // DATA #define DAT_DATA_OFFSET 7 #define CON_EN_OFFSET 8 // EN #define DAT_EN_OFFSET 8 #elif MT6833 /* MT6833 Base Address */ #define IO_PHYS 0x10000000 #define GPIO_BASE (IO_PHYS + 0x00005000) /* MST_EN (gpio58)*/ #define MST_EN_BASE GPIO_BASE #define EN_CON (0x010) #define EN_DAT (0x110) #define EN_PUD (0x0050) //dummy #define EN_DRV (0x0000) // dummy /* MST_DATA (gpio56)*/ #define MST_DATA_BASE GPIO_BASE #define DATA_CON (0x010) #define DATA_DAT (0x110) #define DATA_PUD (0x0050) // dummy #define DATA_DRV (0x0000) // dummy #define CON_DATA_OFFSET 24 // DATA #define DAT_DATA_OFFSET 24 #define CON_EN_OFFSET 26 // EN #define DAT_EN_OFFSET 26 #elif MT6877 /* MT6877 Base Address */ #define IO_PHYS 0x10000000 #define GPIO_BASE (IO_PHYS + 0x00005000) /* MST_EN (gpio139)*/ #define MST_EN_BASE GPIO_BASE #define EN_CON (0x040) #define EN_DAT (0x140) #define EN_PUD (0x0050) //dummy #define EN_DRV (0x0000) // dummy /* MST_DATA (gpio138)*/ #define MST_DATA_BASE GPIO_BASE #define DATA_CON (0x040) #define DATA_DAT (0x140) #define DATA_PUD (0x0050) // dummy #define DATA_DRV (0x0000) // dummy #define CON_DATA_OFFSET 10 // DATA #define DAT_DATA_OFFSET 10 #define CON_EN_OFFSET 11 // EN #define DAT_EN_OFFSET 11 #endif #endif // ]