#ifndef __CPR_FUSES_HWIO_H__ #define __CPR_FUSES_HWIO_H__ /* =========================================================================== */ /** @file cpr_fuses_hwio.h @brief Auto-generated HWIO interface include file. Reference chip release: SM8350 (Lahaina) [lahaina_v1.0_rtl_partition_p3q3r25.3_func_MTO] This file contains HWIO register definitions for the following modules: SECURITY_CONTROL_CORE Generation parameters: { 'filename': 'cpr_fuses_hwio.h', 'header': '#include "msmhwiobase.h"', 'module-filter-exclude': {}, 'module-filter-include': {}, 'modules': ['SECURITY_CONTROL_CORE'], 'output-fvals': True, 'output-offsets': True, 'output-phys': True} */ /* =========================================================================== Copyright (c) 2020 Qualcomm Technologies, Inc. All Rights Reserved. Confidential and Proprietary - Qualcomm Technologies, Inc. Export of this technology or software is regulated by the U.S. Government. Diversion contrary to U.S. law prohibited. All ideas, data and information contained in or disclosed by this document are confidential and proprietary information of Qualcomm Technologies, Inc. and all rights therein are expressly reserved. By accepting this material the recipient agrees that this material and the information contained therein are held in confidence and in trust and will not be used, copied, reproduced in whole or in part, nor its contents revealed in any manner to others without the express written permission of Qualcomm Technologies, Inc. =========================================================================== $Header: //components/rel/core.boot/5.0/QcomPkg/SocPkg/Lahaina/Library/CPRTargetLib/target/8350/hwio/cpr_fuses_hwio.h#2 $ $DateTime: 2020/02/06 15:51:44 $ $Author: pwbldsvc $ =========================================================================== */ #include "msmhwiobase.h" /*---------------------------------------------------------------------------- * MODULE: SECURITY_CONTROL_CORE *--------------------------------------------------------------------------*/ #define SECURITY_CONTROL_CORE_REG_BASE (SECURITY_CONTROL_BASE + 0x00000000) #define SECURITY_CONTROL_CORE_REG_BASE_SIZE 0x7000 #define SECURITY_CONTROL_CORE_REG_BASE_USED 0x6400 #define SECURITY_CONTROL_CORE_REG_BASE_PHYS (SECURITY_CONTROL_BASE_PHYS + 0x00000000) #define SECURITY_CONTROL_CORE_REG_BASE_OFFS 0x00000000 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000000) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000000) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000000) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_CM_CORE_PRIVATE_OTP_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_LSB_CM_CORE_PRIVATE_OTP_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000004) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000004) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000004) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_CM_CORE_PRIVATE_OTP_63_32_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW0_MSB_CM_CORE_PRIVATE_OTP_63_32_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000008) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000008) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000008) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_CM_CORE_PRIVATE_OTP_95_64_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_LSB_CM_CORE_PRIVATE_OTP_95_64_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000000c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000000c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000000c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_CM_CORE_PRIVATE_OTP_127_96_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW1_MSB_CM_CORE_PRIVATE_OTP_127_96_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000010) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000010) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000010) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_CM_CORE_PRIVATE_OTP_159_128_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_LSB_CM_CORE_PRIVATE_OTP_159_128_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000014) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000014) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000014) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_CM_CORE_PRIVATE_OTP_191_160_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW2_MSB_CM_CORE_PRIVATE_OTP_191_160_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000018) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000018) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000018) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_CM_CORE_PRIVATE_OTP_223_192_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_LSB_CM_CORE_PRIVATE_OTP_223_192_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000001c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000001c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000001c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_CM_CORE_PRIVATE_OTP_255_224_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW3_MSB_CM_CORE_PRIVATE_OTP_255_224_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000020) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000020) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000020) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_CM_CORE_PRIVATE_OTP_287_256_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_LSB_CM_CORE_PRIVATE_OTP_287_256_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000024) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000024) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000024) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_CM_CORE_PRIVATE_OTP_319_288_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW4_MSB_CM_CORE_PRIVATE_OTP_319_288_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000028) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000028) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000028) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_CM_CORE_PRIVATE_OTP_351_320_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_LSB_CM_CORE_PRIVATE_OTP_351_320_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000002c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000002c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000002c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_CM_CORE_PRIVATE_OTP_383_352_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW5_MSB_CM_CORE_PRIVATE_OTP_383_352_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000030) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000030) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000030) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_CM_CORE_PRIVATE_OTP_415_384_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_LSB_CM_CORE_PRIVATE_OTP_415_384_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000034) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000034) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000034) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_CM_CORE_PRIVATE_OTP_447_416_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW6_MSB_CM_CORE_PRIVATE_OTP_447_416_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000038) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000038) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000038) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_CM_CORE_PRIVATE_OTP_479_448_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_LSB_CM_CORE_PRIVATE_OTP_479_448_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000003c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000003c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000003c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_CM_CORE_PRIVATE_OTP_511_480_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW7_MSB_CM_CORE_PRIVATE_OTP_511_480_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000040) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000040) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000040) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_CM_CORE_PRIVATE_OTP_543_512_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_LSB_CM_CORE_PRIVATE_OTP_543_512_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000044) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000044) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000044) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_CM_CORE_PRIVATE_OTP_575_544_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW8_MSB_CM_CORE_PRIVATE_OTP_575_544_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000048) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000048) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000048) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_CM_CORE_PRIVATE_OTP_607_576_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_LSB_CM_CORE_PRIVATE_OTP_607_576_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000004c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000004c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000004c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_CM_CORE_PRIVATE_OTP_639_608_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW9_MSB_CM_CORE_PRIVATE_OTP_639_608_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000050) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000050) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000050) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_CM_CORE_PRIVATE_OTP_671_640_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_LSB_CM_CORE_PRIVATE_OTP_671_640_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000054) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000054) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000054) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_CM_CORE_PRIVATE_OTP_703_672_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW10_MSB_CM_CORE_PRIVATE_OTP_703_672_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000058) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000058) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000058) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_CM_CORE_PRIVATE_OTP_735_704_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_LSB_CM_CORE_PRIVATE_OTP_735_704_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000005c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000005c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000005c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_CM_CORE_PRIVATE_OTP_767_736_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW11_MSB_CM_CORE_PRIVATE_OTP_767_736_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000060) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000060) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000060) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_CM_CORE_PRIVATE_OTP_799_768_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_LSB_CM_CORE_PRIVATE_OTP_799_768_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000064) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000064) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000064) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_CM_CORE_PRIVATE_OTP_831_800_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW12_MSB_CM_CORE_PRIVATE_OTP_831_800_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000068) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000068) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000068) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_CM_CORE_PRIVATE_OTP_863_832_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_LSB_CM_CORE_PRIVATE_OTP_863_832_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000006c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000006c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000006c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_CM_CORE_PRIVATE_OTP_895_864_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW13_MSB_CM_CORE_PRIVATE_OTP_895_864_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000070) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000070) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000070) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_CM_CORE_PRIVATE_OTP_927_896_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_LSB_CM_CORE_PRIVATE_OTP_927_896_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000074) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000074) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000074) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_CM_CORE_PRIVATE_OTP_959_928_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW14_MSB_CM_CORE_PRIVATE_OTP_959_928_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000078) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000078) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000078) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_CM_CORE_PRIVATE_OTP_991_960_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_LSB_CM_CORE_PRIVATE_OTP_991_960_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000007c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000007c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000007c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_CM_CORE_PRIVATE_OTP_1023_992_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW15_MSB_CM_CORE_PRIVATE_OTP_1023_992_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000080) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000080) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000080) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_CM_CORE_PRIVATE_OTP_1055_1024_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_LSB_CM_CORE_PRIVATE_OTP_1055_1024_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000084) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000084) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000084) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_CM_CORE_PRIVATE_OTP_1087_1056_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW16_MSB_CM_CORE_PRIVATE_OTP_1087_1056_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000088) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000088) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000088) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_CM_CORE_PRIVATE_OTP_1119_1088_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_LSB_CM_CORE_PRIVATE_OTP_1119_1088_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000008c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000008c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000008c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_CM_CORE_PRIVATE_OTP_1151_1120_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW17_MSB_CM_CORE_PRIVATE_OTP_1151_1120_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000090) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000090) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000090) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_CM_CORE_PRIVATE_OTP_1183_1152_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_LSB_CM_CORE_PRIVATE_OTP_1183_1152_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000094) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000094) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000094) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_CM_CORE_PRIVATE_OTP_1215_1184_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW18_MSB_CM_CORE_PRIVATE_OTP_1215_1184_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000098) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000098) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000098) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_CM_CORE_PRIVATE_OTP_1247_1216_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_LSB_CM_CORE_PRIVATE_OTP_1247_1216_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000009c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000009c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000009c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_CM_CORE_PRIVATE_OTP_1279_1248_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW19_MSB_CM_CORE_PRIVATE_OTP_1279_1248_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000a0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000a0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000a0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_CM_CORE_PRIVATE_OTP_1311_1280_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_LSB_CM_CORE_PRIVATE_OTP_1311_1280_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000a4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000a4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000a4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_CM_CORE_PRIVATE_OTP_1343_1312_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW20_MSB_CM_CORE_PRIVATE_OTP_1343_1312_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000a8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000a8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000a8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_CM_CORE_PRIVATE_OTP_1375_1344_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_LSB_CM_CORE_PRIVATE_OTP_1375_1344_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000ac) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000ac) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000ac) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_CM_CORE_PRIVATE_OTP_1407_1376_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW21_MSB_CM_CORE_PRIVATE_OTP_1407_1376_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000b0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000b0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000b0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_CM_CORE_PRIVATE_OTP_1439_1408_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_LSB_CM_CORE_PRIVATE_OTP_1439_1408_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000b4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000b4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000b4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_CM_CORE_PRIVATE_OTP_1471_1440_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW22_MSB_CM_CORE_PRIVATE_OTP_1471_1440_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000b8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000b8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000b8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_CM_CORE_PRIVATE_OTP_1503_1472_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_LSB_CM_CORE_PRIVATE_OTP_1503_1472_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000bc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000bc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000bc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_CM_CORE_PRIVATE_OTP_1535_1504_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW23_MSB_CM_CORE_PRIVATE_OTP_1535_1504_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000c0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000c0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000c0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_CM_CORE_PRIVATE_OTP_1567_1536_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_LSB_CM_CORE_PRIVATE_OTP_1567_1536_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000c4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000c4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000c4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_CM_CORE_PRIVATE_OTP_1599_1568_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW24_MSB_CM_CORE_PRIVATE_OTP_1599_1568_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000c8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000c8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000c8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_CM_CORE_PRIVATE_OTP_1631_1600_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_LSB_CM_CORE_PRIVATE_OTP_1631_1600_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000cc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000cc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000cc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_CM_CORE_PRIVATE_OTP_1663_1632_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW25_MSB_CM_CORE_PRIVATE_OTP_1663_1632_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000d0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000d0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000d0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_CM_CORE_PRIVATE_OTP_1695_1664_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_LSB_CM_CORE_PRIVATE_OTP_1695_1664_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000d4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000d4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000d4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_CM_CORE_PRIVATE_OTP_1727_1696_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW26_MSB_CM_CORE_PRIVATE_OTP_1727_1696_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000d8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000d8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000d8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_CM_CORE_PRIVATE_OTP_1759_1728_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_LSB_CM_CORE_PRIVATE_OTP_1759_1728_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000dc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000dc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000dc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_CM_CORE_PRIVATE_OTP_1791_1760_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW27_MSB_CM_CORE_PRIVATE_OTP_1791_1760_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000e0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000e0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000e0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_CM_CORE_PRIVATE_OTP_1823_1792_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_LSB_CM_CORE_PRIVATE_OTP_1823_1792_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000e4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000e4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000e4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_CM_CORE_PRIVATE_OTP_1855_1824_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW28_MSB_CM_CORE_PRIVATE_OTP_1855_1824_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000e8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000e8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000e8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_CM_CORE_PRIVATE_OTP_1887_1856_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_LSB_CM_CORE_PRIVATE_OTP_1887_1856_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000ec) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000ec) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000ec) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_CM_CORE_PRIVATE_OTP_1919_1888_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW29_MSB_CM_CORE_PRIVATE_OTP_1919_1888_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000f0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000f0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000f0) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_CM_CORE_PRIVATE_OTP_1951_1920_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_LSB_CM_CORE_PRIVATE_OTP_1951_1920_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000f4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000f4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000f4) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_CM_CORE_PRIVATE_OTP_1983_1952_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW30_MSB_CM_CORE_PRIVATE_OTP_1983_1952_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000f8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000f8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000f8) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_CM_CORE_PRIVATE_OTP_2015_1984_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_LSB_CM_CORE_PRIVATE_OTP_2015_1984_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000000fc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000000fc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000000fc) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_CM_CORE_PRIVATE_OTP_2047_2016_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW31_MSB_CM_CORE_PRIVATE_OTP_2047_2016_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000100) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000100) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000100) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_CM_CORE_PRIVATE_OTP_2079_2048_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_LSB_CM_CORE_PRIVATE_OTP_2079_2048_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000104) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000104) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000104) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_CM_CORE_PRIVATE_OTP_2111_2080_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW32_MSB_CM_CORE_PRIVATE_OTP_2111_2080_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000108) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000108) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000108) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_CM_CORE_PRIVATE_OTP_2143_2112_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_LSB_CM_CORE_PRIVATE_OTP_2143_2112_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000010c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000010c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000010c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_CM_CORE_PRIVATE_OTP_2175_2144_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW33_MSB_CM_CORE_PRIVATE_OTP_2175_2144_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000110) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000110) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000110) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_CM_CORE_PRIVATE_OTP_2207_2176_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_LSB_CM_CORE_PRIVATE_OTP_2207_2176_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000114) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000114) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000114) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_CM_CORE_PRIVATE_OTP_2239_2208_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW34_MSB_CM_CORE_PRIVATE_OTP_2239_2208_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000118) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000118) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000118) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_CM_CORE_PRIVATE_OTP_2271_2240_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_LSB_CM_CORE_PRIVATE_OTP_2271_2240_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000011c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000011c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000011c) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_IN) #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_CM_CORE_PRIVATE_OTP_2303_2272_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_CORE_PRIVATE_OTP_ROW35_MSB_CM_CORE_PRIVATE_OTP_2303_2272_SHFT 0x0 #define HWIO_QFPROM_RAW_LCM_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000120) #define HWIO_QFPROM_RAW_LCM_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000120) #define HWIO_QFPROM_RAW_LCM_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000120) #define HWIO_QFPROM_RAW_LCM_LSB_RMSK 0xe000001f #define HWIO_QFPROM_RAW_LCM_LSB_IN \ in_dword(HWIO_QFPROM_RAW_LCM_LSB_ADDR) #define HWIO_QFPROM_RAW_LCM_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_LCM_LSB_ADDR, m) #define HWIO_QFPROM_RAW_LCM_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_LCM_LSB_ADDR,v) #define HWIO_QFPROM_RAW_LCM_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_LCM_LSB_ADDR,m,v,HWIO_QFPROM_RAW_LCM_LSB_IN) #define HWIO_QFPROM_RAW_LCM_LSB_DISABLE_LCM_BMSK 0x80000000 #define HWIO_QFPROM_RAW_LCM_LSB_DISABLE_LCM_SHFT 0x1f #define HWIO_QFPROM_RAW_LCM_LSB_DISABLE_LCM_STATE_TRANSITION_BMSK 0x40000000 #define HWIO_QFPROM_RAW_LCM_LSB_DISABLE_LCM_STATE_TRANSITION_SHFT 0x1e #define HWIO_QFPROM_RAW_LCM_LSB_DISABLE_SECURE_PHK_BMSK 0x20000000 #define HWIO_QFPROM_RAW_LCM_LSB_DISABLE_SECURE_PHK_SHFT 0x1d #define HWIO_QFPROM_RAW_LCM_LSB_QC_EXTERNAL_BMSK 0x10 #define HWIO_QFPROM_RAW_LCM_LSB_QC_EXTERNAL_SHFT 0x4 #define HWIO_QFPROM_RAW_LCM_LSB_QC_INTERNAL_BMSK 0x8 #define HWIO_QFPROM_RAW_LCM_LSB_QC_INTERNAL_SHFT 0x3 #define HWIO_QFPROM_RAW_LCM_LSB_QC_FEAT_CONFIG_BMSK 0x4 #define HWIO_QFPROM_RAW_LCM_LSB_QC_FEAT_CONFIG_SHFT 0x2 #define HWIO_QFPROM_RAW_LCM_LSB_HW_TEST_BMSK 0x2 #define HWIO_QFPROM_RAW_LCM_LSB_HW_TEST_SHFT 0x1 #define HWIO_QFPROM_RAW_LCM_LSB_SOC_PERSO_BMSK 0x1 #define HWIO_QFPROM_RAW_LCM_LSB_SOC_PERSO_SHFT 0x0 #define HWIO_QFPROM_RAW_LCM_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000124) #define HWIO_QFPROM_RAW_LCM_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000124) #define HWIO_QFPROM_RAW_LCM_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000124) #define HWIO_QFPROM_RAW_LCM_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_LCM_MSB_IN \ in_dword(HWIO_QFPROM_RAW_LCM_MSB_ADDR) #define HWIO_QFPROM_RAW_LCM_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_LCM_MSB_ADDR, m) #define HWIO_QFPROM_RAW_LCM_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_LCM_MSB_ADDR,v) #define HWIO_QFPROM_RAW_LCM_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_LCM_MSB_ADDR,m,v,HWIO_QFPROM_RAW_LCM_MSB_IN) #define HWIO_QFPROM_RAW_LCM_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_RAW_LCM_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000128) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000128) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000128) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_PRI_KEY_DERIVATION_KEY_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_LSB_PRI_KEY_DERIVATION_KEY_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000012c) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000012c) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000012c) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_PRI_KEY_DERIVATION_KEY_63_32_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW0_MSB_PRI_KEY_DERIVATION_KEY_63_32_SHFT 0x0 #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000130) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000130) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000130) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_PRI_KEY_DERIVATION_KEY_95_64_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_LSB_PRI_KEY_DERIVATION_KEY_95_64_SHFT 0x0 #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000134) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000134) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000134) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_PRI_KEY_DERIVATION_KEY_127_96_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW1_MSB_PRI_KEY_DERIVATION_KEY_127_96_SHFT 0x0 #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000138) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000138) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000138) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_PRI_KEY_DERIVATION_KEY_159_128_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_LSB_PRI_KEY_DERIVATION_KEY_159_128_SHFT 0x0 #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000013c) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000013c) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000013c) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_PRI_KEY_DERIVATION_KEY_191_160_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW2_MSB_PRI_KEY_DERIVATION_KEY_191_160_SHFT 0x0 #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000140) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000140) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000140) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_ADDR) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_IN) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_PRI_KEY_DERIVATION_KEY_223_192_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_LSB_PRI_KEY_DERIVATION_KEY_223_192_SHFT 0x0 #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000144) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000144) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000144) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_ADDR) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_IN) #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_PRI_KEY_DERIVATION_KEY_255_224_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PRI_KEY_DERIVATION_KEY_ROW3_MSB_PRI_KEY_DERIVATION_KEY_255_224_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000148) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000148) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000148) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_BMSK 0xffff8000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_SHFT 0xf #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK 0x7fff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000014c) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000014c) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000014c) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_BMSK 0xffffff00 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_SHFT 0x8 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_BMSK 0xff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000150) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000150) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000150) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_BMSK 0xffffff00 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_SHFT 0x8 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_BMSK 0xff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000154) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000154) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000154) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_MDSS_RESOLUTION_LIMIT_BMSK 0xc0000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_MDSS_RESOLUTION_LIMIT_SHFT 0x1e #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DP_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DP_DISABLE_SHFT 0x1d #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_DISABLE_SHFT 0x1c #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_MDP_APICAL_LTC_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_MDP_APICAL_LTC_DISABLE_SHFT 0x1b #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_MDP_APICAL_LTC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_MDP_APICAL_LTC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT 0x1a #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DSI_1_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DSI_1_DISABLE_SHFT 0x19 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DSI_1_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DSI_1_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DSI_0_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DSI_0_DISABLE_SHFT 0x18 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DSI_0_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_DSI_0_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_BMSK 0xffffff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000158) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000158) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000158) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_MOCHA_PART_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_MOCHA_PART_SHFT 0x1f #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_QC_SP_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_QC_SP_DISABLE_SHFT 0x1e #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_QC_SP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_QC_SP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SMMU_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SMMU_DISABLE_SHFT 0x1d #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SMMU_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SMMU_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_DISABLE_SEC_BOOT_GPIO_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_DISABLE_SEC_BOOT_GPIO_SHFT 0x1c #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_QC_UDK_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_QC_UDK_DISABLE_SHFT 0x1b #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_QC_UDK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_QC_UDK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_SHFT 0x1a #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_1_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_1_DISABLE_SHFT 0x19 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_1_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_1_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_0_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_0_DISABLE_SHFT 0x18 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_0_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_0_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_DISABLE_SHFT 0x17 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT 0x16 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK 0x200000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT 0x15 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK 0x1fe000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT 0xd #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_SHFT 0xc #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK 0x800 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT 0xb #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK 0x400 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT 0xa #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_4K_DISABLE_BMSK 0x200 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_4K_DISABLE_SHFT 0x9 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_4K_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_4K_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_CVP_DISABLE_BMSK 0x100 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_CVP_DISABLE_SHFT 0x8 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_CVP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_CVP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_DISABLE_VPX_BMSK 0x80 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_DISABLE_VPX_SHFT 0x7 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_DISABLE_VPX_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_DISABLE_VPX_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_BMSK 0x40 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_SHFT 0x6 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_EUD_PORT1_SEL_BMSK 0x20 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_EUD_PORT1_SEL_SHFT 0x5 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_EUD_PORT1_SEL_USB_PORT0_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_EUD_PORT1_SEL_USB_PORT1_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_EUD_IGNR_CSR_BMSK 0x10 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_EUD_IGNR_CSR_SHFT 0x4 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_MDSS_Q_CONFIG_FUSE_BMSK 0x8 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_MDSS_Q_CONFIG_FUSE_SHFT 0x3 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_MDSS_Q_CONFIG_FUSE_HANA_FEAT_SET_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_MDSS_Q_CONFIG_FUSE_HANAQ_FEAT_SET_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SPR_DISABLE_BMSK 0x4 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_SPR_DISABLE_SHFT 0x2 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_DEMURA_DISABLE_BMSK 0x2 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_DEMURA_DISABLE_SHFT 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_MST_DISABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_LSB_MST_DISABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000015c) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000015c) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000015c) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK 0xfc000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT 0x1a #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT 0x19 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK 0x1fe0000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT 0x11 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_APSS_PDXWRPNTRDELAY_BMSK 0x18000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_APSS_PDXWRPNTRDELAY_SHFT 0xf #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_GATE_SRST_FUSE_BMSK 0x4000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_GATE_SRST_FUSE_SHFT 0xe #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_GATE_SRST_FUSE_UNGATED_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_GATE_SRST_FUSE_GATED_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK 0x2000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT 0xd #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_MOBILE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_AUTOMOTIVE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_POWER_BMSK 0x1000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_POWER_SHFT 0xc #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_POWER_MOBILE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_POWER_AUTOMOTIVE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_EMAC_DISABLE_BMSK 0x800 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_EMAC_DISABLE_SHFT 0xb #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_EMAC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_EMAC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_BMSK 0x400 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_SHFT 0xa #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_NAV_EFUSE_DISABLE_BMSK 0x200 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_NAV_EFUSE_DISABLE_SHFT 0x9 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_NAV_EFUSE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_NAV_EFUSE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_CORTEX_M3_DISABLE_BMSK 0x100 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_CORTEX_M3_DISABLE_SHFT 0x8 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_APS_RESET_DISABLE_BMSK 0x80 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_APS_RESET_DISABLE_SHFT 0x7 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_DOLBY_BIT_BMSK 0x40 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_DOLBY_BIT_SHFT 0x6 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_I_MC5_FUSE_BMSK 0x20 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_I_MC5_FUSE_SHFT 0x5 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_I_MC5_FUSE_MC4_MODE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_I_MC5_FUSE_MC5_MODE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_I_MC4_FUSE_BMSK 0x10 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_I_MC4_FUSE_SHFT 0x4 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_I_MC4_FUSE_MC4_MODE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_I_MC4_FUSE_MC5_MODE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_PKA_3PIP_DISABLE_BMSK 0x8 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_PKA_3PIP_DISABLE_SHFT 0x3 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_PKA_3PIP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_PKA_3PIP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_UFS_SINGLE_LANE_BMSK 0x4 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_UFS_SINGLE_LANE_SHFT 0x2 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_UFS_SINGLE_LANE_ICE_ENGINE_USES_SW_KEY_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_UFS_SINGLE_LANE_ICE_ENGINE_USES_HW_KEY_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_UFS_FUSE_ICE_DISABLE_BMSK 0x2 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_UFS_FUSE_ICE_DISABLE_SHFT 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_UFS_FUSE_ICE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_UFS_FUSE_ICE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_MSMC_NAV_EN_BMSK 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_MSMC_NAV_EN_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_MSMC_NAV_EN_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW2_MSB_MSMC_NAV_EN_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000160) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000160) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000160) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_ADDR) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_IN) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_7_0_BMSK 0xff000000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_7_0_SHFT 0x18 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_TURING_Q6SS_L2TCM_EN_BMSK 0xf00000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_TURING_Q6SS_L2TCM_EN_SHFT 0x14 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_LEGACY_MBNV6_OVERRIDE_BMSK 0x80000 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_LEGACY_MBNV6_OVERRIDE_SHFT 0x13 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_BMSK 0x7f800 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_SHFT 0xb #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_APC1PLL_LVAL_BMSK 0x7f8 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_APC1PLL_LVAL_SHFT 0x3 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_APSS_KRYO_PP_DISABLE_BMSK 0x4 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_APSS_KRYO_PP_DISABLE_SHFT 0x2 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_L3_SIZE_RED_BMSK 0x2 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_L3_SIZE_RED_SHFT 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_LSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000164) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000164) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000164) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_ADDR) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_IN) #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_RSVD_BMSK 0xfffffc00 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_RSVD_SHFT 0xa #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_EN_BMSK 0x200 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_EN_SHFT 0x9 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_EN_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_EN_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_HALF_BMSK 0x100 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_HALF_SHFT 0x8 #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_TURING_Q6SS_PLL_L_MAX_15_8_BMSK 0xff #define HWIO_QFPROM_RAW_CM_FEATURE_CONFIG_ROW3_MSB_TURING_Q6SS_PLL_L_MAX_15_8_SHFT 0x0 #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000168) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000168) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000168) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_MRC_2_0_BMSK 0xfffffff0 #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_MRC_2_0_SHFT 0x4 #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATIOM_LIST_BMSK 0xf #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATIOM_LIST_SHFT 0x0 #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000016c) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000016c) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000016c) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_MRC_2_0_BMSK 0xfffffffe #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_MRC_2_0_SHFT 0x1 #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_BMSK 0x1 #define HWIO_QFPROM_RAW_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_SHFT 0x0 #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000170) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000170) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000170) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_MRC_2_0_95_68_BMSK 0xfffffff0 #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_MRC_2_0_95_68_SHFT 0x4 #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_BMSK 0xf #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_SHFT 0x0 #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000174) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000174) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000174) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_MRC_2_0_127_96_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MRC_2_0_ROW1_MSB_MRC_2_0_127_96_SHFT 0x0 #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000178) #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000178) #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000178) #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_SPEED_BIN_BMSK 0xe0000000 #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_SPEED_BIN_SHFT 0x1d #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_MACCHIATO_EN_BMSK 0x10000000 #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_MACCHIATO_EN_SHFT 0x1c #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_FEATURE_ID_BMSK 0xff00000 #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_FEATURE_ID_SHFT 0x14 #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_JTAG_ID_BMSK 0xfffff #define HWIO_QFPROM_RAW_PTE_ROW0_LSB_JTAG_ID_SHFT 0x0 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000017c) #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000017c) #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000017c) #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_LOGIC_RETENTION_BMSK 0xe0000000 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_LOGIC_RETENTION_SHFT 0x1d #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IDDQ_REVISION_CONTROL_BMSK 0x18000000 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IDDQ_REVISION_CONTROL_SHFT 0x1b #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B58_BMSK 0x4000000 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B58_SHFT 0x1a #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B57_BMSK 0x2000000 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B57_SHFT 0x19 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B56_BMSK 0x1000000 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B56_SHFT 0x18 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B55_BMSK 0x800000 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B55_SHFT 0x17 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B54_BMSK 0x400000 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B54_SHFT 0x16 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B53_BMSK 0x200000 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B53_SHFT 0x15 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B52_BMSK 0x100000 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B52_SHFT 0x14 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B51_BMSK 0x80000 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R51_B51_SHFT 0x13 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IDDQ_MX_ACTIVE_BMSK 0x7f800 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IDDQ_MX_ACTIVE_SHFT 0xb #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IDDQ_CX_ACTIVE_BMSK 0x7f8 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IDDQ_CX_ACTIVE_SHFT 0x3 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IDDQ_MULTIPLIER_BMSK 0x6 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_IDDQ_MULTIPLIER_SHFT 0x1 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R38_B32_BMSK 0x1 #define HWIO_QFPROM_RAW_PTE_ROW0_MSB_SPARE_R38_B32_SHFT 0x0 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000180) #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000180) #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000180) #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_IDDQ_MM_ACTIVE_BMSK 0xff000000 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_IDDQ_MM_ACTIVE_SHFT 0x18 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SPARE_R39_B23_BMSK 0x800000 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SPARE_R39_B23_SHFT 0x17 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_PTE2P9GHZ_BMSK 0x400000 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_PTE2P9GHZ_SHFT 0x16 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SUBBINB_BMSK 0x3c0000 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SUBBINB_SHFT 0x12 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SUBBINA_BMSK 0x3c000 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SUBBINA_SHFT 0xe #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_XO_SHUTDOWN_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_XO_SHUTDOWN_DISABLE_SHFT 0xd #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_RETENTION_FAIL_BMSK 0x1000 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_RETENTION_FAIL_SHFT 0xc #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_TURBO_MODE_ONLY_BMSK 0x800 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_TURBO_MODE_ONLY_SHFT 0xb #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SPARE_R39_B10_BMSK 0x400 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SPARE_R39_B10_SHFT 0xa #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SPARE_R39_B9_BMSK 0x200 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SPARE_R39_B9_SHFT 0x9 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_CPU_ACC_BMSK 0x1f0 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_CPU_ACC_SHFT 0x4 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SPARE_R39_B3_BMSK 0x8 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SPARE_R39_B3_SHFT 0x3 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SPARE_R39_B2_BMSK 0x4 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_SPARE_R39_B2_SHFT 0x2 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_MINOR_REV_BMSK 0x3 #define HWIO_QFPROM_RAW_PTE_ROW1_LSB_MINOR_REV_SHFT 0x0 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000184) #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000184) #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000184) #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_DOU_BINNNING_BMSK 0xe0000000 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_DOU_BINNNING_SHFT 0x1d #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_TSENS_REV_CTRL_BMSK 0x10000000 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_TSENS_REV_CTRL_SHFT 0x1c #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_PARTIAL_GOOD_BMSK 0xf800000 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_PARTIAL_GOOD_SHFT 0x17 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B54_BMSK 0x400000 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B54_SHFT 0x16 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B53_BMSK 0x200000 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B53_SHFT 0x15 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B52_BMSK 0x100000 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B52_SHFT 0x14 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B51_BMSK 0x80000 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B51_SHFT 0x13 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B50_BMSK 0x40000 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B50_SHFT 0x12 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B49_BMSK 0x20000 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B49_SHFT 0x11 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B48_BMSK 0x10000 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B48_SHFT 0x10 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B47_BMSK 0x8000 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B47_SHFT 0xf #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_RSBC_WS_MX_BMSK 0x7f00 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_RSBC_WS_MX_SHFT 0x8 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B39_BMSK 0x80 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B39_SHFT 0x7 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_ML_REVISION_BITS_BMSK 0x70 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_ML_REVISION_BITS_SHFT 0x4 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_ML_MODEL_ID_BMSK 0xe #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_ML_MODEL_ID_SHFT 0x1 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B32_BMSK 0x1 #define HWIO_QFPROM_RAW_PTE_ROW1_MSB_SPARE_R39_B32_SHFT 0x0 #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000188) #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000188) #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000188) #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IDDQ_APC1_XP1_BMSK 0xff000000 #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IDDQ_APC1_XP1_SHFT 0x18 #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IDDQ_APC1_MAX_BMSK 0xff0000 #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IDDQ_APC1_MAX_SHFT 0x10 #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IDDQ_APC1_PERIPH_BMSK 0xff00 #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IDDQ_APC1_PERIPH_SHFT 0x8 #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IDDQ_APC0_ACTIVE_BMSK 0xff #define HWIO_QFPROM_RAW_PTE_ROW2_LSB_IDDQ_APC0_ACTIVE_SHFT 0x0 #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000018c) #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000018c) #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000018c) #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_RMSK 0xfffeffff #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IDDQ_APC1_TOTAL_LEAKAGE_6_0_BMSK 0xfe000000 #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IDDQ_APC1_TOTAL_LEAKAGE_6_0_SHFT 0x19 #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IDDQ_GFX_ACTIVE_BMSK 0x1fe0000 #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IDDQ_GFX_ACTIVE_SHFT 0x11 #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IDDQ_APC1_XP3_BMSK 0xff00 #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IDDQ_APC1_XP3_SHFT 0x8 #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IDDQ_APC1_XP2_BMSK 0xff #define HWIO_QFPROM_RAW_PTE_ROW2_MSB_IDDQ_APC1_XP2_SHFT 0x0 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000190) #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000190) #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000190) #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR) #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW3_LSB_IN) #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_DIE_X_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_DIE_X_3_0_SHFT 0x1c #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_DIE_Y_BMSK 0xff00000 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_DIE_Y_SHFT 0x14 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_MEM_RETENTION_BMSK 0xe0000 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_MEM_RETENTION_SHFT 0x11 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IDDQ_MX_OFF_BMSK 0x1f800 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IDDQ_MX_OFF_SHFT 0xb #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IDDQ_CX_OFF_BMSK 0x7e0 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IDDQ_CX_OFF_SHFT 0x5 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IDDQ_APC1_IOP_WORST_CORE_ID_BMSK 0x18 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IDDQ_APC1_IOP_WORST_CORE_ID_SHFT 0x3 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IDDQ_APC1_TOTAL_LEAKAGE_9_7_BMSK 0x7 #define HWIO_QFPROM_RAW_PTE_ROW3_LSB_IDDQ_APC1_TOTAL_LEAKAGE_9_7_SHFT 0x0 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000194) #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000194) #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000194) #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR) #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW3_MSB_IN) #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_SP_PARTIAL_BMSK 0x80000000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_SP_PARTIAL_SHFT 0x1f #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_SP_BLANK_BMSK 0x40000000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_SP_BLANK_SHFT 0x1e #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_SPARE_R41_B61_BMSK 0x20000000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_SPARE_R41_B61_SHFT 0x1d #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_SPARE_R41_B60_BMSK 0x10000000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_SPARE_R41_B60_SHFT 0x1c #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_WS_PWR_WA_BMSK 0x8000000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_WS_PWR_WA_SHFT 0x1b #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_WS_PERF_WA_BMSK 0x4000000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_WS_PERF_WA_SHFT 0x1a #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_BONE_PILE_BMSK 0x3000000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_BONE_PILE_SHFT 0x18 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_WS_CPR_MX_TUR_VBUMP_BMSK 0x800000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_WS_CPR_MX_TUR_VBUMP_SHFT 0x17 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_DVS_REV_BMSK 0x600000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_DVS_REV_SHFT 0x15 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_WS_2ND_INSERTION_BMSK 0x100000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_WS_2ND_INSERTION_SHFT 0x14 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_MINSVS_FAIL_BMSK 0x80000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_MINSVS_FAIL_SHFT 0x13 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_DVS_PREVIOUSLY_RUN_BMSK 0x40000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_DVS_PREVIOUSLY_RUN_SHFT 0x12 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_APC1_WC_ID_BMSK 0x30000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_APC1_WC_ID_SHFT 0x10 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_ROW_IDENTIFIER_BMSK 0x8000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_ROW_IDENTIFIER_SHFT 0xf #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_SPARE_R41_B46_BMSK 0x4000 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_SPARE_R41_B46_SHFT 0xe #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_CPU_VMIN_CORR_BMSK 0x3e00 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_CPU_VMIN_CORR_SHFT 0x9 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_WAFER_ID_BMSK 0x1f0 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_WAFER_ID_SHFT 0x4 #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_DIE_X_7_4_BMSK 0xf #define HWIO_QFPROM_RAW_PTE_ROW3_MSB_DIE_X_7_4_SHFT 0x0 #define HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000198) #define HWIO_QFPROM_RAW_PTE_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000198) #define HWIO_QFPROM_RAW_PTE_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000198) #define HWIO_QFPROM_RAW_PTE_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PTE_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR) #define HWIO_QFPROM_RAW_PTE_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PTE_ROW4_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PTE_ROW4_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW4_LSB_IN) #define HWIO_QFPROM_RAW_PTE_ROW4_LSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PTE_ROW4_LSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000019c) #define HWIO_QFPROM_RAW_PTE_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000019c) #define HWIO_QFPROM_RAW_PTE_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000019c) #define HWIO_QFPROM_RAW_PTE_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PTE_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR) #define HWIO_QFPROM_RAW_PTE_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PTE_ROW4_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PTE_ROW4_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PTE_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PTE_ROW4_MSB_IN) #define HWIO_QFPROM_RAW_PTE_ROW4_MSB_RSVD1_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PTE_ROW4_MSB_RSVD1_SHFT 0x0 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001a0) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001a0) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001a0) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_IN \ in_dword(HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ADDR) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ADDR, m) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ADDR,v) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ADDR,m,v,HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_IN) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_SPARE_31_READ_DISABLE_BMSK 0x80000000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_SPARE_31_READ_DISABLE_SHFT 0x1f #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_SPARE_30_READ_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_SPARE_30_READ_DISABLE_SHFT 0x1e #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_SPARE_29_READ_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_SPARE_29_READ_DISABLE_SHFT 0x1d #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_SPARE_28_READ_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_SPARE_28_READ_DISABLE_SHFT 0x1c #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_USER_KEY_DERIVATION_KEY_READ_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_USER_KEY_DERIVATION_KEY_READ_DISABLE_SHFT 0x1b #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_READ_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_READ_DISABLE_SHFT 0x1a #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_BOOT_ROM_PATCH_READ_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_BOOT_ROM_PATCH_READ_DISABLE_SHFT 0x19 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_READ_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_READ_DISABLE_SHFT 0x18 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_SECURE_BOOT_READ_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_SECURE_BOOT_READ_DISABLE_SHFT 0x17 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_READ_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_READ_DISABLE_SHFT 0x16 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_QC_SPARE_21_READ_DISABLE_BMSK 0x200000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_QC_SPARE_21_READ_DISABLE_SHFT 0x15 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_QC_SPARE_20_READ_DISABLE_BMSK 0x100000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_QC_SPARE_20_READ_DISABLE_SHFT 0x14 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_MEMORY_CONFIGURATION_READ_DISABLE_BMSK 0x80000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_MEMORY_CONFIGURATION_READ_DISABLE_SHFT 0x13 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_CALIBRATION_READ_DISABLE_BMSK 0x40000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_CALIBRATION_READ_DISABLE_SHFT 0x12 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_READ_DISABLE_BMSK 0x20000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_READ_DISABLE_SHFT 0x11 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_5_READ_DISABLE_BMSK 0x10000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_5_READ_DISABLE_SHFT 0x10 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_4_READ_DISABLE_BMSK 0x8000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_4_READ_DISABLE_SHFT 0xf #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_3_READ_DISABLE_BMSK 0x4000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_3_READ_DISABLE_SHFT 0xe #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_2_READ_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_2_READ_DISABLE_SHFT 0xd #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_1_READ_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_1_READ_DISABLE_SHFT 0xc #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_READ_DISABLE_BMSK 0x800 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_READ_DISABLE_SHFT 0xb #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_READ_DISABLE_BMSK 0x400 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_READ_DISABLE_SHFT 0xa #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_CONFIGURATION_READ_DISABLE_BMSK 0x200 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_OEM_CONFIGURATION_READ_DISABLE_SHFT 0x9 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_FEC_ENABLES_READ_DISABLE_BMSK 0x100 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_FEC_ENABLES_READ_DISABLE_SHFT 0x8 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_WRITE_PERMISSION_READ_DISABLE_BMSK 0x80 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_WRITE_PERMISSION_READ_DISABLE_SHFT 0x7 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_READ_PERMISSION_READ_DISABLE_BMSK 0x40 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_READ_PERMISSION_READ_DISABLE_SHFT 0x6 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_PTE_READ_DISABLE_BMSK 0x20 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_PTE_READ_DISABLE_SHFT 0x5 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_MRC_READ_DISABLE_BMSK 0x10 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_MRC_READ_DISABLE_SHFT 0x4 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_READ_DISABLE_BMSK 0x8 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_READ_DISABLE_SHFT 0x3 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_READ_DISABLE_BMSK 0x4 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_READ_DISABLE_SHFT 0x2 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_LCM_READ_DISABLE_BMSK 0x2 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_LCM_READ_DISABLE_SHFT 0x1 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_CM_PRIVATE_READ_DISABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_LSB_CM_PRIVATE_READ_DISABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001a4) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001a4) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001a4) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_IN \ in_dword(HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_ADDR) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_ADDR, m) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_ADDR,v) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_ADDR,m,v,HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_IN) #define HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_RSVD0_54_BMSK 0xffffffff #define HWIO_QFPROM_RAW_READ_PERMISSIONS_MSB_RSVD0_54_SHFT 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001a8) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001a8) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001a8) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_IN \ in_dword(HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ADDR) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ADDR, m) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ADDR,v) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ADDR,m,v,HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_IN) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_31_WRITE_DISABLE_BMSK 0x80000000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_31_WRITE_DISABLE_SHFT 0x1f #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_30_WRITE_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_30_WRITE_DISABLE_SHFT 0x1e #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_30_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_30_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_29_WRITE_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_29_WRITE_DISABLE_SHFT 0x1d #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_29_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_29_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_28_WRITE_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_28_WRITE_DISABLE_SHFT 0x1c #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_28_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SPARE_28_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_USER_KEY_DERIVATIONKEY_WRITE_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_USER_KEY_DERIVATIONKEY_WRITE_DISABLE_SHFT 0x1b #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_USER_KEY_DERIVATIONKEY_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_USER_KEY_DERIVATIONKEY_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_WRITE_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_WRITE_DISABLE_SHFT 0x1a #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_BOOT_ROM_PATCH_WRITE_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_BOOT_ROM_PATCH_WRITE_DISABLE_SHFT 0x19 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_BOOT_ROM_PATCH_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_BOOT_ROM_PATCH_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_WRITE_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_WRITE_DISABLE_SHFT 0x18 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SECURE_BOOT_WRITE_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SECURE_BOOT_WRITE_DISABLE_SHFT 0x17 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SECURE_BOOT_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_SECURE_BOOT_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_WRITE_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_WRITE_DISABLE_SHFT 0x16 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_QC_SPARE_21_WRITE_DISABLE_BMSK 0x200000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_QC_SPARE_21_WRITE_DISABLE_SHFT 0x15 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_QC_SPARE_21_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_QC_SPARE_21_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_QC_SPARE_20_WRITE_DISABLE_BMSK 0x100000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_QC_SPARE_20_WRITE_DISABLE_SHFT 0x14 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_QC_SPARE_20_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_QC_SPARE_20_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_MEMORY_CONFIGURATION_WRITE_DISABLE_BMSK 0x80000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_MEMORY_CONFIGURATION_WRITE_DISABLE_SHFT 0x13 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_MEMORY_CONFIGURATION_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_MEMORY_CONFIGURATION_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CALIBRATION_WRITE_DISABLE_BMSK 0x40000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CALIBRATION_WRITE_DISABLE_SHFT 0x12 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CALIBRATION_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CALIBRATION_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_WRITE_DISABLE_BMSK 0x20000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_WRITE_DISABLE_SHFT 0x11 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_5_WRITE_DISABLE_BMSK 0x10000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_5_WRITE_DISABLE_SHFT 0x10 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_5_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_5_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_4_WRITE_DISABLE_BMSK 0x8000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_4_WRITE_DISABLE_SHFT 0xf #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_4_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_4_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_3_WRITE_DISABLE_BMSK 0x4000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_3_WRITE_DISABLE_SHFT 0xe #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_3_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_3_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_2_WRITE_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_2_WRITE_DISABLE_SHFT 0xd #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_2_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_2_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_1_WRITE_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_1_WRITE_DISABLE_SHFT 0xc #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_1_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_1_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_WRITE_DISABLE_BMSK 0x800 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_WRITE_DISABLE_SHFT 0xb #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_WRITE_DISABLE_BMSK 0x400 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_WRITE_DISABLE_SHFT 0xa #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_CONFIGURATION_WRITE_DISABLE_BMSK 0x200 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_CONFIGURATION_WRITE_DISABLE_SHFT 0x9 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_CONFIGURATION_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_OEM_CONFIGURATION_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEC_ENABLES_WRITE_DISABLE_BMSK 0x100 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEC_ENABLES_WRITE_DISABLE_SHFT 0x8 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEC_ENABLES_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_FEC_ENABLES_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_WRITE_PERMISSIONS_WRITE_DISABLE_BMSK 0x80 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_WRITE_PERMISSIONS_WRITE_DISABLE_SHFT 0x7 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_WRITE_PERMISSIONS_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_WRITE_PERMISSIONS_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_READ_PERMISSIONS_WRITE_DISABLE_BMSK 0x40 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_READ_PERMISSIONS_WRITE_DISABLE_SHFT 0x6 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_READ_PERMISSIONS_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_READ_PERMISSIONS_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PTE_WRITE_DISABLE_BMSK 0x20 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PTE_WRITE_DISABLE_SHFT 0x5 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PTE_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PTE_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_MRC_2_0_WRITE_DISABLE_BMSK 0x10 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_MRC_2_0_WRITE_DISABLE_SHFT 0x4 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_MRC_2_0_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_MRC_2_0_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_WRITE_DISABLE_BMSK 0x8 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_WRITE_DISABLE_SHFT 0x3 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_WRITE_DISABLE_BMSK 0x4 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_WRITE_DISABLE_SHFT 0x2 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_LCM_WRITE_DISABLE_BMSK 0x2 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_LCM_WRITE_DISABLE_SHFT 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_LCM_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_LCM_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CM_PRIVATE_WRITE_DISABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CM_PRIVATE_WRITE_DISABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CM_PRIVATE_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_LSB_CM_PRIVATE_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001ac) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001ac) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001ac) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_IN \ in_dword(HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_ADDR) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_ADDR, m) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_ADDR,v) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_ADDR,m,v,HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_IN) #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_RSVD0_55_BMSK 0xffffffff #define HWIO_QFPROM_RAW_WRITE_PERMISSIONS_MSB_RSVD0_55_SHFT 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001b0) #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001b0) #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001b0) #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_IN \ in_dword(HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ADDR) #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ADDR, m) #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ADDR,v) #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEC_ENABLES_LSB_IN) #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_31_FEC_ENABLE_BMSK 0x80000000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_31_FEC_ENABLE_SHFT 0x1f #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_30_FEC_ENABLE_BMSK 0x40000000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_30_FEC_ENABLE_SHFT 0x1e #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_30_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_30_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_29_FEC_ENABLE_BMSK 0x20000000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_29_FEC_ENABLE_SHFT 0x1d #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_29_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_29_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_28_FEC_ENABLE_BMSK 0x10000000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_28_FEC_ENABLE_SHFT 0x1c #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_28_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SPARE_28_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_USER_KEY_DERIVATION_KEY_FEC_ENABLE_BMSK 0x8000000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_USER_KEY_DERIVATION_KEY_FEC_ENABLE_SHFT 0x1b #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_USER_KEY_DERIVATION_KEY_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_USER_KEY_DERIVATION_KEY_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_IMAGE_ENCRYPTION_KEY_1_FEC_ENABLE_BMSK 0x4000000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_IMAGE_ENCRYPTION_KEY_1_FEC_ENABLE_SHFT 0x1a #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_IMAGE_ENCRYPTION_KEY_1_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_IMAGE_ENCRYPTION_KEY_1_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_BOOT_ROM_PATCH_FEC_ENABLE_BMSK 0x2000000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_BOOT_ROM_PATCH_FEC_ENABLE_SHFT 0x19 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_BOOT_ROM_PATCH_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_BOOT_ROM_PATCH_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_SECONDARY_KEY_DERIVATION_KEY_FEC_ENABLE_BMSK 0x1000000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_SECONDARY_KEY_DERIVATION_KEY_FEC_ENABLE_SHFT 0x18 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_SECONDARY_KEY_DERIVATION_KEY_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_SECONDARY_KEY_DERIVATION_KEY_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SECURE_BOOT_FEC_ENABLE_BMSK 0x800000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SECURE_BOOT_FEC_ENABLE_SHFT 0x17 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SECURE_BOOT_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_SECURE_BOOT_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_IMAGE_ENCRYPTION_KEY_FEC_ENABLE_BMSK 0x400000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_IMAGE_ENCRYPTION_KEY_FEC_ENABLE_SHFT 0x16 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_IMAGE_ENCRYPTION_KEY_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_IMAGE_ENCRYPTION_KEY_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_QC_SPARE_21_FEC_ENABLE_BMSK 0x200000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_QC_SPARE_21_FEC_ENABLE_SHFT 0x15 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_QC_SPARE_21_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_QC_SPARE_21_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_QC_SPARE_20_FEC_ENABLE_BMSK 0x100000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_QC_SPARE_20_FEC_ENABLE_SHFT 0x14 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_QC_SPARE_20_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_QC_SPARE_20_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_MEMORY_CONFIGURATION_FEC_ENABLE_BMSK 0x80000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_MEMORY_CONFIGURATION_FEC_ENABLE_SHFT 0x13 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_MEMORY_CONFIGURATION_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_MEMORY_CONFIGURATION_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CALIBRATION_FEC_ENABLE_BMSK 0x40000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CALIBRATION_FEC_ENABLE_SHFT 0x12 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CALIBRATION_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CALIBRATION_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PUBLIC_KEY_HASH_0_FEC_ENABLE_BMSK 0x20000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PUBLIC_KEY_HASH_0_FEC_ENABLE_SHFT 0x11 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PUBLIC_KEY_HASH_0_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PUBLIC_KEY_HASH_0_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_5_FEC_ENABLE_BMSK 0x10000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_5_FEC_ENABLE_SHFT 0x10 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_5_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_5_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_4_FEC_ENABLE_BMSK 0x8000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_4_FEC_ENABLE_SHFT 0xf #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_4_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_4_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_3_FEC_ENABLE_BMSK 0x4000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_3_FEC_ENABLE_SHFT 0xe #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_3_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_3_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_2_FEC_ENABLE_BMSK 0x2000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_2_FEC_ENABLE_SHFT 0xd #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_2_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_2_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_1_FEC_ENABLE_BMSK 0x1000 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_1_FEC_ENABLE_SHFT 0xc #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_1_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_ANTI_ROLLBACK_1_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_NM_FEC_ENABLE_BMSK 0x800 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_NM_FEC_ENABLE_SHFT 0xb #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_NM_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_NM_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_M_FEC_ENABLE_BMSK 0x400 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_M_FEC_ENABLE_SHFT 0xa #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_M_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_M_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_CONFIGURATION_FEC_ENABLE_BMSK 0x200 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_CONFIGURATION_FEC_ENABLE_SHFT 0x9 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_CONFIGURATION_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_OEM_CONFIGURATION_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEC_ENABLES_FEC_ENABLE_BMSK 0x100 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEC_ENABLES_FEC_ENABLE_SHFT 0x8 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEC_ENABLES_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_FEC_ENABLES_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_WRITE_PERMISSIONS_FEC_ENABLE_BMSK 0x80 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_WRITE_PERMISSIONS_FEC_ENABLE_SHFT 0x7 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_WRITE_PERMISSIONS_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_WRITE_PERMISSIONS_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_READ_PERMISSIONS_FEC_ENABLE_BMSK 0x40 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_READ_PERMISSIONS_FEC_ENABLE_SHFT 0x6 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_READ_PERMISSIONS_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_READ_PERMISSIONS_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PTE_FEC_ENABLE_BMSK 0x20 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PTE_FEC_ENABLE_SHFT 0x5 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PTE_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PTE_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_MRC_2_0_FEC_ENABLE_BMSK 0x10 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_MRC_2_0_FEC_ENABLE_SHFT 0x4 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_MRC_2_0_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_MRC_2_0_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CM_FEATURE_CONFIGURATION_FEC_ENABLE_BMSK 0x8 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CM_FEATURE_CONFIGURATION_FEC_ENABLE_SHFT 0x3 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CM_FEATURE_CONFIGURATION_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CM_FEATURE_CONFIGURATION_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PRIMARY_KEY_DERIVATION_KEY_FEC_ENABLE_BMSK 0x4 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PRIMARY_KEY_DERIVATION_KEY_FEC_ENABLE_SHFT 0x2 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PRIMARY_KEY_DERIVATION_KEY_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_PRIMARY_KEY_DERIVATION_KEY_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_LCM_FEC_ENABLE_BMSK 0x2 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_LCM_FEC_ENABLE_SHFT 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_LCM_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_LCM_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CM_PRIVATE_FEC_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CM_PRIVATE_FEC_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CM_PRIVATE_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEC_ENABLES_LSB_CM_PRIVATE_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEC_ENABLES_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001b4) #define HWIO_QFPROM_RAW_FEC_ENABLES_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001b4) #define HWIO_QFPROM_RAW_FEC_ENABLES_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001b4) #define HWIO_QFPROM_RAW_FEC_ENABLES_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEC_ENABLES_MSB_IN \ in_dword(HWIO_QFPROM_RAW_FEC_ENABLES_MSB_ADDR) #define HWIO_QFPROM_RAW_FEC_ENABLES_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEC_ENABLES_MSB_ADDR, m) #define HWIO_QFPROM_RAW_FEC_ENABLES_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEC_ENABLES_MSB_ADDR,v) #define HWIO_QFPROM_RAW_FEC_ENABLES_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEC_ENABLES_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEC_ENABLES_MSB_IN) #define HWIO_QFPROM_RAW_FEC_ENABLES_MSB_RSVD0_56_BMSK 0xffffffff #define HWIO_QFPROM_RAW_FEC_ENABLES_MSB_RSVD0_56_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001b8) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001b8) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001b8) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_BMSK 0x80000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_SHFT 0x1f #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_SHFT 0x1e #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_SHFT 0x1d #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_SHFT 0x1c #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_SHFT 0x1b #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_SHFT 0x1a #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_BMSK 0x2000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_SHFT 0x19 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK 0x1000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT 0x18 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_SHFT 0x17 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_SHFT 0x16 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_BMSK 0x200000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_SHFT 0x15 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_USE_OEM_ID_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_USE_SERIAL_NUM_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_BMSK 0x100000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_SHFT 0x14 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_BMSK 0x80000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_SHFT 0x13 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_BMSK 0x60000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_SHFT 0x11 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_BMSK 0x10000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_SHFT 0x10 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_BMSK 0x8000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_SHFT 0xf #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_BMSK 0x4000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_SHFT 0xe #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_USE_GPIO_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_WDOG_EN_IGNORE_GPIO_ENABLE_WDOG_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE__BMSK 0x2000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE__SHFT 0xd #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE__DISABLE_EDL_RESET_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE__ENABLE_EDL_RESET_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_SHFT 0xc #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_BMSK 0x800 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_SHFT 0xb #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_BMSK 0x400 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_SHFT 0xa #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_SD_USB_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_QSPI_SD_USB_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_BMSK 0x3e0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SHFT 0x5 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_DEFAULT_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SD_UFS_EDL_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SD_EDL_FVAL 0x2 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_USB_EDL_FVAL 0x3 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_QSPI_EDL_FVAL 0x4 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SPI_EDL_FVAL 0x5 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FAST_BOOT_UGSG4_SD_USB_EDL_FVAL 0x8 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_ADMA_DISABLE_BMSK 0x10 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_ADMA_DISABLE_SHFT 0x4 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_ADMA_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_SDCC_ADMA_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_BMSK 0x8 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_SHFT 0x3 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_BMSK 0x4 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_SHFT 0x2 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_BMSK 0x2 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_SHFT 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_TIMEOUT_DISABLED_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_TIMEOUT_ENABLED_90S_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_DOWNLOADER_ENABLED_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_DOWNLOADER_DISABLED_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001bc) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001bc) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001bc) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RSVD_BMSK 0xffffc000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_RSVD_SHFT 0xe #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_SHFT 0xd #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_SHFT 0xc #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_BMSK 0x800 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_SHFT 0xb #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_BMSK 0x400 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_SHFT 0xa #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_BMSK 0x200 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_SHFT 0x9 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_BMSK 0x100 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_SHFT 0x8 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_BMSK 0x80 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_SHFT 0x7 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_BMSK 0x40 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_SHFT 0x6 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_BMSK 0x20 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_SHFT 0x5 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_BMSK 0x10 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_SHFT 0x4 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_BMSK 0x8 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_SHFT 0x3 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_BMSK 0x4 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_SHFT 0x2 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_BMSK 0x2 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_SHFT 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001c0) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001c0) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001c0) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RMSK 0xfffff7fe #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_BMSK 0x80000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_SHFT 0x1f #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_BMSK 0x40000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_SHFT 0x1e #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_29_BMSK 0x20000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_29_SHFT 0x1d #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_28_BMSK 0x10000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_28_SHFT 0x1c #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_27_BMSK 0x8000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_27_SHFT 0x1b #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_26_BMSK 0x4000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_26_SHFT 0x1a #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_25_BMSK 0x2000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_25_SHFT 0x19 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_24_BMSK 0x1000000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_24_SHFT 0x18 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_23_BMSK 0x800000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_23_SHFT 0x17 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_22_BMSK 0x400000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_22_SHFT 0x16 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_21_BMSK 0x200000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_21_SHFT 0x15 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_20_BMSK 0x100000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_20_SHFT 0x14 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_19_BMSK 0x80000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_19_SHFT 0x13 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_18_BMSK 0x40000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_18_SHFT 0x12 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_17_BMSK 0x20000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_17_SHFT 0x11 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_16_BMSK 0x10000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD1_50_16_SHFT 0x10 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_BMSK 0x8000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_SHFT 0xf #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_SECURE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_BMSK 0x4000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_SHFT 0xe #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_SECURE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_BMSK 0x2000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_SHFT 0xd #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_SECURE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_BMSK 0x1000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_SHFT 0xc #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_SECURE_FVAL 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPU_IAR_ENABLED_BMSK 0x400 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SPU_IAR_ENABLED_SHFT 0xa #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD0_50_9_BMSK 0x200 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD0_50_9_SHFT 0x9 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD0_50_8_BMSK 0x100 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_RSVD0_50_8_SHFT 0x8 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_BMSK 0x80 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_SHFT 0x7 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_BMSK 0x40 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_SHFT 0x6 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_BMSK 0x20 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_SHFT 0x5 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_BMSK 0x10 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_SHFT 0x4 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_BMSK 0x8 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_SHFT 0x3 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_BMSK 0x6 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_SHFT 0x1 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001c4) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001c4) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001c4) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_BMSK 0xffff0000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_SHFT 0x10 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_BMSK 0xffff #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001c8) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001c8) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001c8) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_VID_BMSK 0xffff0000 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_VID_SHFT 0x10 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_PID_BMSK 0xffff #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_PERIPH_PID_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001cc) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001cc) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001cc) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RSVD_BMSK 0xffffff00 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_RSVD_SHFT 0x8 #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_BMSK 0xff #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001d0) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001d0) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001d0) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_BMSK 0xffff8000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_SHFT 0xf #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK 0x7fff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001d4) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001d4) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001d4) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_BMSK 0xffffff00 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_SHFT 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_BMSK 0xff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001d8) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001d8) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001d8) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_BMSK 0xffffff00 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_SHFT 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_BMSK 0xff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001dc) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001dc) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001dc) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_MDSS_RESOLUTION_LIMIT_BMSK 0xc0000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_MDSS_RESOLUTION_LIMIT_SHFT 0x1e #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DP_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DP_DISABLE_SHFT 0x1d #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_HDCP_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_HDCP_DISABLE_SHFT 0x1c #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_HDCP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_HDCP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_MDP_APICAL_LTC_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_MDP_APICAL_LTC_DISABLE_SHFT 0x1b #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_MDP_APICAL_LTC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_MDP_APICAL_LTC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT 0x1a #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DSI_1_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DSI_1_DISABLE_SHFT 0x19 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DSI_1_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DSI_1_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DSI_0_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DSI_0_DISABLE_SHFT 0x18 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DSI_0_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_DSI_0_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_BMSK 0xffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001e0) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001e0) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001e0) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_MOCHA_PART_BMSK 0x80000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_MOCHA_PART_SHFT 0x1f #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_QC_SP_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_QC_SP_DISABLE_SHFT 0x1e #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_QC_SP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_QC_SP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SMMU_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SMMU_DISABLE_SHFT 0x1d #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SMMU_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SMMU_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_DISABLE_SEC_BOOT_GPIO_BMSK 0x10000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_DISABLE_SEC_BOOT_GPIO_SHFT 0x1c #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_QC_UDK_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_QC_UDK_DISABLE_SHFT 0x1b #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_QC_UDK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_QC_UDK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_SHFT 0x1a #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_PCIE_1_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_PCIE_1_DISABLE_SHFT 0x19 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_PCIE_1_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_PCIE_1_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_PCIE_0_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_PCIE_0_DISABLE_SHFT 0x18 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_PCIE_0_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_PCIE_0_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_DISABLE_SHFT 0x17 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT 0x16 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK 0x200000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT 0x15 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK 0x1fe000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT 0xd #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_SHFT 0xc #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK 0x800 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT 0xb #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK 0x400 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT 0xa #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_4K_DISABLE_BMSK 0x200 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_4K_DISABLE_SHFT 0x9 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_4K_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_4K_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_CVP_DISABLE_BMSK 0x100 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_CVP_DISABLE_SHFT 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_CVP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_CVP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_DISABLE_VPX_BMSK 0x80 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_DISABLE_VPX_SHFT 0x7 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_DISABLE_VPX_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_IRIS_DISABLE_VPX_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_BMSK 0x40 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_SHFT 0x6 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_EUD_PORT1_SEL_BMSK 0x20 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_EUD_PORT1_SEL_SHFT 0x5 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_EUD_PORT1_SEL_USB_PORT0_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_EUD_PORT1_SEL_USB_PORT1_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_EUD_IGNR_CSR_BMSK 0x10 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_EUD_IGNR_CSR_SHFT 0x4 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_MDSS_Q_CONFIG_FUSE_BMSK 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_MDSS_Q_CONFIG_FUSE_SHFT 0x3 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_MDSS_Q_CONFIG_FUSE_HANA_FEAT_SET_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_MDSS_Q_CONFIG_FUSE_HANAQ_FEAT_SET_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SPR_DISABLE_BMSK 0x4 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_SPR_DISABLE_SHFT 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_DEMURA_DISABLE_BMSK 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_DEMURA_DISABLE_SHFT 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_MST_DISABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_LSB_MST_DISABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001e4) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001e4) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001e4) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK 0xfc000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT 0x1a #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK 0x2000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT 0x19 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK 0x1fe0000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT 0x11 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_APSS_PDXWRPNTRDELAY_BMSK 0x18000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_APSS_PDXWRPNTRDELAY_SHFT 0xf #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_GATE_SRST_FUSE_BMSK 0x4000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_GATE_SRST_FUSE_SHFT 0xe #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_GATE_SRST_FUSE_UNGATED_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_GATE_SRST_FUSE_GATED_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK 0x2000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT 0xd #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_MOBILE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_AUTOMOTIVE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_POWER_BMSK 0x1000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_POWER_SHFT 0xc #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_POWER_MOBILE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_POWER_AUTOMOTIVE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_EMAC_DISABLE_BMSK 0x800 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_EMAC_DISABLE_SHFT 0xb #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_EMAC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_EMAC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_BMSK 0x400 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_SHFT 0xa #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_NAV_EFUSE_DISABLE_BMSK 0x200 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_NAV_EFUSE_DISABLE_SHFT 0x9 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_NAV_EFUSE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_NAV_EFUSE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_FUSE_CORTEX_M3_DISABLE_BMSK 0x100 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_FUSE_CORTEX_M3_DISABLE_SHFT 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_APS_RESET_DISABLE_BMSK 0x80 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_APS_RESET_DISABLE_SHFT 0x7 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_DOLBY_BIT_BMSK 0x40 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_DOLBY_BIT_SHFT 0x6 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_I_MC5_FUSE_BMSK 0x20 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_I_MC5_FUSE_SHFT 0x5 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_I_MC5_FUSE_MC4_MODE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_I_MC5_FUSE_MC5_MODE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_I_MC4_FUSE_BMSK 0x10 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_I_MC4_FUSE_SHFT 0x4 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_I_MC4_FUSE_MC4_MODE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_I_MC4_FUSE_MC5_MODE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_PKA_3PIP_DISABLE_BMSK 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_PKA_3PIP_DISABLE_SHFT 0x3 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_PKA_3PIP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_PKA_3PIP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_FUSE_UFS_SINGLE_LANE_BMSK 0x4 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_FUSE_UFS_SINGLE_LANE_SHFT 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_FUSE_UFS_SINGLE_LANE_ICE_ENGINE_USES_SW_KEY_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_FUSE_UFS_SINGLE_LANE_ICE_ENGINE_USES_HW_KEY_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_UFS_FUSE_ICE_DISABLE_BMSK 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_UFS_FUSE_ICE_DISABLE_SHFT 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_UFS_FUSE_ICE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_UFS_FUSE_ICE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_MSMC_NAV_EN_BMSK 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_MSMC_NAV_EN_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_MSMC_NAV_EN_DISABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW2_MSB_MSMC_NAV_EN_ENABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001e8) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001e8) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001e8) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_7_0_BMSK 0xff000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_7_0_SHFT 0x18 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_TURING_Q6SS_L2TCM_EN_BMSK 0xf00000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_TURING_Q6SS_L2TCM_EN_SHFT 0x14 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_LEGACY_MBNV6_OVERRIDE_BMSK 0x80000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_LEGACY_MBNV6_OVERRIDE_SHFT 0x13 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_BMSK 0x7f800 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_SHFT 0xb #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_APC1PLL_LVAL_BMSK 0x7f8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_APC1PLL_LVAL_SHFT 0x3 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_APSS_KRYO_PP_DISABLE_BMSK 0x4 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_APSS_KRYO_PP_DISABLE_SHFT 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_L3_SIZE_RED_BMSK 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_L3_SIZE_RED_SHFT 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_LSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001ec) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001ec) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001ec) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_RSVD_BMSK 0xfffffc00 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_RSVD_SHFT 0xa #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_EN_BMSK 0x200 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_EN_SHFT 0x9 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_EN_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_EN_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_HALF_BMSK 0x100 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_HALF_SHFT 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_TURING_Q6SS_PLL_L_MAX_15_8_BMSK 0xff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_M_ROW3_MSB_TURING_Q6SS_PLL_L_MAX_15_8_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001f0) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001f0) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001f0) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_RMSK 0xfeffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_SM_BIST_DISABLE_BMSK 0x80000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_SM_BIST_DISABLE_SHFT 0x1f #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_SM_BIST_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_SM_BIST_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_TIC_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_TIC_DISABLE_SHFT 0x1e #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_TIC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_TIC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_FUSE_SW_OVERRIDE_SOC_HW_VER_EN_BMSK 0x20000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_FUSE_SW_OVERRIDE_SOC_HW_VER_EN_SHFT 0x1d #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRNG_TESTMODE_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRNG_TESTMODE_DISABLE_SHFT 0x1c #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRNG_TESTMODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRNG_TESTMODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK 0xe000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT 0x19 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_ENABLE_PATCHING_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_DISABLE_PATCHING_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT 0x17 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT 0x16 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK 0x200000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT 0x15 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK 0x100000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT 0x14 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK 0x80000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT 0x13 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC_DEBUG_DISABLE_BMSK 0x40000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC_DEBUG_DISABLE_SHFT 0x12 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_NIDEN_DISABLE_BMSK 0x20000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_NIDEN_DISABLE_SHFT 0x11 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_DBGEN_DISABLE_BMSK 0x10000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_DBGEN_DISABLE_SHFT 0x10 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK 0x8000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT 0xf #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK 0x4000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT 0xe #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT 0xd #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT 0xc #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK 0x800 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT 0xb #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK 0x400 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT 0xa #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK 0x200 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT 0x9 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK 0x100 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK 0x80 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT 0x7 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK 0x40 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT 0x6 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK 0x20 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT 0x5 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK 0x10 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT 0x4 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT 0x3 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK 0x4 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001f4) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001f4) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001f4) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_RSVD_BMSK 0x80000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_RSVD_SHFT 0x1f #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_MODEM_PBL_BOOT_BMSK 0x40000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_MODEM_PBL_BOOT_SHFT 0x1e #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_APPS_BOOT_FROM_ROM_BMSK 0x20000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_APPS_BOOT_FROM_ROM_SHFT 0x1d #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ENABLE_DEVICE_IN_TEST_MODE_BMSK 0x10000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ENABLE_DEVICE_IN_TEST_MODE_SHFT 0x1c #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_QTI_ROOT_SIG_FORMAT_SEL_BMSK 0x8000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_QTI_ROOT_SIG_FORMAT_SEL_SHFT 0x1b #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_CE_BAM_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_CE_BAM_DISABLE_SHFT 0x1a #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_CE_BAM_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_CE_BAM_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_BMSK 0x2000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_SHFT 0x19 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ARM_CE_DISABLE_USAGE_BMSK 0x1000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ARM_CE_DISABLE_USAGE_SHFT 0x18 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_BOOT_ROM_CFG_BMSK 0xff0000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_BOOT_ROM_CFG_SHFT 0x10 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_7_BMSK 0x8000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_7_SHFT 0xf #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_6_BMSK 0x4000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_6_SHFT 0xe #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_5_BMSK 0x2000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_5_SHFT 0xd #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_4_BMSK 0x1000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_4_SHFT 0xc #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_3_BMSK 0x800 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_3_SHFT 0xb #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_2_BMSK 0x400 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_2_SHFT 0xa #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_1_BMSK 0x200 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_1_SHFT 0x9 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_0_BMSK 0x100 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_0_SHFT 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE7_BMSK 0x80 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE7_SHFT 0x7 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK 0x40 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT 0x6 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK 0x20 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT 0x5 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK 0x10 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT 0x4 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT 0x3 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK 0x4 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001f8) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001f8) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001f8) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK 0xfffc0000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT 0x12 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_TAP_INSTR_DISABLE_BMSK 0x3ffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_LSB_TAP_INSTR_DISABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001fc) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000001fc) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000001fc) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_SEC_TAP_ACCESS_DISABLE_BMSK 0xfffc0000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_SEC_TAP_ACCESS_DISABLE_SHFT 0x12 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK 0x3ffff #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW1_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000200) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000200) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000200) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_RMSK 0xffff7bdf #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_MODEM_PBL_PATCH_VERSION_BMSK 0xfe000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_MODEM_PBL_PATCH_VERSION_SHFT 0x19 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_PATCH_VERSION_BMSK 0x1fc0000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_PATCH_VERSION_SHFT 0x12 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_BMSK 0x30000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_SHFT 0x10 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_ENUM_600_MHZ_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_XO_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_ENUM_1200_MHZ_FVAL 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_NA_FVAL 0x3 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_VENDOR_LOCK_BMSK 0x7800 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_VENDOR_LOCK_SHFT 0xb #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_BMSK 0x3c0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_SHFT 0x6 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_TSMC_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_GLOBAL_FOUNDRIES_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_SAMSUNG_FVAL 0x2 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_IBM_FVAL 0x3 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_UMC_FVAL 0x4 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_SMIC_FVAL 0x5 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_STACKED_MEMORY_ID_BMSK 0x1f #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_LSB_STACKED_MEMORY_ID_SHFT 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000204) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000204) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000204) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_RMSK 0xffffbfef #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_RSVD_BMSK 0xf0000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_RSVD_SHFT 0x1c #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_BMSK 0xe000000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_SHFT 0x19 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_DISABLED_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_INITIALIZING_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_ACTIVATED_FVAL 0x3 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_DISABLED_ARI_EOL_FVAL 0x7 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_ACCU_RED_DEC_END_VAL_MODEM_BMSK 0x1fe0000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_ACCU_RED_DEC_END_VAL_MODEM_SHFT 0x11 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_KM_BOOT_INIT1_DISABLE_BMSK 0x10000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_KM_BOOT_INIT1_DISABLE_SHFT 0x10 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_KM_BOOT_INIT0_DISABLE_BMSK 0x8000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_KM_BOOT_INIT0_DISABLE_SHFT 0xf #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_APCS_BOOT_TRIGGER_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_APCS_BOOT_TRIGGER_DISABLE_SHFT 0xd #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_APCS_BOOT_TRIGGER_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_APCS_BOOT_TRIGGER_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT 0xc #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_XBL_SEC_AUTH_DISABLE_BMSK 0x800 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_XBL_SEC_AUTH_DISABLE_SHFT 0xb #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_MSM_PKG_TYPE_BMSK 0x400 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_MSM_PKG_TYPE_SHFT 0xa #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_SPSS_CONFIG_MODE_BMSK 0x300 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_SPSS_CONFIG_MODE_SHFT 0x8 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_PERIPH_DRV_STRENGTH_SETTING__BMSK 0xe0 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_PERIPH_DRV_STRENGTH_SETTING__SHFT 0x5 #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_APPS_PBL_PLL_CTRL_BMSK 0xf #define HWIO_QFPROM_RAW_FEATURE_CONFIG_NM_ROW2_MSB_APPS_PBL_PLL_CTRL_SHFT 0x0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000208) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000208) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000208) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_IN) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_XBL0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_XBL0_SHFT 0x0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000020c) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000020c) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000020c) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_IN) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_XBL1_BMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_MSB_XBL1_SHFT 0x0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000210) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000210) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000210) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_IN) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000214) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000214) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000214) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_IN) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_XBL_SEC_BMSK 0xfe000000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_XBL_SEC_SHFT 0x19 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_SPARE_66_56_BMSK 0x1000000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_SPARE_66_56_SHFT 0x18 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_RPM_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_RPM_SHFT 0x11 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_TZ_BMSK 0x1ffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_MSB_TZ_SHFT 0x0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000218) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000218) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000218) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_IN) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_BMSK 0xc0000000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_SHFT 0x1e #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_BMSK 0x3e000000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_SHFT 0x19 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_BMSK 0x1000000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_SHFT 0x18 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_RPMB_KEY_NOT_PROVISIONED_FVAL 0x0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_RPMB_KEY_PROVISIONED_FVAL 0x1 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_BMSK 0xffff00 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_SHFT 0x8 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_SAFESWITCH_BMSK 0xff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_SAFESWITCH_SHFT 0x0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000021c) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000021c) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000021c) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_IN) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_BMSK 0xf0000000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_SHFT 0x1c #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_BMSK 0xffe0000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_SHFT 0x11 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_BMSK 0x1f000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_SHFT 0xc #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_HYPERVISOR_BMSK 0xfff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_MSB_HYPERVISOR_SHFT 0x0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000220) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000220) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000220) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_IN \ in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR, m) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR,v) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_IN) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MSS_BMSK 0xffff0000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MSS_SHFT 0x10 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MISC_BMSK 0xffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_MISC_SHFT 0x0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000224) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000224) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000224) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_IN \ in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR, m) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR,v) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_IN) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_SIMLOCK_BMSK 0x80000000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_SIMLOCK_SHFT 0x1f #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RSVD0_70_BMSK 0x7ffffff0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_RSVD0_70_SHFT 0x4 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_BMSK 0xf #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_SHFT 0x0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000228) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000228) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000228) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_IN \ in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR, m) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR,v) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_IN) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ANTI_ROLLBACK_5_31_13_BMSK 0xffffe000 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ANTI_ROLLBACK_5_31_13_SHFT 0xd #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_SHRM_BMSK 0x1f00 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_SHRM_SHFT 0x8 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_CPUCP_FW_BMSK 0xff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_CPUCP_FW_SHFT 0x0 #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000022c) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000022c) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000022c) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_IN \ in_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR, m) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR,v) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_IN) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ANTI_ROLLBACK_5_63_32_BMSK 0xffffffff #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_MSB_ANTI_ROLLBACK_5_63_32_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000230) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000230) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000230) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_PK_HASH_0_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_LSB_PK_HASH_0_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000234) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000234) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000234) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_PK_HASH_0_63_32_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW0_MSB_PK_HASH_0_63_32_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000238) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000238) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000238) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_PK_HASH_0_95_64_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_LSB_PK_HASH_0_95_64_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000023c) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000023c) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000023c) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_PK_HASH_0_127_96_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW1_MSB_PK_HASH_0_127_96_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000240) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000240) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000240) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_PK_HASH_0_159_128_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_LSB_PK_HASH_0_159_128_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000244) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000244) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000244) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_PK_HASH_0_191_160_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW2_MSB_PK_HASH_0_191_160_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000248) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000248) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000248) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_PK_HASH_0_223_192_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_LSB_PK_HASH_0_223_192_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000024c) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000024c) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000024c) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_PK_HASH_0_255_224_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW3_MSB_PK_HASH_0_255_224_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000250) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000250) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000250) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_PK_HASH_0_287_256_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_LSB_PK_HASH_0_287_256_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000254) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000254) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000254) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_PK_HASH_0_319_288_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW4_MSB_PK_HASH_0_319_288_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000258) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000258) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000258) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_PK_HASH_0_351_320_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_LSB_PK_HASH_0_351_320_SHFT 0x0 #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000025c) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000025c) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000025c) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_IN \ in_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_ADDR) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_ADDR, m) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_ADDR,v) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_IN) #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_PK_HASH_0_383_352_BMSK 0xffffffff #define HWIO_QFPROM_RAW_PK_HASH_0_ROW5_MSB_PK_HASH_0_383_352_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000260) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000260) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000260) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_REFGEN_SOUTHEAST_BGV_TRIM_4_0_BMSK 0xf8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_REFGEN_SOUTHEAST_BGV_TRIM_4_0_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_USB2PHY_RCAL_CODE_BMSK 0x7800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_USB2PHY_RCAL_CODE_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_BANDGAP_TRIM_BMSK 0x7f0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_BANDGAP_TRIM_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_REFGEN_NORTH_BGV_TRIM_BMSK 0xff00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_REFGEN_NORTH_BGV_TRIM_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_REFGEN_SOUTH_BGV_TRIM_BMSK 0xff #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_LSB_REFGEN_SOUTH_BGV_TRIM_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000264) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000264) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000264) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_RMSK 0xffffffe7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B63_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B63_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B62_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B62_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B61_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B61_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B60_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B60_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B59_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B59_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B58_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B58_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B57_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B57_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B56_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B56_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B55_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B55_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B54_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B54_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B53_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B53_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B52_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B52_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B51_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B51_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B50_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B50_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B49_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B49_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B48_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B48_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B47_BMSK 0x8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B47_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B46_BMSK 0x4000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B46_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B45_BMSK 0x2000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B45_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B44_BMSK 0x1000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B44_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B43_BMSK 0x800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B43_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B42_BMSK 0x400 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B42_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B41_BMSK 0x200 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B41_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B40_BMSK 0x100 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B40_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B39_BMSK 0x80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B39_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B38_BMSK 0x40 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B38_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B37_BMSK 0x20 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_SPARE_R76_B37_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_REFGEN_SOUTHEAST_BGV_TRIM_7_5_BMSK 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW0_MSB_REFGEN_SOUTHEAST_BGV_TRIM_7_5_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000268) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000268) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000268) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B31_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B31_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B30_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B30_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B29_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B29_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B28_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B28_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B27_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B27_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B26_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B26_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B25_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B25_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B24_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B24_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B23_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B23_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B22_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B22_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B21_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B21_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B20_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B20_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B19_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B19_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B18_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B18_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B17_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B17_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B16_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B16_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B15_BMSK 0x8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B15_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B14_BMSK 0x4000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B14_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B13_BMSK 0x2000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B13_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B12_BMSK 0x1000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B12_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B11_BMSK 0x800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B11_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B10_BMSK 0x400 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B10_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B9_BMSK 0x200 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B9_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B8_BMSK 0x100 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B8_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B7_BMSK 0x80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B7_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B6_BMSK 0x40 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B6_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B5_BMSK 0x20 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B5_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B4_BMSK 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B4_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B3_BMSK 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B3_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B2_BMSK 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B2_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B1_BMSK 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B1_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B0_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_LSB_SPARE_R77_B0_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000026c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000026c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000026c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B63_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B63_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B62_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B62_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B61_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B61_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B60_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B60_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B59_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B59_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B58_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B58_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B57_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B57_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B56_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B56_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B55_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B55_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B54_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B54_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B53_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B53_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B52_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B52_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B51_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B51_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B50_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B50_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B49_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B49_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B48_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B48_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B47_BMSK 0x8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B47_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B46_BMSK 0x4000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B46_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B45_BMSK 0x2000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B45_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B44_BMSK 0x1000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B44_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B43_BMSK 0x800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B43_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B42_BMSK 0x400 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B42_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B41_BMSK 0x200 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B41_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B40_BMSK 0x100 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B40_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B39_BMSK 0x80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B39_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B38_BMSK 0x40 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B38_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B37_BMSK 0x20 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B37_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B36_BMSK 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B36_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B35_BMSK 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B35_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B34_BMSK 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B34_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B33_BMSK 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B33_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B32_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW1_MSB_SPARE_R77_B32_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000270) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000270) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000270) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_NOM_BMSK 0xf0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_NOM_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_TUR_BMSK 0xf000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_TUR_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_SUT_BMSK 0xf00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_SUT_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SVS2_BMSK 0xf8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SVS2_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SVS_BMSK 0x7c00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SVS_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_NOM_BMSK 0x3e0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_NOM_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SUT_BMSK 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SUT_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000274) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000274) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000274) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_SVS_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_SVS_1_0_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_NOM_BMSK 0x3e000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_NOM_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_TUR_BMSK 0x1f00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_TUR_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR0_AGING_BMSK 0xff000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR0_AGING_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_BMSK 0xf00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVS_BMSK 0xf0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVS_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVSL1_BMSK 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVSL1_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000278) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000278) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000278) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_AGING_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_AGING_3_0_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVS2_BMSK 0xf000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVS2_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVS_BMSK 0xf00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVS_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVSL1_BMSK 0xf0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVSL1_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_NOM_BMSK 0xf000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_NOM_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_TUR_BMSK 0xf00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_TUR_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_SVS2_BMSK 0xf8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_SVS2_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_SVS_4_2_BMSK 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_SVS_4_2_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000027c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000027c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000027c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_OFFSET_TUR_2_0_BMSK 0xe0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_OFFSET_TUR_2_0_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVS2_BMSK 0x1f000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVS2_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVS_BMSK 0xf80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVS_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVSP_BMSK 0x7c000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVSP_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_NOM_BMSK 0x3e00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_NOM_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SUT_BMSK 0x1f0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SUT_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR1_AGING_7_4_BMSK 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW3_MSB_CPR1_AGING_7_4_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000280) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000280) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000280) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_AGING_2_0_BMSK 0xe0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_AGING_2_0_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SUT_BMSK 0x1e000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SUT_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVS2_BMSK 0x1e00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVS2_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVS_BMSK 0x1e0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVS_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVSL2_BMSK 0x1e000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVSL2_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVSL1_BMSK 0x1e00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVSL1_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_NOMP_BMSK 0x1e0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_NOMP_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_NOM_BMSK 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_NOM_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_TUR_3_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_TUR_3_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000284) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000284) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000284) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR4_TARG_VOLT_NOM_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR4_TARG_VOLT_NOM_1_0_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR4_TARG_VOLT_TUR_BMSK 0x3e000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR4_TARG_VOLT_TUR_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SVS2_BMSK 0x1f00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SVS2_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SVS_BMSK 0xf8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SVS_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_NOM_BMSK 0x7c00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_NOM_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SUT_BMSK 0x3e0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SUT_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR2_AGING_7_3_BMSK 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW4_MSB_CPR2_AGING_7_3_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000288) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000288) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000288) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR5_TARG_VOLT_SUT_2_0_BMSK 0xe0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR5_TARG_VOLT_SUT_2_0_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SUT_BMSK 0x1e000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SUT_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SVSP_BMSK 0x1e00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SVSP_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_NOM_BMSK 0x1e0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_NOM_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_TUR_BMSK 0x1e000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_TUR_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_SUT_BMSK 0x1f00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_SUT_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_SVSP_BMSK 0xf8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_SVSP_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_NOM_4_2_BMSK 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_NOM_4_2_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000028c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000028c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000028c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_SVS_BMSK 0xf8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_SVS_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_NOM_BMSK 0x7c00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_NOM_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_TUR_BMSK 0x3e0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_TUR_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_TUR_BMSK 0x1f000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_TUR_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_SVSP_BMSK 0xf80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_SVSP_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_NOM_BMSK 0x7c #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_NOM_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_SUT_4_3_BMSK 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_SUT_4_3_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000290) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000290) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000290) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_SVSL1_BMSK 0xf0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_SVSL1_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_NOM_BMSK 0xf000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_NOM_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_TUR_BMSK 0xf00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_TUR_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_SVS2_BMSK 0xf8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_SVS2_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_SVS_BMSK 0x7c00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_SVS_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_NOM_BMSK 0x3e0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_NOM_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_TUR_BMSK 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_TUR_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000294) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000294) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000294) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_SVS2_0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_SVS2_0_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_SVS_BMSK 0x7c000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_SVS_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_NOM_BMSK 0x3e00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_NOM_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_TUR_BMSK 0x1f0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_TUR_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR7_AGING_BMSK 0xff00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR7_AGING_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR7_TARG_VOLT_OFFSET_SVS2_BMSK 0xf0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR7_TARG_VOLT_OFFSET_SVS2_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR7_TARG_VOLT_OFFSET_SVS_BMSK 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW6_MSB_CPR7_TARG_VOLT_OFFSET_SVS_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000298) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000298) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000298) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_AGING_BMSK 0xff000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_AGING_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVS2_BMSK 0xf00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVS2_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVS_BMSK 0xf0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVS_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVSL1_BMSK 0xf000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVSL1_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_NOM_BMSK 0xf00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_NOM_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_TUR_BMSK 0xf0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_TUR_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_SVS2_4_1_BMSK 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_SVS2_4_1_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000029c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000029c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000029c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_SVS_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_SVS_3_0_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_NOM_BMSK 0xfc00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_NOM_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_TUR_BMSK 0x3f0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_TUR_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_CPR_GLOBAL_RC_BMSK 0xe000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_CPR_GLOBAL_RC_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_AON_AGING_BMSK 0x1fe0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_AON_AGING_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_AON_TARG_VOLT_BMSK 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW7_MSB_AON_TARG_VOLT_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002a0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002a0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002a0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_CPR9_NOMINAL_QUOT_MIN_BMSK 0xfff00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_CPR9_NOMINAL_QUOT_MIN_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_CPR9_TURBO_QUOT_MIN_BMSK 0xfff00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_CPR9_TURBO_QUOT_MIN_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_CPR9_TARG_VOLT_SVS2_BMSK 0xfc #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_CPR9_TARG_VOLT_SVS2_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_CPR9_TARG_VOLT_SVS_5_4_BMSK 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_LSB_CPR9_TARG_VOLT_SVS_5_4_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002a4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002a4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002a4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_CPR9_QUOT_OFFSET_TUR_BMSK 0xff000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_CPR9_QUOT_OFFSET_TUR_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_CPR9_SVS2_QUOT_MIN_BMSK 0xfff000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_CPR9_SVS2_QUOT_MIN_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_CPR9_SVS_QUOT_MIN_BMSK 0xfff #define HWIO_QFPROM_RAW_CALIBRATION_ROW8_MSB_CPR9_SVS_QUOT_MIN_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002a8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002a8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002a8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_CPR10_TARG_VOLT_NOM_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_CPR10_TARG_VOLT_NOM_3_0_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_CPR10_TARG_VOLT_TUR_BMSK 0xfc00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_CPR10_TARG_VOLT_TUR_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_CPR9_AGING_BMSK 0x3fc000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_CPR9_AGING_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_CPR9_QUOT_OFFSET_SVS_BMSK 0x3f80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_CPR9_QUOT_OFFSET_SVS_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_CPR9_QUOT_OFFSET_NOM_BMSK 0x7f #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_LSB_CPR9_QUOT_OFFSET_NOM_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002ac) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002ac) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002ac) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_CPR10_NOMINAL_QUOT_MIN_5_0_BMSK 0xfc000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_CPR10_NOMINAL_QUOT_MIN_5_0_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_CPR10_TURBO_QUOT_MIN_BMSK 0x3ffc000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_CPR10_TURBO_QUOT_MIN_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_SVS2_BMSK 0x3f00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_SVS2_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_SVS_BMSK 0xfc #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_SVS_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_NOM_5_4_BMSK 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_NOM_5_4_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002b0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002b0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002b0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_CPR10_QUOT_OFFSET_TUR_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_CPR10_QUOT_OFFSET_TUR_1_0_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_CPR10_SVS2_QUOT_MIN_BMSK 0x3ffc0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_CPR10_SVS2_QUOT_MIN_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_CPR10_SVS_QUOT_MIN_BMSK 0x3ffc0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_CPR10_SVS_QUOT_MIN_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_CPR10_NOMINAL_QUOT_MIN_11_6_BMSK 0x3f #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_LSB_CPR10_NOMINAL_QUOT_MIN_11_6_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002b4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002b4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002b4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_CPR11_TARG_VOLT_NOM_BMSK 0xfc000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_CPR11_TARG_VOLT_NOM_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_CPR11_TARG_VOLT_TUR_BMSK 0x3f00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_CPR11_TARG_VOLT_TUR_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_SVS_BMSK 0xfe000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_SVS_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_NOM_BMSK 0x1fc0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_NOM_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_TUR_7_2_BMSK 0x3f #define HWIO_QFPROM_RAW_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_TUR_7_2_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002b8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002b8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002b8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_CPR11_NOMINAL_QUOT_MIN_7_0_BMSK 0xff000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_CPR11_NOMINAL_QUOT_MIN_7_0_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_CPR11_TURBO_QUOT_MIN_BMSK 0xfff000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_CPR11_TURBO_QUOT_MIN_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_CPR11_TARG_VOLT_SVS2_BMSK 0xfc0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_CPR11_TARG_VOLT_SVS2_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_CPR11_TARG_VOLT_SVS_BMSK 0x3f #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_LSB_CPR11_TARG_VOLT_SVS_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002bc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002bc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002bc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_CPR11_QUOT_OFFSET_TUR_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_CPR11_QUOT_OFFSET_TUR_3_0_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_CPR11_SVS2_QUOT_MIN_BMSK 0xfff0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_CPR11_SVS2_QUOT_MIN_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_CPR11_SVS_QUOT_MIN_BMSK 0xfff0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_CPR11_SVS_QUOT_MIN_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_CPR11_NOMINAL_QUOT_MIN_11_8_BMSK 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW11_MSB_CPR11_NOMINAL_QUOT_MIN_11_8_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002c0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002c0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002c0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_CPR12_TARG_VOLT_TUR_BMSK 0xfc000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_CPR12_TARG_VOLT_TUR_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_CPR11_AGING_BMSK 0x3fc0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_CPR11_AGING_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_SVS_BMSK 0x3f800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_SVS_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_NOM_BMSK 0x7f0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_NOM_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_TUR_7_4_BMSK 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_TUR_7_4_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002c4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002c4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002c4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_CPR12_NOMINAL_QUOT_MIN_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_CPR12_NOMINAL_QUOT_MIN_1_0_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_CPR12_TURBO_QUOT_MIN_BMSK 0x3ffc0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_CPR12_TURBO_QUOT_MIN_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_SVS2_BMSK 0x3f000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_SVS2_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_SVS_BMSK 0xfc0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_SVS_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_NOM_BMSK 0x3f #define HWIO_QFPROM_RAW_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_NOM_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002c8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002c8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002c8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_CPR12_SVS2_QUOT_MIN_9_0_BMSK 0xffc00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_CPR12_SVS2_QUOT_MIN_9_0_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_CPR12_SVS_QUOT_MIN_BMSK 0x3ffc00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_CPR12_SVS_QUOT_MIN_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_CPR12_NOMINAL_QUOT_MIN_11_2_BMSK 0x3ff #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_LSB_CPR12_NOMINAL_QUOT_MIN_11_2_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002cc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002cc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002cc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR_MSS_MODE_DISABLE_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR_MSS_MODE_DISABLE_1_0_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR_CX_MODE_DISABLE_BMSK 0x38000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR_CX_MODE_DISABLE_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR_LOCAL_RC_BMSK 0x7000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR_LOCAL_RC_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_SVS_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_SVS_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_NOM_BMSK 0x1fc00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_NOM_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_TUR_BMSK 0x3fc #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_TUR_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR12_SVS2_QUOT_MIN_11_10_BMSK 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW13_MSB_CPR12_SVS2_QUOT_MIN_11_10_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002d0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002d0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002d0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_RESERVED_12_0_BMSK 0xfff80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_RESERVED_12_0_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_MMCX_MODE_DISABLE_BMSK 0x70000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_MMCX_MODE_DISABLE_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_SSCX_MODE_DISABLE_BMSK 0xe000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_SSCX_MODE_DISABLE_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_LPIMX_MODE_DISABLE_BMSK 0x1c00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_LPIMX_MODE_DISABLE_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_MX_MODE_DISABLE_BMSK 0x380 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_MX_MODE_DISABLE_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_DDR_MODE_DISABLE_BMSK 0x70 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_DDR_MODE_DISABLE_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_GFX_MODE_DISABLE_BMSK 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_GFX_MODE_DISABLE_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_MSS_MODE_DISABLE_2_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_LSB_CPR_MSS_MODE_DISABLE_2_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002d4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002d4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002d4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_SPARE_R90_B63_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_SPARE_R90_B63_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_SPARE_R90_B62_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_SPARE_R90_B62_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_SPARE_R90_B61_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_SPARE_R90_B61_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_SPARE_R90_B60_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_SPARE_R90_B60_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_CPR_RESERVED_40_13_BMSK 0xfffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW14_MSB_CPR_RESERVED_40_13_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002d8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002d8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002d8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_TSENS1_BASE1_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_TSENS1_BASE1_1_0_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_TSENS0_BASE1_BMSK 0x3ff00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_TSENS0_BASE1_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_TSENS1_BASE0_BMSK 0xffc00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_TSENS1_BASE0_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_TSENS0_BASE0_BMSK 0x3ff #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_LSB_TSENS0_BASE0_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002dc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002dc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002dc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS4_OFFSET_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS4_OFFSET_3_0_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS3_OFFSET_BMSK 0xf800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS3_OFFSET_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS2_OFFSET_BMSK 0x7c0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS2_OFFSET_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS1_OFFSET_BMSK 0x3e000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS1_OFFSET_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS0_OFFSET_BMSK 0x1f00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS0_OFFSET_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS1_BASE1_9_2_BMSK 0xff #define HWIO_QFPROM_RAW_CALIBRATION_ROW15_MSB_TSENS1_BASE1_9_2_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002e0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002e0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002e0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS11_OFFSET_0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS11_OFFSET_0_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS10_OFFSET_BMSK 0x7c000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS10_OFFSET_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS9_OFFSET_BMSK 0x3e00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS9_OFFSET_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS8_OFFSET_BMSK 0x1f0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS8_OFFSET_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS7_OFFSET_BMSK 0xf800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS7_OFFSET_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS6_OFFSET_BMSK 0x7c0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS6_OFFSET_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS5_OFFSET_BMSK 0x3e #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS5_OFFSET_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS4_OFFSET_4_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_LSB_TSENS4_OFFSET_4_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002e4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002e4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002e4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS17_OFFSET_2_0_BMSK 0xe0000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS17_OFFSET_2_0_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS16_OFFSET_BMSK 0x1f000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS16_OFFSET_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS15_OFFSET_BMSK 0xf80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS15_OFFSET_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS14_OFFSET_BMSK 0x7c000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS14_OFFSET_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS13_OFFSET_BMSK 0x3e00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS13_OFFSET_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS12_OFFSET_BMSK 0x1f0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS12_OFFSET_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS11_OFFSET_4_1_BMSK 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW16_MSB_TSENS11_OFFSET_4_1_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002e8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002e8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002e8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS23_OFFSET_BMSK 0xf8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS23_OFFSET_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS22_OFFSET_BMSK 0x7c00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS22_OFFSET_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS21_OFFSET_BMSK 0x3e0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS21_OFFSET_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS20_OFFSET_BMSK 0x1f000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS20_OFFSET_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS19_OFFSET_BMSK 0xf80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS19_OFFSET_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS18_OFFSET_BMSK 0x7c #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS18_OFFSET_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS17_OFFSET_4_3_BMSK 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_LSB_TSENS17_OFFSET_4_3_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002ec) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002ec) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002ec) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_SPARE_R93_B63_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_SPARE_R93_B63_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_SPARE_R93_B62_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_SPARE_R93_B62_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_SPARE_R93_B61_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_SPARE_R93_B61_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_SPARE_R93_B60_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_SPARE_R93_B60_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS_CAL_SEL_BMSK 0xe000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS_CAL_SEL_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS28_OFFSET_BMSK 0x1f00000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS28_OFFSET_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS27_OFFSET_BMSK 0xf8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS27_OFFSET_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS26_OFFSET_BMSK 0x7c00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS26_OFFSET_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS25_OFFSET_BMSK 0x3e0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS25_OFFSET_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS24_OFFSET_BMSK 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW17_MSB_TSENS24_OFFSET_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002f0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002f0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002f0) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_RMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_SPARE_R94_B0_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_LSB_SPARE_R94_B0_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002f4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002f4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002f4) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW18_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002f8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002f8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002f8) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_LSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000002fc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000002fc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000002fc) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW19_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000300) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000300) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000300) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_LSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000304) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000304) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000304) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW20_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000308) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000308) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000308) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_LSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000030c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000030c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000030c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW21_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000310) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000310) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000310) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_LSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000314) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000314) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000314) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW22_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000318) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000318) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000318) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_RMSK 0xfffffffe #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_AOSS_P1_12_0_BMSK 0xfff80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_AOSS_P1_12_0_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_AOSS_N1_BMSK 0x7fffe #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_LSB_AOSS_N1_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000031c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000031c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000031c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_LPASS_N1_4_0_BMSK 0xf8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_LPASS_N1_4_0_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_AOSS_K_BMSK 0x7fff800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_AOSS_K_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_AOSS_TDOPCODE_BMSK 0x700 #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_AOSS_TDOPCODE_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_AOSS_RDOPCODE_BMSK 0xe0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_AOSS_RDOPCODE_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_AOSS_P1_17_13_BMSK 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW23_MSB_AOSS_P1_17_13_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000320) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000320) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000320) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_LPASS_RDOPCODE_0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_LPASS_RDOPCODE_0_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_LPASS_P1_BMSK 0x7fffe000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_LPASS_P1_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_LPASS_N1_17_5_BMSK 0x1fff #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_LSB_LPASS_N1_17_5_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000324) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000324) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000324) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B63_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B63_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B62_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B62_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B61_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B61_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B60_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B60_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B59_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B59_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B58_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B58_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B57_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B57_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B56_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B56_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B55_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B55_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B54_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B54_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B53_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_SPARE_R100_B53_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_LPASS_K_BMSK 0x1fffe0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_LPASS_K_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_LPASS_TDOPCODE_BMSK 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_LPASS_TDOPCODE_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_LPASS_RDOPCODE_2_1_BMSK 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW24_MSB_LPASS_RDOPCODE_2_1_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000328) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000328) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000328) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B31_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B31_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B30_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B30_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B29_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B29_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B28_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B28_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B27_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B27_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B26_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B26_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B25_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B25_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B24_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B24_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B23_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B23_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B22_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B22_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B21_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B21_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B20_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B20_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B19_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B19_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B18_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B18_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B17_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B17_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B16_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B16_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B15_BMSK 0x8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B15_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B14_BMSK 0x4000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B14_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B13_BMSK 0x2000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B13_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B12_BMSK 0x1000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B12_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B11_BMSK 0x800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B11_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B10_BMSK 0x400 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B10_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B9_BMSK 0x200 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B9_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B8_BMSK 0x100 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B8_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B7_BMSK 0x80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B7_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B6_BMSK 0x40 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B6_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B5_BMSK 0x20 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B5_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B4_BMSK 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B4_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B3_BMSK 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B3_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B2_BMSK 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B2_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B1_BMSK 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B1_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B0_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_LSB_SPARE_R101_B0_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000032c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000032c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000032c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B63_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B63_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B62_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B62_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B61_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B61_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B60_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B60_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B59_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B59_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B58_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B58_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B57_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B57_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B56_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B56_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B55_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B55_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B54_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B54_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B53_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B53_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B52_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B52_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B51_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B51_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B50_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B50_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B49_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B49_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B48_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B48_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B47_BMSK 0x8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B47_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B46_BMSK 0x4000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B46_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B45_BMSK 0x2000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B45_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B44_BMSK 0x1000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B44_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B43_BMSK 0x800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B43_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B42_BMSK 0x400 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B42_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B41_BMSK 0x200 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B41_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B40_BMSK 0x100 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B40_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B39_BMSK 0x80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B39_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B38_BMSK 0x40 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B38_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B37_BMSK 0x20 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B37_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B36_BMSK 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B36_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B35_BMSK 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B35_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B34_BMSK 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B34_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B33_BMSK 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B33_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B32_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW25_MSB_SPARE_R101_B32_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000330) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000330) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000330) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B31_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B31_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B30_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B30_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B29_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B29_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B28_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B28_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B27_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B27_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B26_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B26_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B25_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B25_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B24_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B24_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B23_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B23_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B22_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B22_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B21_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B21_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B20_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B20_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B19_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B19_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B18_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B18_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B17_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B17_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B16_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B16_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B15_BMSK 0x8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B15_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B14_BMSK 0x4000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B14_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B13_BMSK 0x2000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B13_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B12_BMSK 0x1000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B12_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B11_BMSK 0x800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B11_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B10_BMSK 0x400 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B10_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B9_BMSK 0x200 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B9_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B8_BMSK 0x100 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B8_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B7_BMSK 0x80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B7_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B6_BMSK 0x40 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B6_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B5_BMSK 0x20 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B5_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B4_BMSK 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B4_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B3_BMSK 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B3_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B2_BMSK 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B2_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B1_BMSK 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B1_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B0_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_LSB_SPARE_R102_B0_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000334) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000334) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000334) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B63_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B63_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B62_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B62_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B61_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B61_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B60_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B60_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B59_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B59_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B58_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B58_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B57_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B57_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B56_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B56_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B55_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B55_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B54_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B54_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B53_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B53_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B52_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B52_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B51_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B51_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B50_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B50_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B49_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B49_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B48_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B48_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B47_BMSK 0x8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B47_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B46_BMSK 0x4000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B46_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B45_BMSK 0x2000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B45_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B44_BMSK 0x1000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B44_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B43_BMSK 0x800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B43_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B42_BMSK 0x400 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B42_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B41_BMSK 0x200 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B41_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B40_BMSK 0x100 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B40_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B39_BMSK 0x80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B39_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B38_BMSK 0x40 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B38_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B37_BMSK 0x20 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B37_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B36_BMSK 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B36_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B35_BMSK 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B35_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B34_BMSK 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B34_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B33_BMSK 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B33_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B32_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW26_MSB_SPARE_R102_B32_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000338) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000338) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000338) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B31_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B31_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B30_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B30_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B29_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B29_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B28_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B28_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B27_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B27_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B26_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B26_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B25_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B25_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B24_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B24_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B23_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B23_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B22_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B22_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B21_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B21_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B20_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B20_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B19_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B19_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B18_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B18_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B17_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B17_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B16_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B16_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B15_BMSK 0x8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B15_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B14_BMSK 0x4000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B14_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B13_BMSK 0x2000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B13_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B12_BMSK 0x1000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B12_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B11_BMSK 0x800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B11_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B10_BMSK 0x400 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B10_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B9_BMSK 0x200 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B9_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B8_BMSK 0x100 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B8_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B7_BMSK 0x80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B7_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B6_BMSK 0x40 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B6_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B5_BMSK 0x20 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B5_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B4_BMSK 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B4_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B3_BMSK 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B3_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B2_BMSK 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B2_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B1_BMSK 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B1_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B0_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_LSB_SPARE_R103_B0_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000033c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000033c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000033c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B63_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B63_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B62_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B62_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B61_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B61_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B60_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B60_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B59_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B59_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B58_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B58_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B57_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B57_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B56_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B56_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B55_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B55_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B54_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B54_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B53_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B53_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B52_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B52_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B51_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B51_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B50_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B50_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B49_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B49_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B48_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B48_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B47_BMSK 0x8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B47_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B46_BMSK 0x4000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B46_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B45_BMSK 0x2000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B45_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B44_BMSK 0x1000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B44_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B43_BMSK 0x800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B43_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B42_BMSK 0x400 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B42_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B41_BMSK 0x200 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B41_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B40_BMSK 0x100 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B40_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B39_BMSK 0x80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B39_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B38_BMSK 0x40 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B38_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B37_BMSK 0x20 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B37_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B36_BMSK 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B36_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B35_BMSK 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B35_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B34_BMSK 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B34_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B33_BMSK 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B33_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B32_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW27_MSB_SPARE_R103_B32_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000340) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000340) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000340) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B31_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B31_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B30_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B30_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B29_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B29_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B28_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B28_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B27_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B27_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B26_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B26_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B25_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B25_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B24_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B24_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B23_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B23_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B22_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B22_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B21_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B21_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B20_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B20_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B19_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B19_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B18_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B18_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B17_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B17_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B16_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B16_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B15_BMSK 0x8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B15_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B14_BMSK 0x4000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B14_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B13_BMSK 0x2000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B13_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B12_BMSK 0x1000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B12_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B11_BMSK 0x800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B11_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B10_BMSK 0x400 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B10_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B9_BMSK 0x200 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B9_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B8_BMSK 0x100 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B8_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B7_BMSK 0x80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B7_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B6_BMSK 0x40 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B6_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B5_BMSK 0x20 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B5_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B4_BMSK 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B4_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B3_BMSK 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B3_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B2_BMSK 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B2_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B1_BMSK 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B1_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B0_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_LSB_SPARE_R104_B0_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000344) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000344) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000344) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B63_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B63_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B62_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B62_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B61_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B61_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B60_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B60_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B59_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B59_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B58_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B58_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B57_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B57_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B56_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B56_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B55_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B55_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B54_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B54_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B53_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B53_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B52_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B52_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B51_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B51_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B50_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B50_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B49_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B49_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B48_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B48_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B47_BMSK 0x8000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B47_SHFT 0xf #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B46_BMSK 0x4000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B46_SHFT 0xe #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B45_BMSK 0x2000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B45_SHFT 0xd #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B44_BMSK 0x1000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B44_SHFT 0xc #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B43_BMSK 0x800 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B43_SHFT 0xb #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B42_BMSK 0x400 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B42_SHFT 0xa #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B41_BMSK 0x200 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B41_SHFT 0x9 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B40_BMSK 0x100 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B40_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B39_BMSK 0x80 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B39_SHFT 0x7 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B38_BMSK 0x40 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B38_SHFT 0x6 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B37_BMSK 0x20 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B37_SHFT 0x5 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B36_BMSK 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B36_SHFT 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B35_BMSK 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B35_SHFT 0x3 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B34_BMSK 0x4 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B34_SHFT 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B33_BMSK 0x2 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B33_SHFT 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B32_BMSK 0x1 #define HWIO_QFPROM_RAW_CALIBRATION_ROW28_MSB_SPARE_R104_B32_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000348) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000348) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000348) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_Q6_ACD_DVM_VAL1_7_0_BMSK 0xff000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_Q6_ACD_DVM_VAL1_7_0_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_Q6_ACD_DVM_VAL0_BMSK 0xffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_LSB_Q6_ACD_DVM_VAL0_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000034c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000034c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000034c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_Q6_ACD_DVM_VAL2_15_0_BMSK 0xffff0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_Q6_ACD_DVM_VAL2_15_0_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_Q6_ACD_DVM_VAL1_23_8_BMSK 0xffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW29_MSB_Q6_ACD_DVM_VAL1_23_8_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000350) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000350) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000350) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_Q6_ACD_DVM_VAL3_BMSK 0xffffff00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_Q6_ACD_DVM_VAL3_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_Q6_ACD_DVM_VAL2_23_16_BMSK 0xff #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_LSB_Q6_ACD_DVM_VAL2_23_16_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000354) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000354) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000354) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_Q6_ACD_DVM_VAL5_7_0_BMSK 0xff000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_Q6_ACD_DVM_VAL5_7_0_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_Q6_ACD_DVM_VAL4_BMSK 0xffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW30_MSB_Q6_ACD_DVM_VAL4_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000358) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000358) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000358) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_Q6_ACD_DVM_VAL6_15_0_BMSK 0xffff0000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_Q6_ACD_DVM_VAL6_15_0_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_Q6_ACD_DVM_VAL5_23_8_BMSK 0xffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_LSB_Q6_ACD_DVM_VAL5_23_8_SHFT 0x0 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000035c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000035c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000035c) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_IN \ in_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_ADDR) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_ADDR, m) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_ADDR,v) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_ADDR,m,v,HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_IN) #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B63_BMSK 0x80000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B63_SHFT 0x1f #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B62_BMSK 0x40000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B62_SHFT 0x1e #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B61_BMSK 0x20000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B61_SHFT 0x1d #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B60_BMSK 0x10000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B60_SHFT 0x1c #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B59_BMSK 0x8000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B59_SHFT 0x1b #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B58_BMSK 0x4000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B58_SHFT 0x1a #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B57_BMSK 0x2000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B57_SHFT 0x19 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B56_BMSK 0x1000000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B56_SHFT 0x18 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B55_BMSK 0x800000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B55_SHFT 0x17 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B54_BMSK 0x400000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B54_SHFT 0x16 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B53_BMSK 0x200000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B53_SHFT 0x15 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B52_BMSK 0x100000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B52_SHFT 0x14 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B51_BMSK 0x80000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B51_SHFT 0x13 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B50_BMSK 0x40000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B50_SHFT 0x12 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B49_BMSK 0x20000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B49_SHFT 0x11 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B48_BMSK 0x10000 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_SPARE_R107_B48_SHFT 0x10 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_Q6_ACD_DVM_ENABLE_BMSK 0xff00 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_Q6_ACD_DVM_ENABLE_SHFT 0x8 #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_Q6_ACD_DVM_VAL6_23_16_BMSK 0xff #define HWIO_QFPROM_RAW_CALIBRATION_ROW31_MSB_Q6_ACD_DVM_VAL6_23_16_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000360) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000360) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000360) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_MEMORY_REDUNDANCY_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_LSB_MEMORY_REDUNDANCY_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000364) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000364) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000364) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_MEMORY_REDUNDANCY_63_32_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW0_MSB_MEMORY_REDUNDANCY_63_32_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000368) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000368) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000368) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_MEMORY_REDUNDANCY_95_64_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_LSB_MEMORY_REDUNDANCY_95_64_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000036c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000036c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000036c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_MEMORY_REDUNDANCY_127_96_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW1_MSB_MEMORY_REDUNDANCY_127_96_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000370) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000370) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000370) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_MEMORY_REDUNDANCY_159_128_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_LSB_MEMORY_REDUNDANCY_159_128_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000374) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000374) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000374) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_MEMORY_REDUNDANCY_191_160_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW2_MSB_MEMORY_REDUNDANCY_191_160_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000378) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000378) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000378) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_MEMORY_REDUNDANCY_223_192_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_LSB_MEMORY_REDUNDANCY_223_192_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000037c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000037c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000037c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_MEMORY_REDUNDANCY_255_224_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW3_MSB_MEMORY_REDUNDANCY_255_224_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000380) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000380) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000380) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_MEMORY_REDUNDANCY_287_256_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_LSB_MEMORY_REDUNDANCY_287_256_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000384) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000384) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000384) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_MEMORY_REDUNDANCY_319_288_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW4_MSB_MEMORY_REDUNDANCY_319_288_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000388) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000388) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000388) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_MEMORY_REDUNDANCY_351_320_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_LSB_MEMORY_REDUNDANCY_351_320_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000038c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000038c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000038c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_MEMORY_REDUNDANCY_383_352_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW5_MSB_MEMORY_REDUNDANCY_383_352_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000390) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000390) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000390) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_MEMORY_REDUNDANCY_415_384_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_LSB_MEMORY_REDUNDANCY_415_384_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000394) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000394) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000394) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_MEMORY_REDUNDANCY_447_416_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW6_MSB_MEMORY_REDUNDANCY_447_416_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000398) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000398) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000398) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_MEMORY_REDUNDANCY_479_448_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_LSB_MEMORY_REDUNDANCY_479_448_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000039c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000039c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000039c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_MEMORY_REDUNDANCY_511_480_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW7_MSB_MEMORY_REDUNDANCY_511_480_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003a0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003a0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003a0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_MEMORY_REDUNDANCY_543_512_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_LSB_MEMORY_REDUNDANCY_543_512_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003a4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003a4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003a4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_MEMORY_REDUNDANCY_575_544_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW8_MSB_MEMORY_REDUNDANCY_575_544_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003a8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003a8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003a8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_MEMORY_REDUNDANCY_607_576_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_LSB_MEMORY_REDUNDANCY_607_576_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003ac) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003ac) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003ac) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_MEMORY_REDUNDANCY_639_608_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW9_MSB_MEMORY_REDUNDANCY_639_608_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003b0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003b0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003b0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_MEMORY_REDUNDANCY_671_640_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_LSB_MEMORY_REDUNDANCY_671_640_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003b4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003b4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003b4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_MEMORY_REDUNDANCY_703_672_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW10_MSB_MEMORY_REDUNDANCY_703_672_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003b8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003b8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003b8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_MEMORY_REDUNDANCY_735_704_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_LSB_MEMORY_REDUNDANCY_735_704_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003bc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003bc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003bc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_MEMORY_REDUNDANCY_767_736_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW11_MSB_MEMORY_REDUNDANCY_767_736_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003c0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003c0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003c0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_MEMORY_REDUNDANCY_799_768_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_LSB_MEMORY_REDUNDANCY_799_768_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003c4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003c4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003c4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_MEMORY_REDUNDANCY_831_800_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW12_MSB_MEMORY_REDUNDANCY_831_800_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003c8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003c8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003c8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_MEMORY_REDUNDANCY_863_832_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_LSB_MEMORY_REDUNDANCY_863_832_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003cc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003cc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003cc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_MEMORY_REDUNDANCY_895_864_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW13_MSB_MEMORY_REDUNDANCY_895_864_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003d0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003d0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003d0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_MEMORY_REDUNDANCY_927_896_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_LSB_MEMORY_REDUNDANCY_927_896_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003d4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003d4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003d4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_MEMORY_REDUNDANCY_959_928_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW14_MSB_MEMORY_REDUNDANCY_959_928_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003d8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003d8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003d8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_MEMORY_REDUNDANCY_991_960_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_LSB_MEMORY_REDUNDANCY_991_960_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003dc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003dc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003dc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_MEMORY_REDUNDANCY_1023_992_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW15_MSB_MEMORY_REDUNDANCY_1023_992_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003e0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003e0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003e0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_MEMORY_REDUNDANCY_1055_1024_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_LSB_MEMORY_REDUNDANCY_1055_1024_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003e4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003e4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003e4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_MEMORY_REDUNDANCY_1087_1056_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW16_MSB_MEMORY_REDUNDANCY_1087_1056_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003e8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003e8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003e8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_MEMORY_REDUNDANCY_1119_1088_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_LSB_MEMORY_REDUNDANCY_1119_1088_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003ec) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003ec) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003ec) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_MEMORY_REDUNDANCY_1151_1120_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW17_MSB_MEMORY_REDUNDANCY_1151_1120_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003f0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003f0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003f0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_MEMORY_REDUNDANCY_1183_1152_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_LSB_MEMORY_REDUNDANCY_1183_1152_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003f4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003f4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003f4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_MEMORY_REDUNDANCY_1215_1184_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW18_MSB_MEMORY_REDUNDANCY_1215_1184_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003f8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003f8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003f8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_MEMORY_REDUNDANCY_1247_1216_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_LSB_MEMORY_REDUNDANCY_1247_1216_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000003fc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000003fc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000003fc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_MEMORY_REDUNDANCY_1279_1248_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW19_MSB_MEMORY_REDUNDANCY_1279_1248_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000400) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000400) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000400) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_MEMORY_REDUNDANCY_1311_1280_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_LSB_MEMORY_REDUNDANCY_1311_1280_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000404) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000404) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000404) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_MEMORY_REDUNDANCY_1343_1312_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW20_MSB_MEMORY_REDUNDANCY_1343_1312_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000408) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000408) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000408) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_MEMORY_REDUNDANCY_1375_1344_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_LSB_MEMORY_REDUNDANCY_1375_1344_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000040c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000040c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000040c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_MEMORY_REDUNDANCY_1407_1376_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW21_MSB_MEMORY_REDUNDANCY_1407_1376_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000410) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000410) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000410) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_MEMORY_REDUNDANCY_1439_1408_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_LSB_MEMORY_REDUNDANCY_1439_1408_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000414) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000414) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000414) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_MEMORY_REDUNDANCY_1471_1440_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW22_MSB_MEMORY_REDUNDANCY_1471_1440_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000418) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000418) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000418) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_MEMORY_REDUNDANCY_1503_1472_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_LSB_MEMORY_REDUNDANCY_1503_1472_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000041c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000041c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000041c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_MEMORY_REDUNDANCY_1535_1504_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW23_MSB_MEMORY_REDUNDANCY_1535_1504_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000420) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000420) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000420) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_MEMORY_REDUNDANCY_1567_1536_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_LSB_MEMORY_REDUNDANCY_1567_1536_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000424) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000424) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000424) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_MEMORY_REDUNDANCY_1599_1568_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW24_MSB_MEMORY_REDUNDANCY_1599_1568_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000428) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000428) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000428) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_MEMORY_REDUNDANCY_1631_1600_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_LSB_MEMORY_REDUNDANCY_1631_1600_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000042c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000042c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000042c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_MEMORY_REDUNDANCY_1663_1632_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW25_MSB_MEMORY_REDUNDANCY_1663_1632_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000430) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000430) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000430) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_MEMORY_REDUNDANCY_1695_1664_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_LSB_MEMORY_REDUNDANCY_1695_1664_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000434) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000434) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000434) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_MEMORY_REDUNDANCY_1727_1696_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW26_MSB_MEMORY_REDUNDANCY_1727_1696_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000438) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000438) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000438) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_MEMORY_REDUNDANCY_1759_1728_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_LSB_MEMORY_REDUNDANCY_1759_1728_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000043c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000043c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000043c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_MEMORY_REDUNDANCY_1791_1760_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW27_MSB_MEMORY_REDUNDANCY_1791_1760_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000440) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000440) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000440) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_MEMORY_REDUNDANCY_1823_1792_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_LSB_MEMORY_REDUNDANCY_1823_1792_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000444) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000444) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000444) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_MEMORY_REDUNDANCY_1855_1824_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW28_MSB_MEMORY_REDUNDANCY_1855_1824_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000448) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000448) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000448) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_MEMORY_REDUNDANCY_1887_1856_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_LSB_MEMORY_REDUNDANCY_1887_1856_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000044c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000044c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000044c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_MEMORY_REDUNDANCY_1919_1888_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW29_MSB_MEMORY_REDUNDANCY_1919_1888_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000450) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000450) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000450) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_MEMORY_REDUNDANCY_1951_1920_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_LSB_MEMORY_REDUNDANCY_1951_1920_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000454) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000454) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000454) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_MEMORY_REDUNDANCY_1983_1952_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW30_MSB_MEMORY_REDUNDANCY_1983_1952_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000458) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000458) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000458) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_MEMORY_REDUNDANCY_2015_1984_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_LSB_MEMORY_REDUNDANCY_2015_1984_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000045c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000045c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000045c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_MEMORY_REDUNDANCY_2047_2016_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW31_MSB_MEMORY_REDUNDANCY_2047_2016_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000460) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000460) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000460) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_MEMORY_REDUNDANCY_2079_2048_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_LSB_MEMORY_REDUNDANCY_2079_2048_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000464) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000464) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000464) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_MEMORY_REDUNDANCY_2111_2080_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW32_MSB_MEMORY_REDUNDANCY_2111_2080_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000468) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000468) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000468) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_MEMORY_REDUNDANCY_2143_2112_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_LSB_MEMORY_REDUNDANCY_2143_2112_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000046c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000046c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000046c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_MEMORY_REDUNDANCY_2175_2144_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW33_MSB_MEMORY_REDUNDANCY_2175_2144_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000470) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000470) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000470) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_MEMORY_REDUNDANCY_2207_2176_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_LSB_MEMORY_REDUNDANCY_2207_2176_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000474) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000474) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000474) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_MEMORY_REDUNDANCY_2239_2208_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW34_MSB_MEMORY_REDUNDANCY_2239_2208_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000478) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000478) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000478) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_MEMORY_REDUNDANCY_2271_2240_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_LSB_MEMORY_REDUNDANCY_2271_2240_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000047c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000047c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000047c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_MEMORY_REDUNDANCY_2303_2272_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW35_MSB_MEMORY_REDUNDANCY_2303_2272_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000480) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000480) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000480) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_MEMORY_REDUNDANCY_2335_2304_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_LSB_MEMORY_REDUNDANCY_2335_2304_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000484) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000484) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000484) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_MEMORY_REDUNDANCY_2367_2336_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW36_MSB_MEMORY_REDUNDANCY_2367_2336_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000488) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000488) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000488) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_MEMORY_REDUNDANCY_2399_2368_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_LSB_MEMORY_REDUNDANCY_2399_2368_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000048c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000048c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000048c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_MEMORY_REDUNDANCY_2431_2400_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW37_MSB_MEMORY_REDUNDANCY_2431_2400_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000490) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000490) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000490) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_MEMORY_REDUNDANCY_2463_2432_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_LSB_MEMORY_REDUNDANCY_2463_2432_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000494) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000494) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000494) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_MEMORY_REDUNDANCY_2495_2464_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW38_MSB_MEMORY_REDUNDANCY_2495_2464_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000498) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000498) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000498) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_MEMORY_REDUNDANCY_2527_2496_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_LSB_MEMORY_REDUNDANCY_2527_2496_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000049c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000049c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000049c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_MEMORY_REDUNDANCY_2559_2528_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW39_MSB_MEMORY_REDUNDANCY_2559_2528_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004a0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004a0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004a0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_MEMORY_REDUNDANCY_2591_2560_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_LSB_MEMORY_REDUNDANCY_2591_2560_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004a4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004a4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004a4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_MEMORY_REDUNDANCY_2623_2592_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW40_MSB_MEMORY_REDUNDANCY_2623_2592_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004a8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004a8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004a8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_MEMORY_REDUNDANCY_2655_2624_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_LSB_MEMORY_REDUNDANCY_2655_2624_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004ac) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004ac) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004ac) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_MEMORY_REDUNDANCY_2687_2656_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW41_MSB_MEMORY_REDUNDANCY_2687_2656_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004b0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004b0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004b0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_MEMORY_REDUNDANCY_2719_2688_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_LSB_MEMORY_REDUNDANCY_2719_2688_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004b4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004b4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004b4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_MEMORY_REDUNDANCY_2751_2720_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW42_MSB_MEMORY_REDUNDANCY_2751_2720_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004b8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004b8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004b8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_MEMORY_REDUNDANCY_2783_2752_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_LSB_MEMORY_REDUNDANCY_2783_2752_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004bc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004bc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004bc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_MEMORY_REDUNDANCY_2815_2784_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW43_MSB_MEMORY_REDUNDANCY_2815_2784_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004c0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004c0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004c0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_MEMORY_REDUNDANCY_2847_2816_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_LSB_MEMORY_REDUNDANCY_2847_2816_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004c4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004c4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004c4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_MEMORY_REDUNDANCY_2879_2848_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW44_MSB_MEMORY_REDUNDANCY_2879_2848_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004c8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004c8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004c8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_MEMORY_REDUNDANCY_2911_2880_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_LSB_MEMORY_REDUNDANCY_2911_2880_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004cc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004cc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004cc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_MEMORY_REDUNDANCY_2943_2912_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW45_MSB_MEMORY_REDUNDANCY_2943_2912_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004d0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004d0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004d0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_MEMORY_REDUNDANCY_2975_2944_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_LSB_MEMORY_REDUNDANCY_2975_2944_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004d4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004d4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004d4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_MEMORY_REDUNDANCY_3007_2976_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW46_MSB_MEMORY_REDUNDANCY_3007_2976_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004d8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004d8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004d8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_MEMORY_REDUNDANCY_3039_3008_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_LSB_MEMORY_REDUNDANCY_3039_3008_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004dc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004dc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004dc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_MEMORY_REDUNDANCY_3071_3040_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW47_MSB_MEMORY_REDUNDANCY_3071_3040_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004e0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004e0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004e0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_MEMORY_REDUNDANCY_3103_3072_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_LSB_MEMORY_REDUNDANCY_3103_3072_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004e4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004e4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004e4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_MEMORY_REDUNDANCY_3135_3104_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW48_MSB_MEMORY_REDUNDANCY_3135_3104_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004e8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004e8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004e8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_MEMORY_REDUNDANCY_3167_3136_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_LSB_MEMORY_REDUNDANCY_3167_3136_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004ec) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004ec) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004ec) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_MEMORY_REDUNDANCY_3199_3168_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW49_MSB_MEMORY_REDUNDANCY_3199_3168_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004f0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004f0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004f0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_MEMORY_REDUNDANCY_3231_3200_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_LSB_MEMORY_REDUNDANCY_3231_3200_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004f4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004f4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004f4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_MEMORY_REDUNDANCY_3263_3232_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW50_MSB_MEMORY_REDUNDANCY_3263_3232_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004f8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004f8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004f8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_MEMORY_REDUNDANCY_3295_3264_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_LSB_MEMORY_REDUNDANCY_3295_3264_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000004fc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000004fc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000004fc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_MEMORY_REDUNDANCY_3327_3296_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW51_MSB_MEMORY_REDUNDANCY_3327_3296_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000500) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000500) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000500) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_MEMORY_REDUNDANCY_3359_3328_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_LSB_MEMORY_REDUNDANCY_3359_3328_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000504) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000504) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000504) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_MEMORY_REDUNDANCY_3391_3360_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW52_MSB_MEMORY_REDUNDANCY_3391_3360_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000508) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000508) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000508) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_MEMORY_REDUNDANCY_3423_3392_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_LSB_MEMORY_REDUNDANCY_3423_3392_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000050c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000050c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000050c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_MEMORY_REDUNDANCY_3455_3424_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW53_MSB_MEMORY_REDUNDANCY_3455_3424_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000510) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000510) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000510) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_MEMORY_REDUNDANCY_3487_3456_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_LSB_MEMORY_REDUNDANCY_3487_3456_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000514) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000514) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000514) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_MEMORY_REDUNDANCY_3519_3488_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW54_MSB_MEMORY_REDUNDANCY_3519_3488_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000518) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000518) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000518) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_MEMORY_REDUNDANCY_3551_3520_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_LSB_MEMORY_REDUNDANCY_3551_3520_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000051c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000051c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000051c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_MEMORY_REDUNDANCY_3583_3552_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW55_MSB_MEMORY_REDUNDANCY_3583_3552_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000520) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000520) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000520) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_MEMORY_REDUNDANCY_3615_3584_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_LSB_MEMORY_REDUNDANCY_3615_3584_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000524) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000524) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000524) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_MEMORY_REDUNDANCY_3647_3616_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW56_MSB_MEMORY_REDUNDANCY_3647_3616_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000528) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000528) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000528) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_MEMORY_REDUNDANCY_3679_3648_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_LSB_MEMORY_REDUNDANCY_3679_3648_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000052c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000052c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000052c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_MEMORY_REDUNDANCY_3711_3680_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW57_MSB_MEMORY_REDUNDANCY_3711_3680_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000530) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000530) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000530) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_MEMORY_REDUNDANCY_3743_3712_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_LSB_MEMORY_REDUNDANCY_3743_3712_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000534) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000534) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000534) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_MEMORY_REDUNDANCY_3775_3744_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW58_MSB_MEMORY_REDUNDANCY_3775_3744_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000538) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000538) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000538) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_MEMORY_REDUNDANCY_3807_3776_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_LSB_MEMORY_REDUNDANCY_3807_3776_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000053c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000053c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000053c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_MEMORY_REDUNDANCY_3839_3808_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW59_MSB_MEMORY_REDUNDANCY_3839_3808_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000540) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000540) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000540) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_MEMORY_REDUNDANCY_3871_3840_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_LSB_MEMORY_REDUNDANCY_3871_3840_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000544) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000544) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000544) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_MEMORY_REDUNDANCY_3903_3872_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW60_MSB_MEMORY_REDUNDANCY_3903_3872_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000548) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000548) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000548) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_MEMORY_REDUNDANCY_3935_3904_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_LSB_MEMORY_REDUNDANCY_3935_3904_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000054c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000054c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000054c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_MEMORY_REDUNDANCY_3967_3936_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW61_MSB_MEMORY_REDUNDANCY_3967_3936_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000550) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000550) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000550) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_MEMORY_REDUNDANCY_3999_3968_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_LSB_MEMORY_REDUNDANCY_3999_3968_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000554) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000554) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000554) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_MEMORY_REDUNDANCY_4031_4000_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW62_MSB_MEMORY_REDUNDANCY_4031_4000_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000558) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000558) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000558) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_MEMORY_REDUNDANCY_4063_4032_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_LSB_MEMORY_REDUNDANCY_4063_4032_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000055c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000055c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000055c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_MEMORY_REDUNDANCY_4095_4064_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW63_MSB_MEMORY_REDUNDANCY_4095_4064_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000560) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000560) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000560) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_MEMORY_REDUNDANCY_4127_4096_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_LSB_MEMORY_REDUNDANCY_4127_4096_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000564) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000564) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000564) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_MEMORY_REDUNDANCY_4159_4128_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW64_MSB_MEMORY_REDUNDANCY_4159_4128_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000568) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000568) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000568) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_MEMORY_REDUNDANCY_4191_4160_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_LSB_MEMORY_REDUNDANCY_4191_4160_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000056c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000056c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000056c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_MEMORY_REDUNDANCY_4223_4192_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW65_MSB_MEMORY_REDUNDANCY_4223_4192_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000570) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000570) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000570) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_MEMORY_REDUNDANCY_4255_4224_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_LSB_MEMORY_REDUNDANCY_4255_4224_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000574) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000574) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000574) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_MEMORY_REDUNDANCY_4287_4256_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW66_MSB_MEMORY_REDUNDANCY_4287_4256_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000578) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000578) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000578) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_MEMORY_REDUNDANCY_4319_4288_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_LSB_MEMORY_REDUNDANCY_4319_4288_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000057c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000057c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000057c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_MEMORY_REDUNDANCY_4351_4320_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW67_MSB_MEMORY_REDUNDANCY_4351_4320_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000580) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000580) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000580) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_MEMORY_REDUNDANCY_4383_4352_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_LSB_MEMORY_REDUNDANCY_4383_4352_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000584) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000584) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000584) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_MEMORY_REDUNDANCY_4415_4384_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW68_MSB_MEMORY_REDUNDANCY_4415_4384_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000588) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000588) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000588) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_MEMORY_REDUNDANCY_4447_4416_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_LSB_MEMORY_REDUNDANCY_4447_4416_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000058c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000058c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000058c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_MEMORY_REDUNDANCY_4479_4448_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW69_MSB_MEMORY_REDUNDANCY_4479_4448_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000590) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000590) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000590) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_MEMORY_REDUNDANCY_4511_4480_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_LSB_MEMORY_REDUNDANCY_4511_4480_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000594) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000594) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000594) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_MEMORY_REDUNDANCY_4543_4512_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW70_MSB_MEMORY_REDUNDANCY_4543_4512_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000598) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000598) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000598) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_MEMORY_REDUNDANCY_4575_4544_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_LSB_MEMORY_REDUNDANCY_4575_4544_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000059c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000059c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000059c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_MEMORY_REDUNDANCY_4607_4576_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW71_MSB_MEMORY_REDUNDANCY_4607_4576_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005a0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005a0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005a0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_MEMORY_REDUNDANCY_4639_4608_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_LSB_MEMORY_REDUNDANCY_4639_4608_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005a4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005a4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005a4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_MEMORY_REDUNDANCY_4671_4640_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW72_MSB_MEMORY_REDUNDANCY_4671_4640_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005a8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005a8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005a8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_MEMORY_REDUNDANCY_4703_4672_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_LSB_MEMORY_REDUNDANCY_4703_4672_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005ac) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005ac) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005ac) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_MEMORY_REDUNDANCY_4735_4704_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW73_MSB_MEMORY_REDUNDANCY_4735_4704_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005b0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005b0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005b0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_MEMORY_REDUNDANCY_4767_4736_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_LSB_MEMORY_REDUNDANCY_4767_4736_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005b4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005b4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005b4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_MEMORY_REDUNDANCY_4799_4768_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW74_MSB_MEMORY_REDUNDANCY_4799_4768_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005b8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005b8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005b8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_MEMORY_REDUNDANCY_4831_4800_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_LSB_MEMORY_REDUNDANCY_4831_4800_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005bc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005bc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005bc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_MEMORY_REDUNDANCY_4863_4832_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW75_MSB_MEMORY_REDUNDANCY_4863_4832_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005c0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005c0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005c0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_MEMORY_REDUNDANCY_4895_4864_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_LSB_MEMORY_REDUNDANCY_4895_4864_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005c4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005c4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005c4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_MEMORY_REDUNDANCY_4927_4896_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW76_MSB_MEMORY_REDUNDANCY_4927_4896_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005c8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005c8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005c8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_MEMORY_REDUNDANCY_4959_4928_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_LSB_MEMORY_REDUNDANCY_4959_4928_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005cc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005cc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005cc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_MEMORY_REDUNDANCY_4991_4960_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW77_MSB_MEMORY_REDUNDANCY_4991_4960_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005d0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005d0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005d0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_MEMORY_REDUNDANCY_5023_4992_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_LSB_MEMORY_REDUNDANCY_5023_4992_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005d4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005d4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005d4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_MEMORY_REDUNDANCY_5055_5024_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW78_MSB_MEMORY_REDUNDANCY_5055_5024_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005d8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005d8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005d8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_MEMORY_REDUNDANCY_5087_5056_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_LSB_MEMORY_REDUNDANCY_5087_5056_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005dc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005dc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005dc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_MEMORY_REDUNDANCY_5119_5088_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW79_MSB_MEMORY_REDUNDANCY_5119_5088_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005e0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005e0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005e0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_MEMORY_REDUNDANCY_5151_5120_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_LSB_MEMORY_REDUNDANCY_5151_5120_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005e4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005e4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005e4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_MEMORY_REDUNDANCY_5183_5152_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW80_MSB_MEMORY_REDUNDANCY_5183_5152_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005e8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005e8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005e8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_MEMORY_REDUNDANCY_5215_5184_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_LSB_MEMORY_REDUNDANCY_5215_5184_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005ec) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005ec) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005ec) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_MEMORY_REDUNDANCY_5247_5216_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW81_MSB_MEMORY_REDUNDANCY_5247_5216_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005f0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005f0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005f0) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_MEMORY_REDUNDANCY_5279_5248_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_LSB_MEMORY_REDUNDANCY_5279_5248_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005f4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005f4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005f4) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_MEMORY_REDUNDANCY_5311_5280_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW82_MSB_MEMORY_REDUNDANCY_5311_5280_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005f8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005f8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005f8) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_MEMORY_REDUNDANCY_5343_5312_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_LSB_MEMORY_REDUNDANCY_5343_5312_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000005fc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000005fc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000005fc) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_MEMORY_REDUNDANCY_5375_5344_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW83_MSB_MEMORY_REDUNDANCY_5375_5344_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000600) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000600) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000600) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_MEMORY_ACCELERATION_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_LSB_MEMORY_ACCELERATION_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000604) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000604) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000604) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_MEMORY_ACCELERATION_63_32_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW84_MSB_MEMORY_ACCELERATION_63_32_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000608) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000608) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000608) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_MEMORY_ACCELERATION_95_64_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_LSB_MEMORY_ACCELERATION_95_64_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000060c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000060c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000060c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_MEMORY_ACCELERATION_127_96_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW85_MSB_MEMORY_ACCELERATION_127_96_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000610) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000610) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000610) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_MEMORY_ACCELERATION_159_128_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_LSB_MEMORY_ACCELERATION_159_128_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000614) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000614) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000614) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_MEMORY_ACCELERATION_191_160_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW86_MSB_MEMORY_ACCELERATION_191_160_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000618) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000618) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000618) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_MEMORY_ACCELERATION_223_192_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_LSB_MEMORY_ACCELERATION_223_192_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000061c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000061c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000061c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_MEMORY_ACCELERATION_255_224_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW87_MSB_MEMORY_ACCELERATION_255_224_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000620) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000620) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000620) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_MEMORY_ACCELERATION_287_256_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_LSB_MEMORY_ACCELERATION_287_256_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000624) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000624) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000624) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_MEMORY_ACCELERATION_319_288_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW88_MSB_MEMORY_ACCELERATION_319_288_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000628) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000628) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000628) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_MEMORY_ACCELERATION_351_320_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_LSB_MEMORY_ACCELERATION_351_320_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000062c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000062c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000062c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_MEMORY_ACCELERATION_383_352_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW89_MSB_MEMORY_ACCELERATION_383_352_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000630) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000630) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000630) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_MEMORY_ACCELERATION_415_384_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_LSB_MEMORY_ACCELERATION_415_384_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000634) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000634) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000634) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_MEMORY_ACCELERATION_447_416_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW90_MSB_MEMORY_ACCELERATION_447_416_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000638) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000638) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000638) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_MEMORY_ACCELERATION_479_448_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_LSB_MEMORY_ACCELERATION_479_448_SHFT 0x0 #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000063c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000063c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000063c) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_IN \ in_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_ADDR) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_ADDR, m) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_ADDR,v) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_ADDR,m,v,HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_IN) #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_MEMORY_ACCELERATION_511_480_BMSK 0xffffffff #define HWIO_QFPROM_RAW_MEMORY_CONFIGURATION_ROW91_MSB_MEMORY_ACCELERATION_511_480_SHFT 0x0 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000640) #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000640) #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000640) #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_IN \ in_dword(HWIO_QFPROM_RAW_QC_SPARE_20_LSB_ADDR) #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_20_LSB_ADDR, m) #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_QC_SPARE_20_LSB_ADDR,v) #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_20_LSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_20_LSB_IN) #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_RSVD_BMSK 0xfffc0000 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_RSVD_SHFT 0x12 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_RET_FT_BMSK 0x20000 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_RET_FT_SHFT 0x11 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_RET_WS_BMSK 0x10000 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_RET_WS_SHFT 0x10 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_IDDQ_FT_BMSK 0x8000 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_IDDQ_FT_SHFT 0xf #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_IDDQ_WS_BMSK 0x4000 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_IDDQ_WS_SHFT 0xe #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_PONGO_FT_BMSK 0x2000 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_PONGO_FT_SHFT 0xd #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_PONGO_WS_BMSK 0x1000 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_PONGO_WS_SHFT 0xc #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_Q6_FT_BMSK 0x800 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_Q6_FT_SHFT 0xb #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_Q6_WS_BMSK 0x400 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_Q6_WS_SHFT 0xa #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_TSENS_FT_BMSK 0x200 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_TSENS_FT_SHFT 0x9 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_TSENS_WS_BMSK 0x100 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_TSENS_WS_SHFT 0x8 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_MSIP_FT_BMSK 0x80 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_MSIP_FT_SHFT 0x7 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_MSIP_WS_BMSK 0x40 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_MSIP_WS_SHFT 0x6 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_HSIO_FT_BMSK 0x20 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_HSIO_FT_SHFT 0x5 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_HSIO_WS_BMSK 0x10 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_HSIO_WS_SHFT 0x4 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_CPR_FT_BMSK 0x8 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_CPR_FT_SHFT 0x3 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_CPR_WS_BMSK 0x4 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_CPR_WS_SHFT 0x2 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_QFPROM_FT_BMSK 0x2 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_QFPROM_FT_SHFT 0x1 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_QFPROM_WS_BMSK 0x1 #define HWIO_QFPROM_RAW_QC_SPARE_20_LSB_QFPROM_WS_SHFT 0x0 #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000644) #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000644) #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000644) #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_IN \ in_dword(HWIO_QFPROM_RAW_QC_SPARE_20_MSB_ADDR) #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_20_MSB_ADDR, m) #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_QC_SPARE_20_MSB_ADDR,v) #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_20_MSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_20_MSB_IN) #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_RSVD_BMSK 0xffffff #define HWIO_QFPROM_RAW_QC_SPARE_20_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_QC_SPARE_21_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000648) #define HWIO_QFPROM_RAW_QC_SPARE_21_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000648) #define HWIO_QFPROM_RAW_QC_SPARE_21_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000648) #define HWIO_QFPROM_RAW_QC_SPARE_21_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_QC_SPARE_21_LSB_IN \ in_dword(HWIO_QFPROM_RAW_QC_SPARE_21_LSB_ADDR) #define HWIO_QFPROM_RAW_QC_SPARE_21_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_21_LSB_ADDR, m) #define HWIO_QFPROM_RAW_QC_SPARE_21_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_QC_SPARE_21_LSB_ADDR,v) #define HWIO_QFPROM_RAW_QC_SPARE_21_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_21_LSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_21_LSB_IN) #define HWIO_QFPROM_RAW_QC_SPARE_21_LSB_GPU_ISENS_CAL_BMSK 0xffffffff #define HWIO_QFPROM_RAW_QC_SPARE_21_LSB_GPU_ISENS_CAL_SHFT 0x0 #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000064c) #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000064c) #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000064c) #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_IN \ in_dword(HWIO_QFPROM_RAW_QC_SPARE_21_MSB_ADDR) #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_QC_SPARE_21_MSB_ADDR, m) #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_QC_SPARE_21_MSB_ADDR,v) #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_QC_SPARE_21_MSB_ADDR,m,v,HWIO_QFPROM_RAW_QC_SPARE_21_MSB_IN) #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_RSVD_BMSK 0xffffff #define HWIO_QFPROM_RAW_QC_SPARE_21_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000650) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000650) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000650) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_OEM_IMAGE_ENCRYPTION_KEY_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_OEM_IMAGE_ENCRYPTION_KEY_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000654) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000654) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000654) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_OEM_IMAGE_ENCRYPTION_KEY_55_32_BMSK 0xffffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_OEM_IMAGE_ENCRYPTION_KEY_55_32_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000658) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000658) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000658) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_OEM_IMAGE_ENCRYPTION_KEY_87_56_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_OEM_IMAGE_ENCRYPTION_KEY_87_56_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000065c) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000065c) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000065c) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_OEM_IMAGE_ENCRYPTION_KEY_111_88_BMSK 0xffffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_OEM_IMAGE_ENCRYPTION_KEY_111_88_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000660) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000660) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000660) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_SPARE_188_16_15_0_BMSK 0xffff0000 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_SPARE_188_16_15_0_SHFT 0x10 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_OEM_IMAGE_ENCRYPTION_KEY_BMSK 0xffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_OEM_IMAGE_ENCRYPTION_KEY_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000664) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000664) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000664) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_SPARE_188_16_39_16_BMSK 0xffffff #define HWIO_QFPROM_RAW_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_SPARE_188_16_39_16_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000668) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000668) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000668) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_RESERVED_BMSK 0x80000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_RESERVED_SHFT 0x1f #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_USE_SERIAL_NUM_BMSK 0x40000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_USE_SERIAL_NUM_SHFT 0x1e #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_AUTH_EN_BMSK 0x20000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_AUTH_EN_SHFT 0x1d #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_PK_HASH_IN_FUSE_BMSK 0x10000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_PK_HASH_IN_FUSE_SHFT 0x1c #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX3_BMSK 0x8000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX3_SHFT 0x1b #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX2_BMSK 0x4000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX2_SHFT 0x1a #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX1_BMSK 0x2000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX1_SHFT 0x19 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX0_BMSK 0x1000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX0_SHFT 0x18 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_RESERVED_BMSK 0x800000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_RESERVED_SHFT 0x17 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_USE_SERIAL_NUM_BMSK 0x400000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_USE_SERIAL_NUM_SHFT 0x16 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_AUTH_EN_BMSK 0x200000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_AUTH_EN_SHFT 0x15 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_PK_HASH_IN_FUSE_BMSK 0x100000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_PK_HASH_IN_FUSE_SHFT 0x14 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX3_BMSK 0x80000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX3_SHFT 0x13 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX2_BMSK 0x40000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX2_SHFT 0x12 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX1_BMSK 0x20000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX1_SHFT 0x11 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX0_BMSK 0x10000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX0_SHFT 0x10 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_RESERVED_BMSK 0x8000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_RESERVED_SHFT 0xf #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_USE_SERIAL_NUM_BMSK 0x4000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_USE_SERIAL_NUM_SHFT 0xe #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_AUTH_EN_BMSK 0x2000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_AUTH_EN_SHFT 0xd #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_PK_HASH_IN_FUSE_BMSK 0x1000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_PK_HASH_IN_FUSE_SHFT 0xc #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX3_BMSK 0x800 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX3_SHFT 0xb #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX2_BMSK 0x400 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX2_SHFT 0xa #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX1_BMSK 0x200 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX1_SHFT 0x9 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX0_BMSK 0x100 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX0_SHFT 0x8 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_RESERVED_BMSK 0x80 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_RESERVED_SHFT 0x7 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_USE_SERIAL_NUM_BMSK 0x40 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_USE_SERIAL_NUM_SHFT 0x6 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_AUTH_EN_BMSK 0x20 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_AUTH_EN_SHFT 0x5 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_PK_HASH_IN_FUSE_BMSK 0x10 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_PK_HASH_IN_FUSE_SHFT 0x4 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX3_BMSK 0x8 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX3_SHFT 0x3 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX2_BMSK 0x4 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX2_SHFT 0x2 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX1_BMSK 0x2 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX1_SHFT 0x1 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX0_BMSK 0x1 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX0_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000066c) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000066c) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000066c) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_RESERVED_BMSK 0x800000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_RESERVED_SHFT 0x17 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_USE_SERIAL_NUM_BMSK 0x400000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_USE_SERIAL_NUM_SHFT 0x16 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_AUTH_EN_BMSK 0x200000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_AUTH_EN_SHFT 0x15 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_PK_HASH_IN_FUSE_BMSK 0x100000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_PK_HASH_IN_FUSE_SHFT 0x14 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX3_BMSK 0x80000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX3_SHFT 0x13 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX2_BMSK 0x40000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX2_SHFT 0x12 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX1_BMSK 0x20000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX1_SHFT 0x11 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX0_BMSK 0x10000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX0_SHFT 0x10 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_RESERVED_BMSK 0x8000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_RESERVED_SHFT 0xf #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_USE_SERIAL_NUM_BMSK 0x4000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_USE_SERIAL_NUM_SHFT 0xe #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_AUTH_EN_BMSK 0x2000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_AUTH_EN_SHFT 0xd #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_PK_HASH_IN_FUSE_BMSK 0x1000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_PK_HASH_IN_FUSE_SHFT 0xc #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX3_BMSK 0x800 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX3_SHFT 0xb #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX2_BMSK 0x400 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX2_SHFT 0xa #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX1_BMSK 0x200 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX1_SHFT 0x9 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX0_BMSK 0x100 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX0_SHFT 0x8 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_RESERVED_BMSK 0x80 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_RESERVED_SHFT 0x7 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_USE_SERIAL_NUM_BMSK 0x40 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_USE_SERIAL_NUM_SHFT 0x6 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_AUTH_EN_BMSK 0x20 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_AUTH_EN_SHFT 0x5 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_PK_HASH_IN_FUSE_BMSK 0x10 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_PK_HASH_IN_FUSE_SHFT 0x4 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX3_BMSK 0x8 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX3_SHFT 0x3 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX2_BMSK 0x4 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX2_SHFT 0x2 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX1_BMSK 0x2 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX1_SHFT 0x1 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX0_BMSK 0x1 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX0_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000670) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000670) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000670) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_RESERVED_BMSK 0x80000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_RESERVED_SHFT 0x1f #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_USE_SERIAL_NUM_BMSK 0x40000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_USE_SERIAL_NUM_SHFT 0x1e #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_AUTH_EN_BMSK 0x20000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_AUTH_EN_SHFT 0x1d #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_PK_HASH_IN_FUSE_BMSK 0x10000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_PK_HASH_IN_FUSE_SHFT 0x1c #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX3_BMSK 0x8000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX3_SHFT 0x1b #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX2_BMSK 0x4000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX2_SHFT 0x1a #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX1_BMSK 0x2000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX1_SHFT 0x19 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX0_BMSK 0x1000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX0_SHFT 0x18 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_RESERVED_BMSK 0x800000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_RESERVED_SHFT 0x17 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_USE_SERIAL_NUM_BMSK 0x400000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_USE_SERIAL_NUM_SHFT 0x16 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_AUTH_EN_BMSK 0x200000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_AUTH_EN_SHFT 0x15 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_PK_HASH_IN_FUSE_BMSK 0x100000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_PK_HASH_IN_FUSE_SHFT 0x14 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX3_BMSK 0x80000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX3_SHFT 0x13 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX2_BMSK 0x40000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX2_SHFT 0x12 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX1_BMSK 0x20000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX1_SHFT 0x11 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX0_BMSK 0x10000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX0_SHFT 0x10 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_RESERVED_BMSK 0x8000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_RESERVED_SHFT 0xf #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_USE_SERIAL_NUM_BMSK 0x4000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_USE_SERIAL_NUM_SHFT 0xe #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_AUTH_EN_BMSK 0x2000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_AUTH_EN_SHFT 0xd #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_PK_HASH_IN_FUSE_BMSK 0x1000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_PK_HASH_IN_FUSE_SHFT 0xc #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX3_BMSK 0x800 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX3_SHFT 0xb #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX2_BMSK 0x400 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX2_SHFT 0xa #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX1_BMSK 0x200 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX1_SHFT 0x9 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX0_BMSK 0x100 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX0_SHFT 0x8 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_RESERVED_BMSK 0x80 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_RESERVED_SHFT 0x7 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_USE_SERIAL_NUM_BMSK 0x40 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_USE_SERIAL_NUM_SHFT 0x6 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_AUTH_EN_BMSK 0x20 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_AUTH_EN_SHFT 0x5 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_PK_HASH_IN_FUSE_BMSK 0x10 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_PK_HASH_IN_FUSE_SHFT 0x4 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX3_BMSK 0x8 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX3_SHFT 0x3 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX2_BMSK 0x4 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX2_SHFT 0x2 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX1_BMSK 0x2 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX1_SHFT 0x1 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX0_BMSK 0x1 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX0_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000674) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000674) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000674) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_RESERVED_BMSK 0x800000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_RESERVED_SHFT 0x17 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_USE_SERIAL_NUM_BMSK 0x400000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_USE_SERIAL_NUM_SHFT 0x16 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_AUTH_EN_BMSK 0x200000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_AUTH_EN_SHFT 0x15 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_PK_HASH_IN_FUSE_BMSK 0x100000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_PK_HASH_IN_FUSE_SHFT 0x14 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX3_BMSK 0x80000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX3_SHFT 0x13 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX2_BMSK 0x40000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX2_SHFT 0x12 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX1_BMSK 0x20000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX1_SHFT 0x11 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX0_BMSK 0x10000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX0_SHFT 0x10 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_RESERVED_BMSK 0x8000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_RESERVED_SHFT 0xf #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_USE_SERIAL_NUM_BMSK 0x4000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_USE_SERIAL_NUM_SHFT 0xe #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_AUTH_EN_BMSK 0x2000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_AUTH_EN_SHFT 0xd #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_PK_HASH_IN_FUSE_BMSK 0x1000 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_PK_HASH_IN_FUSE_SHFT 0xc #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX3_BMSK 0x800 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX3_SHFT 0xb #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX2_BMSK 0x400 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX2_SHFT 0xa #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX1_BMSK 0x200 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX1_SHFT 0x9 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX0_BMSK 0x100 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX0_SHFT 0x8 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_RESERVED_BMSK 0x80 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_RESERVED_SHFT 0x7 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_USE_SERIAL_NUM_BMSK 0x40 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_USE_SERIAL_NUM_SHFT 0x6 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_AUTH_EN_BMSK 0x20 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_AUTH_EN_SHFT 0x5 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_PK_HASH_IN_FUSE_BMSK 0x10 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_PK_HASH_IN_FUSE_SHFT 0x4 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX3_BMSK 0x8 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX3_SHFT 0x3 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX2_BMSK 0x4 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX2_SHFT 0x2 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX1_BMSK 0x2 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX1_SHFT 0x1 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX0_BMSK 0x1 #define HWIO_QFPROM_RAW_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX0_SHFT 0x0 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000678) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000678) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000678) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_SEC_KEY_DERIVATION_KEY_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_LSB_SEC_KEY_DERIVATION_KEY_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000067c) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000067c) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000067c) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_SEC_KEY_DERIVATION_KEY_55_32_BMSK 0xffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW0_MSB_SEC_KEY_DERIVATION_KEY_55_32_SHFT 0x0 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000680) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000680) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000680) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_SEC_KEY_DERIVATION_KEY_87_56_BMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_LSB_SEC_KEY_DERIVATION_KEY_87_56_SHFT 0x0 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000684) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000684) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000684) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_SEC_KEY_DERIVATION_KEY_111_88_BMSK 0xffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW1_MSB_SEC_KEY_DERIVATION_KEY_111_88_SHFT 0x0 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000688) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000688) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000688) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_SEC_KEY_DERIVATION_KEY_143_112_BMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_LSB_SEC_KEY_DERIVATION_KEY_143_112_SHFT 0x0 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000068c) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000068c) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000068c) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_SEC_KEY_DERIVATION_KEY_167_144_BMSK 0xffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW2_MSB_SEC_KEY_DERIVATION_KEY_167_144_SHFT 0x0 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000690) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000690) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000690) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_ADDR) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_IN) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_SEC_KEY_DERIVATION_KEY_199_168_BMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_LSB_SEC_KEY_DERIVATION_KEY_199_168_SHFT 0x0 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000694) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000694) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000694) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_ADDR) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_IN) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_SEC_KEY_DERIVATION_KEY_223_200_BMSK 0xffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW3_MSB_SEC_KEY_DERIVATION_KEY_223_200_SHFT 0x0 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000698) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000698) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000698) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,v) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_SEC_KEY_DERIVATION_KEY_BMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_LSB_SEC_KEY_DERIVATION_KEY_SHFT 0x0 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000069c) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000069c) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000069c) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,v) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN) #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_55_BMSK 0x800000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_55_SHFT 0x17 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_54_BMSK 0x400000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_54_SHFT 0x16 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_53_BMSK 0x200000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_53_SHFT 0x15 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_52_BMSK 0x100000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_52_SHFT 0x14 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_51_BMSK 0x80000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_51_SHFT 0x13 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_50_BMSK 0x40000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_50_SHFT 0x12 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_49_BMSK 0x20000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_49_SHFT 0x11 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_48_BMSK 0x10000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_48_SHFT 0x10 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_47_BMSK 0x8000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_47_SHFT 0xf #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_46_BMSK 0x4000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_46_SHFT 0xe #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_45_BMSK 0x2000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_45_SHFT 0xd #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_44_BMSK 0x1000 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_44_SHFT 0xc #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_43_BMSK 0x800 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_43_SHFT 0xb #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_42_BMSK 0x400 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_42_SHFT 0xa #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_41_BMSK 0x200 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_41_SHFT 0x9 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_40_BMSK 0x100 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_40_SHFT 0x8 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_39_BMSK 0x80 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_39_SHFT 0x7 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_38_BMSK 0x40 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_38_SHFT 0x6 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_37_BMSK 0x20 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_37_SHFT 0x5 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_36_BMSK 0x10 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_36_SHFT 0x4 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_35_BMSK 0x8 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_35_SHFT 0x3 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_34_BMSK 0x4 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_34_SHFT 0x2 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_33_BMSK 0x2 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_33_SHFT 0x1 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_32_BMSK 0x1 #define HWIO_QFPROM_RAW_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_32_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006a0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006a0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006a0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_BOOT_PATCH_0_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_LSB_BOOT_PATCH_0_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006a4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006a4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006a4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_BOOT_PATCH_0_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_BOOT_PATCH_0_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_BOOT_PATCH_0_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW0_MSB_BOOT_PATCH_0_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006a8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006a8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006a8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_BOOT_PATCH_1_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_LSB_BOOT_PATCH_1_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006ac) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006ac) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006ac) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_BOOT_PATCH_1_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_BOOT_PATCH_1_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_BOOT_PATCH_1_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW1_MSB_BOOT_PATCH_1_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006b0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006b0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006b0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_BOOT_PATCH_2_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_LSB_BOOT_PATCH_2_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006b4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006b4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006b4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_BOOT_PATCH_2_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_BOOT_PATCH_2_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_BOOT_PATCH_2_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW2_MSB_BOOT_PATCH_2_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006b8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006b8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006b8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_BOOT_PATCH_3_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_LSB_BOOT_PATCH_3_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006bc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006bc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006bc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_BOOT_PATCH_3_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_BOOT_PATCH_3_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_BOOT_PATCH_3_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW3_MSB_BOOT_PATCH_3_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006c0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006c0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006c0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_BOOT_PATCH_4_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_LSB_BOOT_PATCH_4_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006c4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006c4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006c4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_BOOT_PATCH_4_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_BOOT_PATCH_4_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_BOOT_PATCH_4_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW4_MSB_BOOT_PATCH_4_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006c8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006c8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006c8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_BOOT_PATCH_5_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_LSB_BOOT_PATCH_5_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006cc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006cc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006cc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_BOOT_PATCH_5_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_BOOT_PATCH_5_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_BOOT_PATCH_5_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW5_MSB_BOOT_PATCH_5_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006d0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006d0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006d0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_BOOT_PATCH_6_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_LSB_BOOT_PATCH_6_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006d4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006d4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006d4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_BOOT_PATCH_6_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_BOOT_PATCH_6_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_BOOT_PATCH_6_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW6_MSB_BOOT_PATCH_6_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006d8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006d8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006d8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_BOOT_PATCH_7_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_LSB_BOOT_PATCH_7_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006dc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006dc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006dc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_BOOT_PATCH_7_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_BOOT_PATCH_7_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_BOOT_PATCH_7_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW7_MSB_BOOT_PATCH_7_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006e0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006e0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006e0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_BOOT_PATCH_8_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_LSB_BOOT_PATCH_8_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006e4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006e4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006e4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_BOOT_PATCH_8_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_BOOT_PATCH_8_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_BOOT_PATCH_8_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW8_MSB_BOOT_PATCH_8_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006e8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006e8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006e8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_BOOT_PATCH_9_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_LSB_BOOT_PATCH_9_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006ec) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006ec) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006ec) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_BOOT_PATCH_9_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_BOOT_PATCH_9_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_BOOT_PATCH_9_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW9_MSB_BOOT_PATCH_9_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006f0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006f0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006f0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_BOOT_PATCH_10_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_LSB_BOOT_PATCH_10_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006f4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006f4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006f4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_BOOT_PATCH_10_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_BOOT_PATCH_10_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_BOOT_PATCH_10_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW10_MSB_BOOT_PATCH_10_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006f8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006f8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006f8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_BOOT_PATCH_11_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_LSB_BOOT_PATCH_11_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000006fc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000006fc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000006fc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_BOOT_PATCH_11_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_BOOT_PATCH_11_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_BOOT_PATCH_11_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW11_MSB_BOOT_PATCH_11_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000700) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000700) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000700) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_BOOT_PATCH_12_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_LSB_BOOT_PATCH_12_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000704) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000704) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000704) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_BOOT_PATCH_12_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_BOOT_PATCH_12_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_BOOT_PATCH_12_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW12_MSB_BOOT_PATCH_12_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000708) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000708) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000708) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_BOOT_PATCH_13_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_LSB_BOOT_PATCH_13_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000070c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000070c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000070c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_BOOT_PATCH_13_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_BOOT_PATCH_13_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_BOOT_PATCH_13_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW13_MSB_BOOT_PATCH_13_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000710) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000710) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000710) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_BOOT_PATCH_14_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_LSB_BOOT_PATCH_14_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000714) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000714) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000714) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_BOOT_PATCH_14_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_BOOT_PATCH_14_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_BOOT_PATCH_14_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW14_MSB_BOOT_PATCH_14_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000718) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000718) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000718) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_BOOT_PATCH_15_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_LSB_BOOT_PATCH_15_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000071c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000071c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000071c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_BOOT_PATCH_15_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_BOOT_PATCH_15_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_BOOT_PATCH_15_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW15_MSB_BOOT_PATCH_15_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000720) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000720) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000720) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_BOOT_PATCH_16_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_LSB_BOOT_PATCH_16_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000724) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000724) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000724) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_BOOT_PATCH_16_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_BOOT_PATCH_16_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_BOOT_PATCH_16_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW16_MSB_BOOT_PATCH_16_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000728) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000728) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000728) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_BOOT_PATCH_17_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_LSB_BOOT_PATCH_17_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000072c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000072c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000072c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_BOOT_PATCH_17_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_BOOT_PATCH_17_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_BOOT_PATCH_17_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW17_MSB_BOOT_PATCH_17_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000730) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000730) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000730) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_BOOT_PATCH_18_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_LSB_BOOT_PATCH_18_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000734) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000734) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000734) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_BOOT_PATCH_18_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_BOOT_PATCH_18_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_BOOT_PATCH_18_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW18_MSB_BOOT_PATCH_18_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000738) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000738) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000738) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_BOOT_PATCH_19_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_LSB_BOOT_PATCH_19_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000073c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000073c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000073c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_BOOT_PATCH_19_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_BOOT_PATCH_19_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_BOOT_PATCH_19_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW19_MSB_BOOT_PATCH_19_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000740) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000740) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000740) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_BOOT_PATCH_20_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_LSB_BOOT_PATCH_20_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000744) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000744) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000744) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_BOOT_PATCH_20_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_BOOT_PATCH_20_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_BOOT_PATCH_20_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW20_MSB_BOOT_PATCH_20_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000748) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000748) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000748) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_BOOT_PATCH_21_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_LSB_BOOT_PATCH_21_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000074c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000074c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000074c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_BOOT_PATCH_21_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_BOOT_PATCH_21_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_BOOT_PATCH_21_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW21_MSB_BOOT_PATCH_21_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000750) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000750) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000750) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_BOOT_PATCH_22_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_LSB_BOOT_PATCH_22_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000754) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000754) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000754) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_BOOT_PATCH_22_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_BOOT_PATCH_22_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_BOOT_PATCH_22_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW22_MSB_BOOT_PATCH_22_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000758) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000758) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000758) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_BOOT_PATCH_23_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_LSB_BOOT_PATCH_23_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000075c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000075c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000075c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_BOOT_PATCH_23_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_BOOT_PATCH_23_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_BOOT_PATCH_23_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW23_MSB_BOOT_PATCH_23_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000760) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000760) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000760) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_BOOT_PATCH_24_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_LSB_BOOT_PATCH_24_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000764) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000764) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000764) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_BOOT_PATCH_24_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_BOOT_PATCH_24_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_BOOT_PATCH_24_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW24_MSB_BOOT_PATCH_24_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000768) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000768) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000768) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_BOOT_PATCH_25_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_LSB_BOOT_PATCH_25_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000076c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000076c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000076c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_BOOT_PATCH_25_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_BOOT_PATCH_25_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_BOOT_PATCH_25_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW25_MSB_BOOT_PATCH_25_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000770) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000770) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000770) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_BOOT_PATCH_26_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_LSB_BOOT_PATCH_26_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000774) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000774) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000774) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_BOOT_PATCH_26_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_BOOT_PATCH_26_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_BOOT_PATCH_26_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW26_MSB_BOOT_PATCH_26_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000778) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000778) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000778) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_BOOT_PATCH_27_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_LSB_BOOT_PATCH_27_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000077c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000077c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000077c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_BOOT_PATCH_27_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_BOOT_PATCH_27_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_BOOT_PATCH_27_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW27_MSB_BOOT_PATCH_27_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000780) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000780) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000780) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_BOOT_PATCH_28_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_LSB_BOOT_PATCH_28_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000784) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000784) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000784) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_BOOT_PATCH_28_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_BOOT_PATCH_28_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_BOOT_PATCH_28_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW28_MSB_BOOT_PATCH_28_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000788) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000788) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000788) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_BOOT_PATCH_29_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_LSB_BOOT_PATCH_29_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000078c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000078c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000078c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_BOOT_PATCH_29_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_BOOT_PATCH_29_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_BOOT_PATCH_29_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW29_MSB_BOOT_PATCH_29_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000790) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000790) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000790) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_BOOT_PATCH_30_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_LSB_BOOT_PATCH_30_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000794) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000794) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000794) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_BOOT_PATCH_30_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_BOOT_PATCH_30_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_BOOT_PATCH_30_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW30_MSB_BOOT_PATCH_30_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000798) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000798) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000798) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_BOOT_PATCH_31_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_LSB_BOOT_PATCH_31_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000079c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000079c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000079c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_BOOT_PATCH_31_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_BOOT_PATCH_31_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_BOOT_PATCH_31_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW31_MSB_BOOT_PATCH_31_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007a0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007a0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007a0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_BOOT_PATCH_32_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_LSB_BOOT_PATCH_32_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007a4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007a4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007a4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_BOOT_PATCH_32_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_BOOT_PATCH_32_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_BOOT_PATCH_32_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW32_MSB_BOOT_PATCH_32_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007a8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007a8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007a8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_BOOT_PATCH_33_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_LSB_BOOT_PATCH_33_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007ac) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007ac) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007ac) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_BOOT_PATCH_33_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_BOOT_PATCH_33_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_BOOT_PATCH_33_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW33_MSB_BOOT_PATCH_33_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007b0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007b0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007b0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_BOOT_PATCH_34_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_LSB_BOOT_PATCH_34_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007b4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007b4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007b4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_BOOT_PATCH_34_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_BOOT_PATCH_34_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_BOOT_PATCH_34_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW34_MSB_BOOT_PATCH_34_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007b8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007b8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007b8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_BOOT_PATCH_35_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_LSB_BOOT_PATCH_35_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007bc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007bc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007bc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_BOOT_PATCH_35_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_BOOT_PATCH_35_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_BOOT_PATCH_35_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW35_MSB_BOOT_PATCH_35_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007c0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007c0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007c0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_BOOT_PATCH_36_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_LSB_BOOT_PATCH_36_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007c4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007c4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007c4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_BOOT_PATCH_36_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_BOOT_PATCH_36_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_BOOT_PATCH_36_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW36_MSB_BOOT_PATCH_36_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007c8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007c8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007c8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_BOOT_PATCH_37_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_LSB_BOOT_PATCH_37_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007cc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007cc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007cc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_BOOT_PATCH_37_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_BOOT_PATCH_37_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_BOOT_PATCH_37_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW37_MSB_BOOT_PATCH_37_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007d0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007d0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007d0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_BOOT_PATCH_38_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_LSB_BOOT_PATCH_38_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007d4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007d4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007d4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_BOOT_PATCH_38_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_BOOT_PATCH_38_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_BOOT_PATCH_38_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW38_MSB_BOOT_PATCH_38_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007d8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007d8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007d8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_BOOT_PATCH_39_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_LSB_BOOT_PATCH_39_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007dc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007dc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007dc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_BOOT_PATCH_39_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_BOOT_PATCH_39_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_BOOT_PATCH_39_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW39_MSB_BOOT_PATCH_39_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007e0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007e0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007e0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_BOOT_PATCH_40_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_LSB_BOOT_PATCH_40_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007e4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007e4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007e4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_BOOT_PATCH_40_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_BOOT_PATCH_40_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_BOOT_PATCH_40_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW40_MSB_BOOT_PATCH_40_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007e8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007e8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007e8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_BOOT_PATCH_41_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_LSB_BOOT_PATCH_41_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007ec) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007ec) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007ec) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_BOOT_PATCH_41_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_BOOT_PATCH_41_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_BOOT_PATCH_41_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW41_MSB_BOOT_PATCH_41_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007f0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007f0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007f0) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_BOOT_PATCH_42_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_LSB_BOOT_PATCH_42_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007f4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007f4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007f4) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_BOOT_PATCH_42_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_BOOT_PATCH_42_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_BOOT_PATCH_42_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW42_MSB_BOOT_PATCH_42_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007f8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007f8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007f8) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_BOOT_PATCH_43_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_LSB_BOOT_PATCH_43_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000007fc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000007fc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000007fc) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_BOOT_PATCH_43_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_BOOT_PATCH_43_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_BOOT_PATCH_43_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW43_MSB_BOOT_PATCH_43_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000800) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000800) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000800) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_BOOT_PATCH_44_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_LSB_BOOT_PATCH_44_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000804) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000804) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000804) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_BOOT_PATCH_44_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_BOOT_PATCH_44_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_BOOT_PATCH_44_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW44_MSB_BOOT_PATCH_44_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000808) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000808) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000808) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_BOOT_PATCH_45_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_LSB_BOOT_PATCH_45_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000080c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000080c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000080c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_BOOT_PATCH_45_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_BOOT_PATCH_45_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_BOOT_PATCH_45_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW45_MSB_BOOT_PATCH_45_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000810) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000810) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000810) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_BOOT_PATCH_46_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_LSB_BOOT_PATCH_46_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000814) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000814) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000814) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_BOOT_PATCH_46_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_BOOT_PATCH_46_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_BOOT_PATCH_46_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW46_MSB_BOOT_PATCH_46_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000818) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000818) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000818) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_BOOT_PATCH_47_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_LSB_BOOT_PATCH_47_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000081c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000081c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000081c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_BOOT_PATCH_47_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_BOOT_PATCH_47_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_BOOT_PATCH_47_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW47_MSB_BOOT_PATCH_47_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000820) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000820) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000820) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_BOOT_PATCH_48_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_LSB_BOOT_PATCH_48_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000824) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000824) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000824) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_BOOT_PATCH_48_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_BOOT_PATCH_48_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_BOOT_PATCH_48_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW48_MSB_BOOT_PATCH_48_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000828) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000828) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000828) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_BOOT_PATCH_49_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_LSB_BOOT_PATCH_49_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000082c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000082c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000082c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_BOOT_PATCH_49_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_BOOT_PATCH_49_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_BOOT_PATCH_49_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW49_MSB_BOOT_PATCH_49_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000830) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000830) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000830) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_BOOT_PATCH_50_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_LSB_BOOT_PATCH_50_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000834) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000834) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000834) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_BOOT_PATCH_50_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_BOOT_PATCH_50_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_BOOT_PATCH_50_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW50_MSB_BOOT_PATCH_50_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000838) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000838) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000838) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_BOOT_PATCH_51_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_LSB_BOOT_PATCH_51_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000083c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000083c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000083c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_BOOT_PATCH_51_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_BOOT_PATCH_51_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_BOOT_PATCH_51_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW51_MSB_BOOT_PATCH_51_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000840) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000840) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000840) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_BOOT_PATCH_52_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_LSB_BOOT_PATCH_52_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000844) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000844) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000844) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_BOOT_PATCH_52_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_BOOT_PATCH_52_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_BOOT_PATCH_52_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW52_MSB_BOOT_PATCH_52_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000848) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000848) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000848) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_BOOT_PATCH_53_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_LSB_BOOT_PATCH_53_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000084c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000084c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000084c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_BOOT_PATCH_53_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_BOOT_PATCH_53_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_BOOT_PATCH_53_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW53_MSB_BOOT_PATCH_53_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000850) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000850) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000850) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_BOOT_PATCH_54_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_LSB_BOOT_PATCH_54_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000854) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000854) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000854) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_BOOT_PATCH_54_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_BOOT_PATCH_54_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_BOOT_PATCH_54_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW54_MSB_BOOT_PATCH_54_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000858) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000858) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000858) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_BOOT_PATCH_55_DATA_BMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_LSB_BOOT_PATCH_55_DATA_SHFT 0x0 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000085c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000085c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000085c) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_IN \ in_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_ADDR) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_ADDR, m) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_ADDR,v) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_ADDR,m,v,HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_IN) #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_RSVD1_BMSK 0x80000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_RSVD1_SHFT 0x1f #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_BOOT_PATCH_55_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_BOOT_PATCH_55_ADDR_SHFT 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_BOOT_PATCH_55_ENABLE_BMSK 0x1 #define HWIO_QFPROM_RAW_BOOT_ROM_PATCH_ROW55_MSB_BOOT_PATCH_55_ENABLE_SHFT 0x0 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000860) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000860) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000860) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_IMAGE_ENCRYPTION_KEY_1_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_IMAGE_ENCRYPTION_KEY_1_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000864) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000864) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000864) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_IMAGE_ENCRYPTION_KEY_1_55_32_BMSK 0xffffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_IMAGE_ENCRYPTION_KEY_1_55_32_SHFT 0x0 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000868) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000868) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000868) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_IMAGE_ENCRYPTION_KEY_1_87_56_BMSK 0xffffffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_IMAGE_ENCRYPTION_KEY_1_87_56_SHFT 0x0 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000086c) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000086c) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000086c) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_IMAGE_ENCRYPTION_KEY_1_111_88_BMSK 0xffffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_IMAGE_ENCRYPTION_KEY_1_111_88_SHFT 0x0 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000870) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000870) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000870) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_UNUSED_254_15_0_BMSK 0xffff0000 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_UNUSED_254_15_0_SHFT 0x10 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_IMAGE_ENCRYPTION_KEY_1_BMSK 0xffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_IMAGE_ENCRYPTION_KEY_1_SHFT 0x0 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000874) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000874) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000874) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_UNUSED_254_39_16_BMSK 0xffffff #define HWIO_QFPROM_RAW_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_UNUSED_254_39_16_SHFT 0x0 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000878) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000878) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000878) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_USER_KEY_DERIVATION_KEY_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_LSB_USER_KEY_DERIVATION_KEY_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000087c) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000087c) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000087c) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_USER_KEY_DERIVATION_KEY_55_32_BMSK 0xffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW0_MSB_USER_KEY_DERIVATION_KEY_55_32_SHFT 0x0 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000880) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000880) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000880) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_USER_KEY_DERIVATION_KEY_87_56_BMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_LSB_USER_KEY_DERIVATION_KEY_87_56_SHFT 0x0 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000884) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000884) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000884) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_USER_KEY_DERIVATION_KEY_111_88_BMSK 0xffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW1_MSB_USER_KEY_DERIVATION_KEY_111_88_SHFT 0x0 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000888) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000888) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000888) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_ADDR) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_ADDR,v) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_IN) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_USER_KEY_DERIVATION_KEY_143_112_BMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_LSB_USER_KEY_DERIVATION_KEY_143_112_SHFT 0x0 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000088c) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000088c) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000088c) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_ADDR) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_ADDR,v) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_IN) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_USER_KEY_DERIVATION_KEY_167_144_BMSK 0xffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW2_MSB_USER_KEY_DERIVATION_KEY_167_144_SHFT 0x0 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000890) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000890) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000890) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_ADDR) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_ADDR,v) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_IN) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_USER_KEY_DERIVATION_KEY_199_168_BMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_LSB_USER_KEY_DERIVATION_KEY_199_168_SHFT 0x0 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000894) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000894) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000894) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_ADDR) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_ADDR,v) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_IN) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_USER_KEY_DERIVATION_KEY_223_200_BMSK 0xffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW3_MSB_USER_KEY_DERIVATION_KEY_223_200_SHFT 0x0 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000898) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00000898) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00000898) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_ADDR) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,v) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_IN) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_USER_KEY_DERIVATION_KEY_BMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_LSB_USER_KEY_DERIVATION_KEY_SHFT 0x0 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000089c) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000089c) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000089c) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_ADDR) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,v) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_ADDR,m,v,HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_IN) #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_BMSK 0x80000000 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_RSVD0_SHFT 0x1f #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_BMSK 0x7f000000 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_FEC_VALUE_SHFT 0x18 #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_UNUSED_259_BMSK 0xffffff #define HWIO_QFPROM_RAW_USER_KEY_DERIVATION_KEY_ROW4_MSB_UNUSED_259_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008a0) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008a0) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008a0) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_OEM_SPARE_28_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_LSB_OEM_SPARE_28_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008a4) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008a4) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008a4) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_OEM_SPARE_28_63_32_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW0_MSB_OEM_SPARE_28_63_32_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008a8) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008a8) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008a8) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_OEM_SPARE_28_95_64_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_LSB_OEM_SPARE_28_95_64_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008ac) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008ac) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008ac) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_OEM_SPARE_28_127_96_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_28_ROW1_MSB_OEM_SPARE_28_127_96_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008b0) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008b0) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008b0) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_OEM_SPARE_29_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_LSB_OEM_SPARE_29_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008b4) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008b4) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008b4) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_OEM_SPARE_29_63_32_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW0_MSB_OEM_SPARE_29_63_32_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008b8) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008b8) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008b8) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_OEM_SPARE_29_95_64_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_LSB_OEM_SPARE_29_95_64_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008bc) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008bc) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008bc) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_OEM_SPARE_29_127_96_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_29_ROW1_MSB_OEM_SPARE_29_127_96_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008c0) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008c0) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008c0) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_OEM_SPARE_30_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_LSB_OEM_SPARE_30_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008c4) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008c4) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008c4) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_OEM_SPARE_30_63_32_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW0_MSB_OEM_SPARE_30_63_32_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008c8) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008c8) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008c8) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_OEM_SPARE_30_95_64_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_LSB_OEM_SPARE_30_95_64_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008cc) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008cc) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008cc) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_OEM_SPARE_30_127_96_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_30_ROW1_MSB_OEM_SPARE_30_127_96_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008d0) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008d0) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008d0) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_OEM_SPARE_31_31_0_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_LSB_OEM_SPARE_31_31_0_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008d4) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008d4) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008d4) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_OEM_SPARE_31_63_32_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW0_MSB_OEM_SPARE_31_63_32_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008d8) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008d8) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008d8) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_OEM_SPARE_31_95_64_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_LSB_OEM_SPARE_31_95_64_SHFT 0x0 #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000008dc) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000008dc) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000008dc) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_ADDR) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_OUT(v) \ out_dword(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_ADDR,v) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_ADDR,m,v,HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_IN) #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_OEM_SPARE_31_127_96_BMSK 0xffffffff #define HWIO_QFPROM_RAW_OEM_SPARE_31_ROW1_MSB_OEM_SPARE_31_127_96_SHFT 0x0 #define HWIO_QFPROM_BLOW_TIMER_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000203c) #define HWIO_QFPROM_BLOW_TIMER_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000203c) #define HWIO_QFPROM_BLOW_TIMER_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000203c) #define HWIO_QFPROM_BLOW_TIMER_RMSK 0xfff #define HWIO_QFPROM_BLOW_TIMER_IN \ in_dword(HWIO_QFPROM_BLOW_TIMER_ADDR) #define HWIO_QFPROM_BLOW_TIMER_INM(m) \ in_dword_masked(HWIO_QFPROM_BLOW_TIMER_ADDR, m) #define HWIO_QFPROM_BLOW_TIMER_OUT(v) \ out_dword(HWIO_QFPROM_BLOW_TIMER_ADDR,v) #define HWIO_QFPROM_BLOW_TIMER_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_BLOW_TIMER_ADDR,m,v,HWIO_QFPROM_BLOW_TIMER_IN) #define HWIO_QFPROM_BLOW_TIMER_BLOW_TIMER_BMSK 0xfff #define HWIO_QFPROM_BLOW_TIMER_BLOW_TIMER_SHFT 0x0 #define HWIO_QFPROM_TEST_CTRL_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002040) #define HWIO_QFPROM_TEST_CTRL_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002040) #define HWIO_QFPROM_TEST_CTRL_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002040) #define HWIO_QFPROM_TEST_CTRL_RMSK 0xf #define HWIO_QFPROM_TEST_CTRL_IN \ in_dword(HWIO_QFPROM_TEST_CTRL_ADDR) #define HWIO_QFPROM_TEST_CTRL_INM(m) \ in_dword_masked(HWIO_QFPROM_TEST_CTRL_ADDR, m) #define HWIO_QFPROM_TEST_CTRL_OUT(v) \ out_dword(HWIO_QFPROM_TEST_CTRL_ADDR,v) #define HWIO_QFPROM_TEST_CTRL_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_TEST_CTRL_ADDR,m,v,HWIO_QFPROM_TEST_CTRL_IN) #define HWIO_QFPROM_TEST_CTRL_SEL_TST_ROM_BMSK 0x8 #define HWIO_QFPROM_TEST_CTRL_SEL_TST_ROM_SHFT 0x3 #define HWIO_QFPROM_TEST_CTRL_SEL_TST_WL_BMSK 0x4 #define HWIO_QFPROM_TEST_CTRL_SEL_TST_WL_SHFT 0x2 #define HWIO_QFPROM_TEST_CTRL_SEL_TST_BL_BMSK 0x2 #define HWIO_QFPROM_TEST_CTRL_SEL_TST_BL_SHFT 0x1 #define HWIO_QFPROM_TEST_CTRL_EN_FUSE_RES_MEAS_BMSK 0x1 #define HWIO_QFPROM_TEST_CTRL_EN_FUSE_RES_MEAS_SHFT 0x0 #define HWIO_QFPROM_ACCEL_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002044) #define HWIO_QFPROM_ACCEL_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002044) #define HWIO_QFPROM_ACCEL_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002044) #define HWIO_QFPROM_ACCEL_RMSK 0xfff #define HWIO_QFPROM_ACCEL_IN \ in_dword(HWIO_QFPROM_ACCEL_ADDR) #define HWIO_QFPROM_ACCEL_INM(m) \ in_dword_masked(HWIO_QFPROM_ACCEL_ADDR, m) #define HWIO_QFPROM_ACCEL_OUT(v) \ out_dword(HWIO_QFPROM_ACCEL_ADDR,v) #define HWIO_QFPROM_ACCEL_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_ACCEL_ADDR,m,v,HWIO_QFPROM_ACCEL_IN) #define HWIO_QFPROM_ACCEL_QFPROM_GATELAST_BMSK 0x800 #define HWIO_QFPROM_ACCEL_QFPROM_GATELAST_SHFT 0xb #define HWIO_QFPROM_ACCEL_QFPROM_TRIPPT_SEL_BMSK 0x700 #define HWIO_QFPROM_ACCEL_QFPROM_TRIPPT_SEL_SHFT 0x8 #define HWIO_QFPROM_ACCEL_QFPROM_ACCEL_BMSK 0xff #define HWIO_QFPROM_ACCEL_QFPROM_ACCEL_SHFT 0x0 #define HWIO_QFPROM_BLOW_STATUS_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002048) #define HWIO_QFPROM_BLOW_STATUS_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002048) #define HWIO_QFPROM_BLOW_STATUS_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002048) #define HWIO_QFPROM_BLOW_STATUS_RMSK 0x3 #define HWIO_QFPROM_BLOW_STATUS_IN \ in_dword(HWIO_QFPROM_BLOW_STATUS_ADDR) #define HWIO_QFPROM_BLOW_STATUS_INM(m) \ in_dword_masked(HWIO_QFPROM_BLOW_STATUS_ADDR, m) #define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_BMSK 0x2 #define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_SHFT 0x1 #define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_NO_ERROR_FVAL 0x0 #define HWIO_QFPROM_BLOW_STATUS_QFPROM_WR_ERR_ERROR_FVAL 0x1 #define HWIO_QFPROM_BLOW_STATUS_QFPROM_BUSY_BMSK 0x1 #define HWIO_QFPROM_BLOW_STATUS_QFPROM_BUSY_SHFT 0x0 #define HWIO_QFPROM_ROM_ERROR_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000204c) #define HWIO_QFPROM_ROM_ERROR_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000204c) #define HWIO_QFPROM_ROM_ERROR_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000204c) #define HWIO_QFPROM_ROM_ERROR_RMSK 0x1 #define HWIO_QFPROM_ROM_ERROR_IN \ in_dword(HWIO_QFPROM_ROM_ERROR_ADDR) #define HWIO_QFPROM_ROM_ERROR_INM(m) \ in_dword_masked(HWIO_QFPROM_ROM_ERROR_ADDR, m) #define HWIO_QFPROM_ROM_ERROR_ERROR_BMSK 0x1 #define HWIO_QFPROM_ROM_ERROR_ERROR_SHFT 0x0 #define HWIO_QFPROM_ROM_ERROR_ERROR_NO_ERROR_FVAL 0x0 #define HWIO_QFPROM_ROM_ERROR_ERROR_ERROR_FVAL 0x1 #define HWIO_QFPROM0_MATCH_STATUS_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002050) #define HWIO_QFPROM0_MATCH_STATUS_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002050) #define HWIO_QFPROM0_MATCH_STATUS_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002050) #define HWIO_QFPROM0_MATCH_STATUS_RMSK 0xffffffff #define HWIO_QFPROM0_MATCH_STATUS_IN \ in_dword(HWIO_QFPROM0_MATCH_STATUS_ADDR) #define HWIO_QFPROM0_MATCH_STATUS_INM(m) \ in_dword_masked(HWIO_QFPROM0_MATCH_STATUS_ADDR, m) #define HWIO_QFPROM0_MATCH_STATUS_FLAG_BMSK 0xffffffff #define HWIO_QFPROM0_MATCH_STATUS_FLAG_SHFT 0x0 #define HWIO_QFPROM1_MATCH_STATUS_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002054) #define HWIO_QFPROM1_MATCH_STATUS_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002054) #define HWIO_QFPROM1_MATCH_STATUS_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002054) #define HWIO_QFPROM1_MATCH_STATUS_RMSK 0xffffffff #define HWIO_QFPROM1_MATCH_STATUS_IN \ in_dword(HWIO_QFPROM1_MATCH_STATUS_ADDR) #define HWIO_QFPROM1_MATCH_STATUS_INM(m) \ in_dword_masked(HWIO_QFPROM1_MATCH_STATUS_ADDR, m) #define HWIO_QFPROM1_MATCH_STATUS_FLAG_BMSK 0xffffffff #define HWIO_QFPROM1_MATCH_STATUS_FLAG_SHFT 0x0 #define HWIO_FEC_ESR_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002058) #define HWIO_FEC_ESR_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002058) #define HWIO_FEC_ESR_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002058) #define HWIO_FEC_ESR_RMSK 0x2fdf #define HWIO_FEC_ESR_IN \ in_dword(HWIO_FEC_ESR_ADDR) #define HWIO_FEC_ESR_INM(m) \ in_dword_masked(HWIO_FEC_ESR_ADDR, m) #define HWIO_FEC_ESR_OUT(v) \ out_dword(HWIO_FEC_ESR_ADDR,v) #define HWIO_FEC_ESR_OUTM(m,v) \ out_dword_masked_ns(HWIO_FEC_ESR_ADDR,m,v,HWIO_FEC_ESR_IN) #define HWIO_FEC_ESR_CORR_SW_ACC_BMSK 0x2000 #define HWIO_FEC_ESR_CORR_SW_ACC_SHFT 0xd #define HWIO_FEC_ESR_CORR_SECURE_CHANNEL_BMSK 0x800 #define HWIO_FEC_ESR_CORR_SECURE_CHANNEL_SHFT 0xb #define HWIO_FEC_ESR_CORR_BOOT_ROM_BMSK 0x400 #define HWIO_FEC_ESR_CORR_BOOT_ROM_SHFT 0xa #define HWIO_FEC_ESR_CORR_FUSE_SENSE_BMSK 0x200 #define HWIO_FEC_ESR_CORR_FUSE_SENSE_SHFT 0x9 #define HWIO_FEC_ESR_CORR_MULT_BMSK 0x100 #define HWIO_FEC_ESR_CORR_MULT_SHFT 0x8 #define HWIO_FEC_ESR_CORR_SEEN_BMSK 0x80 #define HWIO_FEC_ESR_CORR_SEEN_SHFT 0x7 #define HWIO_FEC_ESR_CORR_SEEN_NO_CORRECTION_FVAL 0x0 #define HWIO_FEC_ESR_CORR_SEEN_CORRECTION_FVAL 0x1 #define HWIO_FEC_ESR_ERR_SW_ACC_BMSK 0x40 #define HWIO_FEC_ESR_ERR_SW_ACC_SHFT 0x6 #define HWIO_FEC_ESR_ERR_SECURE_CHANNEL_BMSK 0x10 #define HWIO_FEC_ESR_ERR_SECURE_CHANNEL_SHFT 0x4 #define HWIO_FEC_ESR_ERR_BOOT_ROM_BMSK 0x8 #define HWIO_FEC_ESR_ERR_BOOT_ROM_SHFT 0x3 #define HWIO_FEC_ESR_ERR_FUSE_SENSE_BMSK 0x4 #define HWIO_FEC_ESR_ERR_FUSE_SENSE_SHFT 0x2 #define HWIO_FEC_ESR_ERR_MULT_BMSK 0x2 #define HWIO_FEC_ESR_ERR_MULT_SHFT 0x1 #define HWIO_FEC_ESR_ERR_SEEN_BMSK 0x1 #define HWIO_FEC_ESR_ERR_SEEN_SHFT 0x0 #define HWIO_FEC_ESR_ERR_SEEN_NO_ERROR_FVAL 0x0 #define HWIO_FEC_ESR_ERR_SEEN_ERROR_FVAL 0x1 #define HWIO_FEC_EAR_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000205c) #define HWIO_FEC_EAR_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000205c) #define HWIO_FEC_EAR_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000205c) #define HWIO_FEC_EAR_RMSK 0xffffffff #define HWIO_FEC_EAR_IN \ in_dword(HWIO_FEC_EAR_ADDR) #define HWIO_FEC_EAR_INM(m) \ in_dword_masked(HWIO_FEC_EAR_ADDR, m) #define HWIO_FEC_EAR_CORR_ADDR_BMSK 0xffff0000 #define HWIO_FEC_EAR_CORR_ADDR_SHFT 0x10 #define HWIO_FEC_EAR_ERR_ADDR_BMSK 0xffff #define HWIO_FEC_EAR_ERR_ADDR_SHFT 0x0 #define HWIO_QFPROM_BIST_CTRL_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002060) #define HWIO_QFPROM_BIST_CTRL_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002060) #define HWIO_QFPROM_BIST_CTRL_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002060) #define HWIO_QFPROM_BIST_CTRL_RMSK 0xff #define HWIO_QFPROM_BIST_CTRL_IN \ in_dword(HWIO_QFPROM_BIST_CTRL_ADDR) #define HWIO_QFPROM_BIST_CTRL_INM(m) \ in_dword_masked(HWIO_QFPROM_BIST_CTRL_ADDR, m) #define HWIO_QFPROM_BIST_CTRL_OUT(v) \ out_dword(HWIO_QFPROM_BIST_CTRL_ADDR,v) #define HWIO_QFPROM_BIST_CTRL_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_BIST_CTRL_ADDR,m,v,HWIO_QFPROM_BIST_CTRL_IN) #define HWIO_QFPROM_BIST_CTRL_AUTH_REGION_BMSK 0xfc #define HWIO_QFPROM_BIST_CTRL_AUTH_REGION_SHFT 0x2 #define HWIO_QFPROM_BIST_CTRL_SHA_ENABLE_BMSK 0x2 #define HWIO_QFPROM_BIST_CTRL_SHA_ENABLE_SHFT 0x1 #define HWIO_QFPROM_BIST_CTRL_START_BMSK 0x1 #define HWIO_QFPROM_BIST_CTRL_START_SHFT 0x0 #define HWIO_QFPROM_BIST_ERROR0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002064) #define HWIO_QFPROM_BIST_ERROR0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002064) #define HWIO_QFPROM_BIST_ERROR0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002064) #define HWIO_QFPROM_BIST_ERROR0_RMSK 0xffffffff #define HWIO_QFPROM_BIST_ERROR0_IN \ in_dword(HWIO_QFPROM_BIST_ERROR0_ADDR) #define HWIO_QFPROM_BIST_ERROR0_INM(m) \ in_dword_masked(HWIO_QFPROM_BIST_ERROR0_ADDR, m) #define HWIO_QFPROM_BIST_ERROR0_ERROR_BMSK 0xffffffff #define HWIO_QFPROM_BIST_ERROR0_ERROR_SHFT 0x0 #define HWIO_QFPROM_BIST_ERROR0_ERROR_NO_ERROR_FVAL 0x0 #define HWIO_QFPROM_BIST_ERROR0_ERROR_ERROR_FVAL 0x1 #define HWIO_QFPROM_BIST_ERROR1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002068) #define HWIO_QFPROM_BIST_ERROR1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002068) #define HWIO_QFPROM_BIST_ERROR1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002068) #define HWIO_QFPROM_BIST_ERROR1_RMSK 0xffffffff #define HWIO_QFPROM_BIST_ERROR1_IN \ in_dword(HWIO_QFPROM_BIST_ERROR1_ADDR) #define HWIO_QFPROM_BIST_ERROR1_INM(m) \ in_dword_masked(HWIO_QFPROM_BIST_ERROR1_ADDR, m) #define HWIO_QFPROM_BIST_ERROR1_ERROR_BMSK 0xffffffff #define HWIO_QFPROM_BIST_ERROR1_ERROR_SHFT 0x0 #define HWIO_QFPROM_BIST_ERROR1_ERROR_NO_ERROR_FVAL 0x0 #define HWIO_QFPROM_BIST_ERROR1_ERROR_ERROR_FVAL 0x1 #define HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x0000206c + 0x4 * (n)) #define HWIO_QFPROM_HASH_SIGNATUREn_PHYS(n) (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000206c + 0x4 * (n)) #define HWIO_QFPROM_HASH_SIGNATUREn_OFFS(n) (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000206c + 0x4 * (n)) #define HWIO_QFPROM_HASH_SIGNATUREn_RMSK 0xffffffff #define HWIO_QFPROM_HASH_SIGNATUREn_MAXn 7 #define HWIO_QFPROM_HASH_SIGNATUREn_INI(n) \ in_dword_masked(HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n), HWIO_QFPROM_HASH_SIGNATUREn_RMSK) #define HWIO_QFPROM_HASH_SIGNATUREn_INMI(n,mask) \ in_dword_masked(HWIO_QFPROM_HASH_SIGNATUREn_ADDR(n), mask) #define HWIO_QFPROM_HASH_SIGNATUREn_HASH_VALUE_BMSK 0xffffffff #define HWIO_QFPROM_HASH_SIGNATUREn_HASH_VALUE_SHFT 0x0 #define HWIO_HW_KEY_STATUS_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000208c) #define HWIO_HW_KEY_STATUS_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000208c) #define HWIO_HW_KEY_STATUS_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000208c) #define HWIO_HW_KEY_STATUS_RMSK 0x7ff #define HWIO_HW_KEY_STATUS_IN \ in_dword(HWIO_HW_KEY_STATUS_ADDR) #define HWIO_HW_KEY_STATUS_INM(m) \ in_dword_masked(HWIO_HW_KEY_STATUS_ADDR, m) #define HWIO_HW_KEY_STATUS_MSA_SECURE_BMSK 0x400 #define HWIO_HW_KEY_STATUS_MSA_SECURE_SHFT 0xa #define HWIO_HW_KEY_STATUS_MSA_SECURE_MSA_NOT_SECURE_FVAL 0x0 #define HWIO_HW_KEY_STATUS_MSA_SECURE_MSA_SECURE_FVAL 0x1 #define HWIO_HW_KEY_STATUS_APPS_SECURE_BMSK 0x200 #define HWIO_HW_KEY_STATUS_APPS_SECURE_SHFT 0x9 #define HWIO_HW_KEY_STATUS_APPS_SECURE_APPS_NOT_SECURE_FVAL 0x0 #define HWIO_HW_KEY_STATUS_APPS_SECURE_APPS_SECURE_FVAL 0x1 #define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_BMSK 0x100 #define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_SHFT 0x8 #define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_KDF_AND_HW_KEY_SHIFT_IN_PROGRESS_FVAL 0x0 #define HWIO_HW_KEY_STATUS_KDF_AND_HW_KEY_SHIFT_DONE_KDF_AND_HW_KEY_SHIFT_HAS_COMPLETED_FVAL 0x1 #define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_BMSK 0x80 #define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_SHFT 0x7 #define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_HW_KEY_SHIFT_IN_PROGRESS_FVAL 0x0 #define HWIO_HW_KEY_STATUS_HW_KEY_SHIFT_DONE_HW_KEY_SHIFT_HAS_COMPLETED_FVAL 0x1 #define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_BMSK 0x40 #define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_SHFT 0x6 #define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_FUSE_SENSE_IN_PROGRESS_FVAL 0x0 #define HWIO_HW_KEY_STATUS_FUSE_SENSE_DONE_FUSE_SENSE_HAS_COMPLETED_FVAL 0x1 #define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_BMSK 0x20 #define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_SHFT 0x5 #define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_CRI_CM_BOOT_IN_PROGRESS_FVAL 0x0 #define HWIO_HW_KEY_STATUS_CRI_CM_BOOT_DONE_CRI_CM_BOOT_HAS_COMPLETED_FVAL 0x1 #define HWIO_HW_KEY_STATUS_KDF_DONE_BMSK 0x10 #define HWIO_HW_KEY_STATUS_KDF_DONE_SHFT 0x4 #define HWIO_HW_KEY_STATUS_KDF_DONE_KDF_OPERATION_IN_PROGRESS_FVAL 0x0 #define HWIO_HW_KEY_STATUS_KDF_DONE_KDF_OPERATION_HAS_COMPLETED_FVAL 0x1 #define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_BMSK 0x8 #define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_SHFT 0x3 #define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_NOT_BLOCKED_FVAL 0x0 #define HWIO_HW_KEY_STATUS_MSA_KEYS_BLOCKED_BLOCKED_FVAL 0x1 #define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_BMSK 0x4 #define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_SHFT 0x2 #define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_NOT_BLOCKED_FVAL 0x0 #define HWIO_HW_KEY_STATUS_APPS_KEYS_BLOCKED_BLOCKED_FVAL 0x1 #define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_BMSK 0x2 #define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_SHFT 0x1 #define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_NOT_BLOWN_FVAL 0x0 #define HWIO_HW_KEY_STATUS_SEC_KEY_DERIVATION_KEY_BLOWN_BLOWN_FVAL 0x1 #define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_BMSK 0x1 #define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_SHFT 0x0 #define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_NOT_BLOWN_FVAL 0x0 #define HWIO_HW_KEY_STATUS_PRI_KEY_DERIVATION_KEY_BLOWN_BLOWN_FVAL 0x1 #define HWIO_RESET_JDR_STATUS_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002090) #define HWIO_RESET_JDR_STATUS_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002090) #define HWIO_RESET_JDR_STATUS_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002090) #define HWIO_RESET_JDR_STATUS_RMSK 0x3 #define HWIO_RESET_JDR_STATUS_IN \ in_dword(HWIO_RESET_JDR_STATUS_ADDR) #define HWIO_RESET_JDR_STATUS_INM(m) \ in_dword_masked(HWIO_RESET_JDR_STATUS_ADDR, m) #define HWIO_RESET_JDR_STATUS_FORCE_RESET_BMSK 0x2 #define HWIO_RESET_JDR_STATUS_FORCE_RESET_SHFT 0x1 #define HWIO_RESET_JDR_STATUS_DISABLE_SYSTEM_RESET_BMSK 0x1 #define HWIO_RESET_JDR_STATUS_DISABLE_SYSTEM_RESET_SHFT 0x0 #define HWIO_ATPG_JDR_STATUS_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002094) #define HWIO_ATPG_JDR_STATUS_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002094) #define HWIO_ATPG_JDR_STATUS_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002094) #define HWIO_ATPG_JDR_STATUS_RMSK 0x1 #define HWIO_ATPG_JDR_STATUS_IN \ in_dword(HWIO_ATPG_JDR_STATUS_ADDR) #define HWIO_ATPG_JDR_STATUS_INM(m) \ in_dword_masked(HWIO_ATPG_JDR_STATUS_ADDR, m) #define HWIO_ATPG_JDR_STATUS_FUSE_SENSE_ATPG_CTL_BMSK 0x1 #define HWIO_ATPG_JDR_STATUS_FUSE_SENSE_ATPG_CTL_SHFT 0x0 #define HWIO_FEAT_PROV_OUTn_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x00002098 + 0x4 * (n)) #define HWIO_FEAT_PROV_OUTn_PHYS(n) (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002098 + 0x4 * (n)) #define HWIO_FEAT_PROV_OUTn_OFFS(n) (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002098 + 0x4 * (n)) #define HWIO_FEAT_PROV_OUTn_RMSK 0xffffffff #define HWIO_FEAT_PROV_OUTn_MAXn 3 #define HWIO_FEAT_PROV_OUTn_INI(n) \ in_dword_masked(HWIO_FEAT_PROV_OUTn_ADDR(n), HWIO_FEAT_PROV_OUTn_RMSK) #define HWIO_FEAT_PROV_OUTn_INMI(n,mask) \ in_dword_masked(HWIO_FEAT_PROV_OUTn_ADDR(n), mask) #define HWIO_FEAT_PROV_OUTn_FEAT_PROV_OUT_VALUE_BMSK 0xffffffff #define HWIO_FEAT_PROV_OUTn_FEAT_PROV_OUT_VALUE_SHFT 0x0 #define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x000020a8 + 0x4 * (n)) #define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_PHYS(n) (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000020a8 + 0x4 * (n)) #define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_OFFS(n) (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000020a8 + 0x4 * (n)) #define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_RMSK 0xffffffff #define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_MAXn 3 #define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_INI(n) \ in_dword_masked(HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n), HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_RMSK) #define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_INMI(n,mask) \ in_dword_masked(HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_ADDR(n), mask) #define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_SEC_CTRL_MISC_CONFIG_STATUS_VALUE_BMSK 0xffffffff #define HWIO_SEC_CTRL_MISC_CONFIG_STATUSn_SEC_CTRL_MISC_CONFIG_STATUS_VALUE_SHFT 0x0 #define HWIO_DEBUG_FUSE_STATUS_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000020f0) #define HWIO_DEBUG_FUSE_STATUS_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000020f0) #define HWIO_DEBUG_FUSE_STATUS_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000020f0) #define HWIO_DEBUG_FUSE_STATUS_RMSK 0xffffffff #define HWIO_DEBUG_FUSE_STATUS_IN \ in_dword(HWIO_DEBUG_FUSE_STATUS_ADDR) #define HWIO_DEBUG_FUSE_STATUS_INM(m) \ in_dword_masked(HWIO_DEBUG_FUSE_STATUS_ADDR, m) #define HWIO_DEBUG_FUSE_STATUS_RSVD0_BMSK 0xff000000 #define HWIO_DEBUG_FUSE_STATUS_RSVD0_SHFT 0x18 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC5_DEBUG_BMSK 0x800000 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC5_DEBUG_SHFT 0x17 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC4_DEBUG_BMSK 0x400000 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC4_DEBUG_SHFT 0x16 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC3_DEBUG_BMSK 0x200000 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC3_DEBUG_SHFT 0x15 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC2_DEBUG_BMSK 0x100000 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC2_DEBUG_SHFT 0x14 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC1_DEBUG_BMSK 0x80000 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC1_DEBUG_SHFT 0x13 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC_DEBUG_BMSK 0x40000 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MISC_DEBUG_SHFT 0x12 #define HWIO_DEBUG_FUSE_STATUS_APPS_NIDEN_BMSK 0x20000 #define HWIO_DEBUG_FUSE_STATUS_APPS_NIDEN_SHFT 0x11 #define HWIO_DEBUG_FUSE_STATUS_APPS_DBGEN_BMSK 0x10000 #define HWIO_DEBUG_FUSE_STATUS_APPS_DBGEN_SHFT 0x10 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPNIDEN_BMSK 0x8000 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPNIDEN_SHFT 0xf #define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPNIDEN_BMSK 0x4000 #define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPNIDEN_SHFT 0xe #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_NIDEN_BMSK 0x2000 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_NIDEN_SHFT 0xd #define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_NIDEN_BMSK 0x1000 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_NIDEN_SHFT 0xc #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_NIDEN_BMSK 0x800 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_NIDEN_SHFT 0xb #define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_NIDEN_BMSK 0x400 #define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_NIDEN_SHFT 0xa #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_NIDEN_BMSK 0x200 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_NIDEN_SHFT 0x9 #define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_NIDEN_BMSK 0x100 #define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_NIDEN_SHFT 0x8 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPIDEN_BMSK 0x80 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_QSEE_SPIDEN_SHFT 0x7 #define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPIDEN_BMSK 0x40 #define HWIO_DEBUG_FUSE_STATUS_SHARED_QSEE_SPIDEN_SHFT 0x6 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_DBGEN_BMSK 0x20 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_MSS_DBGEN_SHFT 0x5 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_DBGEN_BMSK 0x10 #define HWIO_DEBUG_FUSE_STATUS_SHARED_MSS_DBGEN_SHFT 0x4 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_DBGEN_BMSK 0x8 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_CP_DBGEN_SHFT 0x3 #define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_DBGEN_BMSK 0x4 #define HWIO_DEBUG_FUSE_STATUS_SHARED_CP_DBGEN_SHFT 0x2 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_DBGEN_BMSK 0x2 #define HWIO_DEBUG_FUSE_STATUS_PRIVATE_NS_DBGEN_SHFT 0x1 #define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_DBGEN_BMSK 0x1 #define HWIO_DEBUG_FUSE_STATUS_SHARED_NS_DBGEN_SHFT 0x0 #define HWIO_HW_ATTESTATION_CTRL0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002100) #define HWIO_HW_ATTESTATION_CTRL0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002100) #define HWIO_HW_ATTESTATION_CTRL0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002100) #define HWIO_HW_ATTESTATION_CTRL0_RMSK 0x1fffffff #define HWIO_HW_ATTESTATION_CTRL0_IN \ in_dword(HWIO_HW_ATTESTATION_CTRL0_ADDR) #define HWIO_HW_ATTESTATION_CTRL0_INM(m) \ in_dword_masked(HWIO_HW_ATTESTATION_CTRL0_ADDR, m) #define HWIO_HW_ATTESTATION_CTRL0_OUT(v) \ out_dword(HWIO_HW_ATTESTATION_CTRL0_ADDR,v) #define HWIO_HW_ATTESTATION_CTRL0_OUTM(m,v) \ out_dword_masked_ns(HWIO_HW_ATTESTATION_CTRL0_ADDR,m,v,HWIO_HW_ATTESTATION_CTRL0_IN) #define HWIO_HW_ATTESTATION_CTRL0_REGION_BMSK 0x1f800000 #define HWIO_HW_ATTESTATION_CTRL0_REGION_SHFT 0x17 #define HWIO_HW_ATTESTATION_CTRL0_CONTEXT_STRING_BMSK 0x7fff80 #define HWIO_HW_ATTESTATION_CTRL0_CONTEXT_STRING_SHFT 0x7 #define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_BMSK 0x78 #define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_SHFT 0x3 #define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_PKDK_FVAL 0x0 #define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_SKDK_FVAL 0x1 #define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_RTL_TEST_KEY_FVAL 0x2 #define HWIO_HW_ATTESTATION_CTRL0_KEY_SELECT_RTL_COMMERCIAL_KEY_FVAL 0x3 #define HWIO_HW_ATTESTATION_CTRL0_OPERATION_BMSK 0x7 #define HWIO_HW_ATTESTATION_CTRL0_OPERATION_SHFT 0x0 #define HWIO_HW_ATTESTATION_CTRL0_OPERATION_DEFAULT_FVAL 0x0 #define HWIO_HW_ATTESTATION_CTRL0_OPERATION_KEY_GEN_FVAL 0x1 #define HWIO_HW_ATTESTATION_CTRL0_OPERATION_START_FVAL 0x2 #define HWIO_HW_ATTESTATION_CTRL0_OPERATION_UPDATE_FVAL 0x3 #define HWIO_HW_ATTESTATION_CTRL0_OPERATION_FINAL_FVAL 0x4 #define HWIO_HW_ATTESTATION_CTRL1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002104) #define HWIO_HW_ATTESTATION_CTRL1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002104) #define HWIO_HW_ATTESTATION_CTRL1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002104) #define HWIO_HW_ATTESTATION_CTRL1_RMSK 0xffffffff #define HWIO_HW_ATTESTATION_CTRL1_IN \ in_dword(HWIO_HW_ATTESTATION_CTRL1_ADDR) #define HWIO_HW_ATTESTATION_CTRL1_INM(m) \ in_dword_masked(HWIO_HW_ATTESTATION_CTRL1_ADDR, m) #define HWIO_HW_ATTESTATION_CTRL1_OUT(v) \ out_dword(HWIO_HW_ATTESTATION_CTRL1_ADDR,v) #define HWIO_HW_ATTESTATION_CTRL1_OUTM(m,v) \ out_dword_masked_ns(HWIO_HW_ATTESTATION_CTRL1_ADDR,m,v,HWIO_HW_ATTESTATION_CTRL1_IN) #define HWIO_HW_ATTESTATION_CTRL1_NONCE_BMSK 0xffffffff #define HWIO_HW_ATTESTATION_CTRL1_NONCE_SHFT 0x0 #define HWIO_HW_ATTESTATION_CMD_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002108) #define HWIO_HW_ATTESTATION_CMD_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002108) #define HWIO_HW_ATTESTATION_CMD_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002108) #define HWIO_HW_ATTESTATION_CMD_RMSK 0x1 #define HWIO_HW_ATTESTATION_CMD_OUT(v) \ out_dword(HWIO_HW_ATTESTATION_CMD_ADDR,v) #define HWIO_HW_ATTESTATION_CMD_OPERATION_COMMAND_BMSK 0x1 #define HWIO_HW_ATTESTATION_CMD_OPERATION_COMMAND_SHFT 0x0 #define HWIO_HW_ATTESTATION_STATUS_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000210c) #define HWIO_HW_ATTESTATION_STATUS_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000210c) #define HWIO_HW_ATTESTATION_STATUS_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000210c) #define HWIO_HW_ATTESTATION_STATUS_RMSK 0xffffffff #define HWIO_HW_ATTESTATION_STATUS_IN \ in_dword(HWIO_HW_ATTESTATION_STATUS_ADDR) #define HWIO_HW_ATTESTATION_STATUS_INM(m) \ in_dword_masked(HWIO_HW_ATTESTATION_STATUS_ADDR, m) #define HWIO_HW_ATTESTATION_STATUS_STATUS_BMSK 0xffffffff #define HWIO_HW_ATTESTATION_STATUS_STATUS_SHFT 0x0 #define HWIO_HW_ATTESTATION_STATUS_STATUS_HW_ATTEST_DERIVED_KEY_READY_FVAL 0x0 #define HWIO_HW_ATTESTATION_STATUS_STATUS_HW_ATTEST_MAC_VALUE_READY_FVAL 0x1 #define HWIO_HW_ATTESTATION_ERROR_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00002110) #define HWIO_HW_ATTESTATION_ERROR_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002110) #define HWIO_HW_ATTESTATION_ERROR_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002110) #define HWIO_HW_ATTESTATION_ERROR_RMSK 0xffffffff #define HWIO_HW_ATTESTATION_ERROR_IN \ in_dword(HWIO_HW_ATTESTATION_ERROR_ADDR) #define HWIO_HW_ATTESTATION_ERROR_INM(m) \ in_dword_masked(HWIO_HW_ATTESTATION_ERROR_ADDR, m) #define HWIO_HW_ATTESTATION_ERROR_ERROR_BMSK 0xffffffff #define HWIO_HW_ATTESTATION_ERROR_ERROR_SHFT 0x0 #define HWIO_HW_ATTESTATION_ERROR_ERROR_REGION_OUTSIDE_VALID_RANGE_FVAL 0x0 #define HWIO_HW_ATTESTATION_RESULTn_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x00002120 + 0x4 * (n)) #define HWIO_HW_ATTESTATION_RESULTn_PHYS(n) (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00002120 + 0x4 * (n)) #define HWIO_HW_ATTESTATION_RESULTn_OFFS(n) (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00002120 + 0x4 * (n)) #define HWIO_HW_ATTESTATION_RESULTn_RMSK 0xffffffff #define HWIO_HW_ATTESTATION_RESULTn_MAXn 7 #define HWIO_HW_ATTESTATION_RESULTn_INI(n) \ in_dword_masked(HWIO_HW_ATTESTATION_RESULTn_ADDR(n), HWIO_HW_ATTESTATION_RESULTn_RMSK) #define HWIO_HW_ATTESTATION_RESULTn_INMI(n,mask) \ in_dword_masked(HWIO_HW_ATTESTATION_RESULTn_ADDR(n), mask) #define HWIO_HW_ATTESTATION_RESULTn_RESULT_BMSK 0xffffffff #define HWIO_HW_ATTESTATION_RESULTn_RESULT_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004000) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004000) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004000) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_LSB_CM_CORE_PRIVATE_OTP_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_LSB_CM_CORE_PRIVATE_OTP_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004004) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004004) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004004) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_MSB_CM_CORE_PRIVATE_OTP_63_32_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW0_MSB_CM_CORE_PRIVATE_OTP_63_32_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004008) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004008) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004008) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_LSB_CM_CORE_PRIVATE_OTP_95_64_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_LSB_CM_CORE_PRIVATE_OTP_95_64_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000400c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000400c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000400c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_MSB_CM_CORE_PRIVATE_OTP_127_96_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW1_MSB_CM_CORE_PRIVATE_OTP_127_96_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004010) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004010) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004010) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_LSB_CM_CORE_PRIVATE_OTP_159_128_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_LSB_CM_CORE_PRIVATE_OTP_159_128_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004014) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004014) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004014) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_MSB_CM_CORE_PRIVATE_OTP_191_160_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW2_MSB_CM_CORE_PRIVATE_OTP_191_160_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004018) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004018) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004018) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_LSB_CM_CORE_PRIVATE_OTP_223_192_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_LSB_CM_CORE_PRIVATE_OTP_223_192_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000401c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000401c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000401c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_MSB_CM_CORE_PRIVATE_OTP_255_224_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW3_MSB_CM_CORE_PRIVATE_OTP_255_224_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004020) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004020) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004020) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_LSB_CM_CORE_PRIVATE_OTP_287_256_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_LSB_CM_CORE_PRIVATE_OTP_287_256_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004024) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004024) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004024) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_MSB_CM_CORE_PRIVATE_OTP_319_288_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW4_MSB_CM_CORE_PRIVATE_OTP_319_288_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004028) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004028) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004028) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_LSB_CM_CORE_PRIVATE_OTP_351_320_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_LSB_CM_CORE_PRIVATE_OTP_351_320_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000402c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000402c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000402c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_MSB_CM_CORE_PRIVATE_OTP_383_352_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW5_MSB_CM_CORE_PRIVATE_OTP_383_352_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004030) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004030) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004030) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_LSB_CM_CORE_PRIVATE_OTP_415_384_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_LSB_CM_CORE_PRIVATE_OTP_415_384_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004034) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004034) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004034) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_MSB_CM_CORE_PRIVATE_OTP_447_416_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW6_MSB_CM_CORE_PRIVATE_OTP_447_416_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004038) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004038) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004038) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_LSB_CM_CORE_PRIVATE_OTP_479_448_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_LSB_CM_CORE_PRIVATE_OTP_479_448_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000403c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000403c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000403c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_MSB_CM_CORE_PRIVATE_OTP_511_480_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW7_MSB_CM_CORE_PRIVATE_OTP_511_480_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004040) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004040) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004040) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_LSB_CM_CORE_PRIVATE_OTP_543_512_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_LSB_CM_CORE_PRIVATE_OTP_543_512_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004044) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004044) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004044) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_MSB_CM_CORE_PRIVATE_OTP_575_544_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW8_MSB_CM_CORE_PRIVATE_OTP_575_544_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004048) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004048) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004048) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_LSB_CM_CORE_PRIVATE_OTP_607_576_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_LSB_CM_CORE_PRIVATE_OTP_607_576_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000404c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000404c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000404c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_MSB_CM_CORE_PRIVATE_OTP_639_608_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW9_MSB_CM_CORE_PRIVATE_OTP_639_608_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004050) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004050) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004050) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_LSB_CM_CORE_PRIVATE_OTP_671_640_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_LSB_CM_CORE_PRIVATE_OTP_671_640_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004054) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004054) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004054) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_MSB_CM_CORE_PRIVATE_OTP_703_672_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW10_MSB_CM_CORE_PRIVATE_OTP_703_672_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004058) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004058) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004058) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_LSB_CM_CORE_PRIVATE_OTP_735_704_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_LSB_CM_CORE_PRIVATE_OTP_735_704_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000405c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000405c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000405c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_MSB_CM_CORE_PRIVATE_OTP_767_736_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW11_MSB_CM_CORE_PRIVATE_OTP_767_736_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004060) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004060) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004060) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_LSB_CM_CORE_PRIVATE_OTP_799_768_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_LSB_CM_CORE_PRIVATE_OTP_799_768_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004064) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004064) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004064) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_MSB_CM_CORE_PRIVATE_OTP_831_800_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW12_MSB_CM_CORE_PRIVATE_OTP_831_800_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004068) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004068) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004068) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_LSB_CM_CORE_PRIVATE_OTP_863_832_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_LSB_CM_CORE_PRIVATE_OTP_863_832_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000406c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000406c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000406c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_MSB_CM_CORE_PRIVATE_OTP_895_864_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW13_MSB_CM_CORE_PRIVATE_OTP_895_864_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004070) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004070) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004070) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_LSB_CM_CORE_PRIVATE_OTP_927_896_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_LSB_CM_CORE_PRIVATE_OTP_927_896_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004074) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004074) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004074) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_MSB_CM_CORE_PRIVATE_OTP_959_928_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW14_MSB_CM_CORE_PRIVATE_OTP_959_928_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004078) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004078) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004078) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_LSB_CM_CORE_PRIVATE_OTP_991_960_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_LSB_CM_CORE_PRIVATE_OTP_991_960_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000407c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000407c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000407c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_MSB_CM_CORE_PRIVATE_OTP_1023_992_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW15_MSB_CM_CORE_PRIVATE_OTP_1023_992_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004080) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004080) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004080) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_LSB_CM_CORE_PRIVATE_OTP_1055_1024_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_LSB_CM_CORE_PRIVATE_OTP_1055_1024_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004084) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004084) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004084) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_MSB_CM_CORE_PRIVATE_OTP_1087_1056_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW16_MSB_CM_CORE_PRIVATE_OTP_1087_1056_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004088) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004088) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004088) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_LSB_CM_CORE_PRIVATE_OTP_1119_1088_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_LSB_CM_CORE_PRIVATE_OTP_1119_1088_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000408c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000408c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000408c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_MSB_CM_CORE_PRIVATE_OTP_1151_1120_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW17_MSB_CM_CORE_PRIVATE_OTP_1151_1120_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004090) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004090) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004090) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_LSB_CM_CORE_PRIVATE_OTP_1183_1152_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_LSB_CM_CORE_PRIVATE_OTP_1183_1152_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004094) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004094) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004094) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_MSB_CM_CORE_PRIVATE_OTP_1215_1184_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW18_MSB_CM_CORE_PRIVATE_OTP_1215_1184_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004098) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004098) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004098) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_LSB_CM_CORE_PRIVATE_OTP_1247_1216_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_LSB_CM_CORE_PRIVATE_OTP_1247_1216_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000409c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000409c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000409c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_MSB_CM_CORE_PRIVATE_OTP_1279_1248_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW19_MSB_CM_CORE_PRIVATE_OTP_1279_1248_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040a0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040a0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040a0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_LSB_CM_CORE_PRIVATE_OTP_1311_1280_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_LSB_CM_CORE_PRIVATE_OTP_1311_1280_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040a4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040a4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040a4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_MSB_CM_CORE_PRIVATE_OTP_1343_1312_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW20_MSB_CM_CORE_PRIVATE_OTP_1343_1312_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040a8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040a8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040a8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_LSB_CM_CORE_PRIVATE_OTP_1375_1344_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_LSB_CM_CORE_PRIVATE_OTP_1375_1344_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040ac) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040ac) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040ac) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_MSB_CM_CORE_PRIVATE_OTP_1407_1376_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW21_MSB_CM_CORE_PRIVATE_OTP_1407_1376_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040b0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040b0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040b0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_LSB_CM_CORE_PRIVATE_OTP_1439_1408_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_LSB_CM_CORE_PRIVATE_OTP_1439_1408_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040b4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040b4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040b4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_MSB_CM_CORE_PRIVATE_OTP_1471_1440_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW22_MSB_CM_CORE_PRIVATE_OTP_1471_1440_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040b8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040b8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040b8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_LSB_CM_CORE_PRIVATE_OTP_1503_1472_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_LSB_CM_CORE_PRIVATE_OTP_1503_1472_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040bc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040bc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040bc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_MSB_CM_CORE_PRIVATE_OTP_1535_1504_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW23_MSB_CM_CORE_PRIVATE_OTP_1535_1504_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040c0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040c0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040c0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_LSB_CM_CORE_PRIVATE_OTP_1567_1536_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_LSB_CM_CORE_PRIVATE_OTP_1567_1536_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040c4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040c4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040c4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_MSB_CM_CORE_PRIVATE_OTP_1599_1568_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW24_MSB_CM_CORE_PRIVATE_OTP_1599_1568_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040c8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040c8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040c8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_LSB_CM_CORE_PRIVATE_OTP_1631_1600_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_LSB_CM_CORE_PRIVATE_OTP_1631_1600_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040cc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040cc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040cc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_MSB_CM_CORE_PRIVATE_OTP_1663_1632_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW25_MSB_CM_CORE_PRIVATE_OTP_1663_1632_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040d0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040d0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040d0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_LSB_CM_CORE_PRIVATE_OTP_1695_1664_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_LSB_CM_CORE_PRIVATE_OTP_1695_1664_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040d4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040d4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040d4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_MSB_CM_CORE_PRIVATE_OTP_1727_1696_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW26_MSB_CM_CORE_PRIVATE_OTP_1727_1696_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040d8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040d8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040d8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_LSB_CM_CORE_PRIVATE_OTP_1759_1728_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_LSB_CM_CORE_PRIVATE_OTP_1759_1728_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040dc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040dc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040dc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_MSB_CM_CORE_PRIVATE_OTP_1791_1760_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW27_MSB_CM_CORE_PRIVATE_OTP_1791_1760_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040e0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040e0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040e0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_LSB_CM_CORE_PRIVATE_OTP_1823_1792_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_LSB_CM_CORE_PRIVATE_OTP_1823_1792_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040e4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040e4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040e4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_MSB_CM_CORE_PRIVATE_OTP_1855_1824_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW28_MSB_CM_CORE_PRIVATE_OTP_1855_1824_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040e8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040e8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040e8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_LSB_CM_CORE_PRIVATE_OTP_1887_1856_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_LSB_CM_CORE_PRIVATE_OTP_1887_1856_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040ec) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040ec) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040ec) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_MSB_CM_CORE_PRIVATE_OTP_1919_1888_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW29_MSB_CM_CORE_PRIVATE_OTP_1919_1888_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040f0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040f0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040f0) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_LSB_CM_CORE_PRIVATE_OTP_1951_1920_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_LSB_CM_CORE_PRIVATE_OTP_1951_1920_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040f4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040f4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040f4) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_MSB_CM_CORE_PRIVATE_OTP_1983_1952_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW30_MSB_CM_CORE_PRIVATE_OTP_1983_1952_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040f8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040f8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040f8) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_LSB_CM_CORE_PRIVATE_OTP_2015_1984_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_LSB_CM_CORE_PRIVATE_OTP_2015_1984_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000040fc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000040fc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000040fc) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_MSB_CM_CORE_PRIVATE_OTP_2047_2016_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW31_MSB_CM_CORE_PRIVATE_OTP_2047_2016_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004100) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004100) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004100) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_LSB_CM_CORE_PRIVATE_OTP_2079_2048_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_LSB_CM_CORE_PRIVATE_OTP_2079_2048_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004104) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004104) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004104) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_MSB_CM_CORE_PRIVATE_OTP_2111_2080_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW32_MSB_CM_CORE_PRIVATE_OTP_2111_2080_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004108) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004108) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004108) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_LSB_CM_CORE_PRIVATE_OTP_2143_2112_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_LSB_CM_CORE_PRIVATE_OTP_2143_2112_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000410c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000410c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000410c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_MSB_CM_CORE_PRIVATE_OTP_2175_2144_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW33_MSB_CM_CORE_PRIVATE_OTP_2175_2144_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004110) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004110) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004110) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_LSB_CM_CORE_PRIVATE_OTP_2207_2176_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_LSB_CM_CORE_PRIVATE_OTP_2207_2176_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004114) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004114) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004114) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_MSB_CM_CORE_PRIVATE_OTP_2239_2208_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW34_MSB_CM_CORE_PRIVATE_OTP_2239_2208_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004118) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004118) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004118) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_LSB_CM_CORE_PRIVATE_OTP_2271_2240_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_LSB_CM_CORE_PRIVATE_OTP_2271_2240_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000411c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000411c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000411c) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_MSB_CM_CORE_PRIVATE_OTP_2303_2272_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_CORE_PRIVATE_OTP_ROW35_MSB_CM_CORE_PRIVATE_OTP_2303_2272_SHFT 0x0 #define HWIO_QFPROM_CORR_LCM_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004120) #define HWIO_QFPROM_CORR_LCM_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004120) #define HWIO_QFPROM_CORR_LCM_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004120) #define HWIO_QFPROM_CORR_LCM_LSB_RMSK 0xe000001f #define HWIO_QFPROM_CORR_LCM_LSB_IN \ in_dword(HWIO_QFPROM_CORR_LCM_LSB_ADDR) #define HWIO_QFPROM_CORR_LCM_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_LCM_LSB_ADDR, m) #define HWIO_QFPROM_CORR_LCM_LSB_DISABLE_LCM_BMSK 0x80000000 #define HWIO_QFPROM_CORR_LCM_LSB_DISABLE_LCM_SHFT 0x1f #define HWIO_QFPROM_CORR_LCM_LSB_DISABLE_LCM_STATE_TRANSITION_BMSK 0x40000000 #define HWIO_QFPROM_CORR_LCM_LSB_DISABLE_LCM_STATE_TRANSITION_SHFT 0x1e #define HWIO_QFPROM_CORR_LCM_LSB_DISABLE_SECURE_PHK_BMSK 0x20000000 #define HWIO_QFPROM_CORR_LCM_LSB_DISABLE_SECURE_PHK_SHFT 0x1d #define HWIO_QFPROM_CORR_LCM_LSB_QC_EXTERNAL_BMSK 0x10 #define HWIO_QFPROM_CORR_LCM_LSB_QC_EXTERNAL_SHFT 0x4 #define HWIO_QFPROM_CORR_LCM_LSB_QC_INTERNAL_BMSK 0x8 #define HWIO_QFPROM_CORR_LCM_LSB_QC_INTERNAL_SHFT 0x3 #define HWIO_QFPROM_CORR_LCM_LSB_QC_FEAT_CONFIG_BMSK 0x4 #define HWIO_QFPROM_CORR_LCM_LSB_QC_FEAT_CONFIG_SHFT 0x2 #define HWIO_QFPROM_CORR_LCM_LSB_HW_TEST_BMSK 0x2 #define HWIO_QFPROM_CORR_LCM_LSB_HW_TEST_SHFT 0x1 #define HWIO_QFPROM_CORR_LCM_LSB_SOC_PERSO_BMSK 0x1 #define HWIO_QFPROM_CORR_LCM_LSB_SOC_PERSO_SHFT 0x0 #define HWIO_QFPROM_CORR_LCM_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004124) #define HWIO_QFPROM_CORR_LCM_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004124) #define HWIO_QFPROM_CORR_LCM_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004124) #define HWIO_QFPROM_CORR_LCM_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_LCM_MSB_IN \ in_dword(HWIO_QFPROM_CORR_LCM_MSB_ADDR) #define HWIO_QFPROM_CORR_LCM_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_LCM_MSB_ADDR, m) #define HWIO_QFPROM_CORR_LCM_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_CORR_LCM_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004128) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004128) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004128) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_LSB_PRI_KEY_DERIVATION_KEY_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_LSB_PRI_KEY_DERIVATION_KEY_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000412c) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000412c) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000412c) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_MSB_PRI_KEY_DERIVATION_KEY_63_32_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW0_MSB_PRI_KEY_DERIVATION_KEY_63_32_SHFT 0x0 #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004130) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004130) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004130) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_LSB_PRI_KEY_DERIVATION_KEY_95_64_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_LSB_PRI_KEY_DERIVATION_KEY_95_64_SHFT 0x0 #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004134) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004134) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004134) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_MSB_PRI_KEY_DERIVATION_KEY_127_96_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW1_MSB_PRI_KEY_DERIVATION_KEY_127_96_SHFT 0x0 #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004138) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004138) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004138) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_LSB_PRI_KEY_DERIVATION_KEY_159_128_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_LSB_PRI_KEY_DERIVATION_KEY_159_128_SHFT 0x0 #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000413c) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000413c) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000413c) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_MSB_PRI_KEY_DERIVATION_KEY_191_160_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW2_MSB_PRI_KEY_DERIVATION_KEY_191_160_SHFT 0x0 #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004140) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004140) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004140) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_LSB_ADDR) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_LSB_PRI_KEY_DERIVATION_KEY_223_192_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_LSB_PRI_KEY_DERIVATION_KEY_223_192_SHFT 0x0 #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004144) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004144) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004144) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_MSB_ADDR) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_MSB_PRI_KEY_DERIVATION_KEY_255_224_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PRI_KEY_DERIVATION_KEY_ROW3_MSB_PRI_KEY_DERIVATION_KEY_255_224_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004148) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004148) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004148) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_BMSK 0xffff8000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_SHFT 0xf #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK 0x7fff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000414c) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000414c) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000414c) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_BMSK 0xffffff00 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_SHFT 0x8 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_BMSK 0xff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004150) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004150) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004150) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_BMSK 0xffffff00 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_SHFT 0x8 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_BMSK 0xff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004154) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004154) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004154) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_MDSS_RESOLUTION_LIMIT_BMSK 0xc0000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_MDSS_RESOLUTION_LIMIT_SHFT 0x1e #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DP_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DP_DISABLE_SHFT 0x1d #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_DISABLE_SHFT 0x1c #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_MDP_APICAL_LTC_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_MDP_APICAL_LTC_DISABLE_SHFT 0x1b #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_MDP_APICAL_LTC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_MDP_APICAL_LTC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT 0x1a #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DSI_1_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DSI_1_DISABLE_SHFT 0x19 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DSI_1_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DSI_1_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DSI_0_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DSI_0_DISABLE_SHFT 0x18 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DSI_0_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_DSI_0_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_BMSK 0xffffff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004158) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004158) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004158) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_MOCHA_PART_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_MOCHA_PART_SHFT 0x1f #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_QC_SP_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_QC_SP_DISABLE_SHFT 0x1e #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_QC_SP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_QC_SP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SMMU_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SMMU_DISABLE_SHFT 0x1d #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SMMU_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SMMU_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_DISABLE_SEC_BOOT_GPIO_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_DISABLE_SEC_BOOT_GPIO_SHFT 0x1c #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_QC_UDK_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_QC_UDK_DISABLE_SHFT 0x1b #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_QC_UDK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_QC_UDK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_SHFT 0x1a #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_1_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_1_DISABLE_SHFT 0x19 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_1_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_1_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_0_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_0_DISABLE_SHFT 0x18 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_0_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_PCIE_0_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_DISABLE_SHFT 0x17 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT 0x16 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK 0x200000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT 0x15 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK 0x1fe000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT 0xd #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_SHFT 0xc #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK 0x800 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT 0xb #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK 0x400 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT 0xa #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_4K_DISABLE_BMSK 0x200 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_4K_DISABLE_SHFT 0x9 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_4K_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_4K_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_CVP_DISABLE_BMSK 0x100 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_CVP_DISABLE_SHFT 0x8 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_CVP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_CVP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_DISABLE_VPX_BMSK 0x80 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_DISABLE_VPX_SHFT 0x7 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_DISABLE_VPX_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_IRIS_DISABLE_VPX_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_BMSK 0x40 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_SHFT 0x6 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_EUD_PORT1_SEL_BMSK 0x20 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_EUD_PORT1_SEL_SHFT 0x5 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_EUD_PORT1_SEL_USB_PORT0_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_EUD_PORT1_SEL_USB_PORT1_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_EUD_IGNR_CSR_BMSK 0x10 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_EUD_IGNR_CSR_SHFT 0x4 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_MDSS_Q_CONFIG_FUSE_BMSK 0x8 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_MDSS_Q_CONFIG_FUSE_SHFT 0x3 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_MDSS_Q_CONFIG_FUSE_HANA_FEAT_SET_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_MDSS_Q_CONFIG_FUSE_HANAQ_FEAT_SET_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SPR_DISABLE_BMSK 0x4 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_SPR_DISABLE_SHFT 0x2 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_DEMURA_DISABLE_BMSK 0x2 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_DEMURA_DISABLE_SHFT 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_MST_DISABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_LSB_MST_DISABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000415c) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000415c) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000415c) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK 0xfc000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT 0x1a #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT 0x19 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK 0x1fe0000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT 0x11 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_APSS_PDXWRPNTRDELAY_BMSK 0x18000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_APSS_PDXWRPNTRDELAY_SHFT 0xf #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_GATE_SRST_FUSE_BMSK 0x4000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_GATE_SRST_FUSE_SHFT 0xe #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_GATE_SRST_FUSE_UNGATED_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_GATE_SRST_FUSE_GATED_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK 0x2000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT 0xd #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_MOBILE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_AUTOMOTIVE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_POWER_BMSK 0x1000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_POWER_SHFT 0xc #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_POWER_MOBILE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_AUTOMOTIVE_BIT_POWER_AUTOMOTIVE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_EMAC_DISABLE_BMSK 0x800 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_EMAC_DISABLE_SHFT 0xb #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_EMAC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_EMAC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_BMSK 0x400 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_SHFT 0xa #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_NAV_EFUSE_DISABLE_BMSK 0x200 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_NAV_EFUSE_DISABLE_SHFT 0x9 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_NAV_EFUSE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_NAV_EFUSE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_CORTEX_M3_DISABLE_BMSK 0x100 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_CORTEX_M3_DISABLE_SHFT 0x8 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_APS_RESET_DISABLE_BMSK 0x80 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_APS_RESET_DISABLE_SHFT 0x7 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_DOLBY_BIT_BMSK 0x40 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_DOLBY_BIT_SHFT 0x6 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_I_MC5_FUSE_BMSK 0x20 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_I_MC5_FUSE_SHFT 0x5 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_I_MC5_FUSE_MC4_MODE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_I_MC5_FUSE_MC5_MODE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_I_MC4_FUSE_BMSK 0x10 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_I_MC4_FUSE_SHFT 0x4 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_I_MC4_FUSE_MC4_MODE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_I_MC4_FUSE_MC5_MODE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_PKA_3PIP_DISABLE_BMSK 0x8 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_PKA_3PIP_DISABLE_SHFT 0x3 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_PKA_3PIP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_PKA_3PIP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_UFS_SINGLE_LANE_BMSK 0x4 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_UFS_SINGLE_LANE_SHFT 0x2 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_UFS_SINGLE_LANE_ICE_ENGINE_USES_SW_KEY_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_FUSE_UFS_SINGLE_LANE_ICE_ENGINE_USES_HW_KEY_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_UFS_FUSE_ICE_DISABLE_BMSK 0x2 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_UFS_FUSE_ICE_DISABLE_SHFT 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_UFS_FUSE_ICE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_UFS_FUSE_ICE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_MSMC_NAV_EN_BMSK 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_MSMC_NAV_EN_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_MSMC_NAV_EN_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW2_MSB_MSMC_NAV_EN_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004160) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004160) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004160) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_ADDR) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_7_0_BMSK 0xff000000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_7_0_SHFT 0x18 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_TURING_Q6SS_L2TCM_EN_BMSK 0xf00000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_TURING_Q6SS_L2TCM_EN_SHFT 0x14 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_LEGACY_MBNV6_OVERRIDE_BMSK 0x80000 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_LEGACY_MBNV6_OVERRIDE_SHFT 0x13 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_BMSK 0x7f800 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_SHFT 0xb #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_APC1PLL_LVAL_BMSK 0x7f8 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_APC1PLL_LVAL_SHFT 0x3 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_APSS_KRYO_PP_DISABLE_BMSK 0x4 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_APSS_KRYO_PP_DISABLE_SHFT 0x2 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_L3_SIZE_RED_BMSK 0x2 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_SYS_CFG_L3_SIZE_RED_SHFT 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_LSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004164) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004164) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004164) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_ADDR) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_RSVD_BMSK 0xfffffc00 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_RSVD_SHFT 0xa #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_EN_BMSK 0x200 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_EN_SHFT 0x9 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_EN_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_EN_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_HALF_BMSK 0x100 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_EFUSE_Q6SS_HVX_HALF_SHFT 0x8 #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_TURING_Q6SS_PLL_L_MAX_15_8_BMSK 0xff #define HWIO_QFPROM_CORR_CM_FEATURE_CONFIG_ROW3_MSB_TURING_Q6SS_PLL_L_MAX_15_8_SHFT 0x0 #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004168) #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004168) #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004168) #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_MRC_2_0_BMSK 0xfffffff0 #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_MRC_2_0_SHFT 0x4 #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATIOM_LIST_BMSK 0xf #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_LSB_ROOT_CERT_ACTIVATIOM_LIST_SHFT 0x0 #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000416c) #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000416c) #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000416c) #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_MRC_2_0_BMSK 0xfffffffe #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_MRC_2_0_SHFT 0x1 #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_BMSK 0x1 #define HWIO_QFPROM_CORR_MRC_2_0_ROW0_MSB_CURRENT_UIE_KEY_SEL_SHFT 0x0 #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004170) #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004170) #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004170) #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_MRC_2_0_95_68_BMSK 0xfffffff0 #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_MRC_2_0_95_68_SHFT 0x4 #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_BMSK 0xf #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_LSB_ROOT_CERT_REVOCATION_LIST_SHFT 0x0 #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004174) #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004174) #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004174) #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_MRC_2_0_127_96_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MRC_2_0_ROW1_MSB_MRC_2_0_127_96_SHFT 0x0 #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004178) #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004178) #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004178) #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_SPEED_BIN_BMSK 0xe0000000 #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_SPEED_BIN_SHFT 0x1d #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_MACCHIATO_EN_BMSK 0x10000000 #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_MACCHIATO_EN_SHFT 0x1c #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_FEATURE_ID_BMSK 0xff00000 #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_FEATURE_ID_SHFT 0x14 #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_JTAG_ID_BMSK 0xfffff #define HWIO_QFPROM_CORR_PTE_ROW0_LSB_JTAG_ID_SHFT 0x0 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000417c) #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000417c) #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000417c) #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_LOGIC_RETENTION_BMSK 0xe0000000 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_LOGIC_RETENTION_SHFT 0x1d #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IDDQ_REVISION_CONTROL_BMSK 0x18000000 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IDDQ_REVISION_CONTROL_SHFT 0x1b #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B58_BMSK 0x4000000 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B58_SHFT 0x1a #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B57_BMSK 0x2000000 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B57_SHFT 0x19 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B56_BMSK 0x1000000 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B56_SHFT 0x18 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B55_BMSK 0x800000 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B55_SHFT 0x17 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B54_BMSK 0x400000 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B54_SHFT 0x16 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B53_BMSK 0x200000 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B53_SHFT 0x15 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B52_BMSK 0x100000 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B52_SHFT 0x14 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B51_BMSK 0x80000 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R51_B51_SHFT 0x13 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IDDQ_MX_ACTIVE_BMSK 0x7f800 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IDDQ_MX_ACTIVE_SHFT 0xb #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IDDQ_CX_ACTIVE_BMSK 0x7f8 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IDDQ_CX_ACTIVE_SHFT 0x3 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IDDQ_MULTIPLIER_BMSK 0x6 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_IDDQ_MULTIPLIER_SHFT 0x1 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R38_B32_BMSK 0x1 #define HWIO_QFPROM_CORR_PTE_ROW0_MSB_SPARE_R38_B32_SHFT 0x0 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004180) #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004180) #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004180) #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_IDDQ_MM_ACTIVE_BMSK 0xff000000 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_IDDQ_MM_ACTIVE_SHFT 0x18 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SPARE_R39_B23_BMSK 0x800000 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SPARE_R39_B23_SHFT 0x17 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_PTE2P9GHZ_BMSK 0x400000 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_PTE2P9GHZ_SHFT 0x16 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SUBBINB_BMSK 0x3c0000 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SUBBINB_SHFT 0x12 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SUBBINA_BMSK 0x3c000 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SUBBINA_SHFT 0xe #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_XO_SHUTDOWN_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_XO_SHUTDOWN_DISABLE_SHFT 0xd #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_RETENTION_FAIL_BMSK 0x1000 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_RETENTION_FAIL_SHFT 0xc #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_TURBO_MODE_ONLY_BMSK 0x800 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_TURBO_MODE_ONLY_SHFT 0xb #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SPARE_R39_B10_BMSK 0x400 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SPARE_R39_B10_SHFT 0xa #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SPARE_R39_B9_BMSK 0x200 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SPARE_R39_B9_SHFT 0x9 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_CPU_ACC_BMSK 0x1f0 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_CPU_ACC_SHFT 0x4 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SPARE_R39_B3_BMSK 0x8 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SPARE_R39_B3_SHFT 0x3 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SPARE_R39_B2_BMSK 0x4 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_SPARE_R39_B2_SHFT 0x2 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_MINOR_REV_BMSK 0x3 #define HWIO_QFPROM_CORR_PTE_ROW1_LSB_MINOR_REV_SHFT 0x0 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004184) #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004184) #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004184) #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_DOU_BINNNING_BMSK 0xe0000000 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_DOU_BINNNING_SHFT 0x1d #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_TSENS_REV_CTRL_BMSK 0x10000000 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_TSENS_REV_CTRL_SHFT 0x1c #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_PARTIAL_GOOD_BMSK 0xf800000 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_PARTIAL_GOOD_SHFT 0x17 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B54_BMSK 0x400000 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B54_SHFT 0x16 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B53_BMSK 0x200000 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B53_SHFT 0x15 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B52_BMSK 0x100000 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B52_SHFT 0x14 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B51_BMSK 0x80000 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B51_SHFT 0x13 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B50_BMSK 0x40000 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B50_SHFT 0x12 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B49_BMSK 0x20000 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B49_SHFT 0x11 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B48_BMSK 0x10000 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B48_SHFT 0x10 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B47_BMSK 0x8000 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B47_SHFT 0xf #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_RSBC_WS_MX_BMSK 0x7f00 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_RSBC_WS_MX_SHFT 0x8 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B39_BMSK 0x80 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B39_SHFT 0x7 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_ML_REVISION_BITS_BMSK 0x70 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_ML_REVISION_BITS_SHFT 0x4 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_ML_MODEL_ID_BMSK 0xe #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_ML_MODEL_ID_SHFT 0x1 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B32_BMSK 0x1 #define HWIO_QFPROM_CORR_PTE_ROW1_MSB_SPARE_R39_B32_SHFT 0x0 #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004188) #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004188) #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004188) #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IDDQ_APC1_XP1_BMSK 0xff000000 #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IDDQ_APC1_XP1_SHFT 0x18 #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IDDQ_APC1_MAX_BMSK 0xff0000 #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IDDQ_APC1_MAX_SHFT 0x10 #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IDDQ_APC1_PERIPH_BMSK 0xff00 #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IDDQ_APC1_PERIPH_SHFT 0x8 #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IDDQ_APC0_ACTIVE_BMSK 0xff #define HWIO_QFPROM_CORR_PTE_ROW2_LSB_IDDQ_APC0_ACTIVE_SHFT 0x0 #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000418c) #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000418c) #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000418c) #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_RMSK 0xfffeffff #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IDDQ_APC1_TOTAL_LEAKAGE_6_0_BMSK 0xfe000000 #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IDDQ_APC1_TOTAL_LEAKAGE_6_0_SHFT 0x19 #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IDDQ_GFX_ACTIVE_BMSK 0x1fe0000 #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IDDQ_GFX_ACTIVE_SHFT 0x11 #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IDDQ_APC1_XP3_BMSK 0xff00 #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IDDQ_APC1_XP3_SHFT 0x8 #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IDDQ_APC1_XP2_BMSK 0xff #define HWIO_QFPROM_CORR_PTE_ROW2_MSB_IDDQ_APC1_XP2_SHFT 0x0 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004190) #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004190) #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004190) #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR) #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_DIE_X_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_DIE_X_3_0_SHFT 0x1c #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_DIE_Y_BMSK 0xff00000 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_DIE_Y_SHFT 0x14 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_MEM_RETENTION_BMSK 0xe0000 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_MEM_RETENTION_SHFT 0x11 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IDDQ_MX_OFF_BMSK 0x1f800 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IDDQ_MX_OFF_SHFT 0xb #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IDDQ_CX_OFF_BMSK 0x7e0 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IDDQ_CX_OFF_SHFT 0x5 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IDDQ_APC1_IOP_WORST_CORE_ID_BMSK 0x18 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IDDQ_APC1_IOP_WORST_CORE_ID_SHFT 0x3 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IDDQ_APC1_TOTAL_LEAKAGE_9_7_BMSK 0x7 #define HWIO_QFPROM_CORR_PTE_ROW3_LSB_IDDQ_APC1_TOTAL_LEAKAGE_9_7_SHFT 0x0 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004194) #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004194) #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004194) #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR) #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_SP_PARTIAL_BMSK 0x80000000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_SP_PARTIAL_SHFT 0x1f #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_SP_BLANK_BMSK 0x40000000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_SP_BLANK_SHFT 0x1e #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_SPARE_R41_B61_BMSK 0x20000000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_SPARE_R41_B61_SHFT 0x1d #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_SPARE_R41_B60_BMSK 0x10000000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_SPARE_R41_B60_SHFT 0x1c #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_WS_PWR_WA_BMSK 0x8000000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_WS_PWR_WA_SHFT 0x1b #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_WS_PERF_WA_BMSK 0x4000000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_WS_PERF_WA_SHFT 0x1a #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_BONE_PILE_BMSK 0x3000000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_BONE_PILE_SHFT 0x18 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_WS_CPR_MX_TUR_VBUMP_BMSK 0x800000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_WS_CPR_MX_TUR_VBUMP_SHFT 0x17 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_DVS_REV_BMSK 0x600000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_DVS_REV_SHFT 0x15 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_WS_2ND_INSERTION_BMSK 0x100000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_WS_2ND_INSERTION_SHFT 0x14 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_MINSVS_FAIL_BMSK 0x80000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_MINSVS_FAIL_SHFT 0x13 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_DVS_PREVIOUSLY_RUN_BMSK 0x40000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_DVS_PREVIOUSLY_RUN_SHFT 0x12 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_APC1_WC_ID_BMSK 0x30000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_APC1_WC_ID_SHFT 0x10 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_ROW_IDENTIFIER_BMSK 0x8000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_ROW_IDENTIFIER_SHFT 0xf #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_SPARE_R41_B46_BMSK 0x4000 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_SPARE_R41_B46_SHFT 0xe #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_CPU_VMIN_CORR_BMSK 0x3e00 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_CPU_VMIN_CORR_SHFT 0x9 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_WAFER_ID_BMSK 0x1f0 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_WAFER_ID_SHFT 0x4 #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_DIE_X_7_4_BMSK 0xf #define HWIO_QFPROM_CORR_PTE_ROW3_MSB_DIE_X_7_4_SHFT 0x0 #define HWIO_QFPROM_CORR_PTE_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004198) #define HWIO_QFPROM_CORR_PTE_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004198) #define HWIO_QFPROM_CORR_PTE_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004198) #define HWIO_QFPROM_CORR_PTE_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PTE_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PTE_ROW4_LSB_ADDR) #define HWIO_QFPROM_CORR_PTE_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PTE_ROW4_LSB_PTE_DATA0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PTE_ROW4_LSB_PTE_DATA0_SHFT 0x0 #define HWIO_QFPROM_CORR_PTE_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000419c) #define HWIO_QFPROM_CORR_PTE_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000419c) #define HWIO_QFPROM_CORR_PTE_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000419c) #define HWIO_QFPROM_CORR_PTE_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PTE_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PTE_ROW4_MSB_ADDR) #define HWIO_QFPROM_CORR_PTE_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PTE_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PTE_ROW4_MSB_PTE_DATA1_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PTE_ROW4_MSB_PTE_DATA1_SHFT 0x0 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041a0) #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041a0) #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041a0) #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_IN \ in_dword(HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ADDR) #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ADDR, m) #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_SPARE_31_READ_DISABLE_BMSK 0x80000000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_SPARE_31_READ_DISABLE_SHFT 0x1f #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_SPARE_30_READ_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_SPARE_30_READ_DISABLE_SHFT 0x1e #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_SPARE_29_READ_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_SPARE_29_READ_DISABLE_SHFT 0x1d #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_SPARE_28_READ_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_SPARE_28_READ_DISABLE_SHFT 0x1c #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_USER_KEY_DERIVATION_KEY_READ_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_USER_KEY_DERIVATION_KEY_READ_DISABLE_SHFT 0x1b #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_READ_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_READ_DISABLE_SHFT 0x1a #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_BOOT_ROM_PATCH_READ_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_BOOT_ROM_PATCH_READ_DISABLE_SHFT 0x19 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_READ_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_READ_DISABLE_SHFT 0x18 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_SECURE_BOOT_READ_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_SECURE_BOOT_READ_DISABLE_SHFT 0x17 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_READ_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_READ_DISABLE_SHFT 0x16 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_QC_SPARE_21_READ_DISABLE_BMSK 0x200000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_QC_SPARE_21_READ_DISABLE_SHFT 0x15 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_QC_SPARE_20_READ_DISABLE_BMSK 0x100000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_QC_SPARE_20_READ_DISABLE_SHFT 0x14 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_MEMORY_CONFIGURATION_READ_DISABLE_BMSK 0x80000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_MEMORY_CONFIGURATION_READ_DISABLE_SHFT 0x13 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_CALIBRATION_READ_DISABLE_BMSK 0x40000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_CALIBRATION_READ_DISABLE_SHFT 0x12 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_READ_DISABLE_BMSK 0x20000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_READ_DISABLE_SHFT 0x11 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_5_READ_DISABLE_BMSK 0x10000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_5_READ_DISABLE_SHFT 0x10 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_4_READ_DISABLE_BMSK 0x8000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_4_READ_DISABLE_SHFT 0xf #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_3_READ_DISABLE_BMSK 0x4000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_3_READ_DISABLE_SHFT 0xe #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_2_READ_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_2_READ_DISABLE_SHFT 0xd #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_1_READ_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_ANTI_ROLLBACK_1_READ_DISABLE_SHFT 0xc #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_READ_DISABLE_BMSK 0x800 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_READ_DISABLE_SHFT 0xb #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_READ_DISABLE_BMSK 0x400 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_READ_DISABLE_SHFT 0xa #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_CONFIGURATION_READ_DISABLE_BMSK 0x200 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_OEM_CONFIGURATION_READ_DISABLE_SHFT 0x9 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_FEC_ENABLES_READ_DISABLE_BMSK 0x100 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_FEC_ENABLES_READ_DISABLE_SHFT 0x8 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_WRITE_PERMISSION_READ_DISABLE_BMSK 0x80 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_WRITE_PERMISSION_READ_DISABLE_SHFT 0x7 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_READ_PERMISSION_READ_DISABLE_BMSK 0x40 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_READ_PERMISSION_READ_DISABLE_SHFT 0x6 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_PTE_READ_DISABLE_BMSK 0x20 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_PTE_READ_DISABLE_SHFT 0x5 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_MRC_READ_DISABLE_BMSK 0x10 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_MRC_READ_DISABLE_SHFT 0x4 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_READ_DISABLE_BMSK 0x8 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_READ_DISABLE_SHFT 0x3 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_READ_DISABLE_BMSK 0x4 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_READ_DISABLE_SHFT 0x2 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_LCM_READ_DISABLE_BMSK 0x2 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_LCM_READ_DISABLE_SHFT 0x1 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_CM_PRIVATE_READ_DISABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_LSB_CM_PRIVATE_READ_DISABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_READ_PERMISSIONS_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041a4) #define HWIO_QFPROM_CORR_READ_PERMISSIONS_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041a4) #define HWIO_QFPROM_CORR_READ_PERMISSIONS_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041a4) #define HWIO_QFPROM_CORR_READ_PERMISSIONS_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_READ_PERMISSIONS_MSB_IN \ in_dword(HWIO_QFPROM_CORR_READ_PERMISSIONS_MSB_ADDR) #define HWIO_QFPROM_CORR_READ_PERMISSIONS_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_READ_PERMISSIONS_MSB_ADDR, m) #define HWIO_QFPROM_CORR_READ_PERMISSIONS_MSB_RSVD0_54_BMSK 0xffffffff #define HWIO_QFPROM_CORR_READ_PERMISSIONS_MSB_RSVD0_54_SHFT 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041a8) #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041a8) #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041a8) #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_IN \ in_dword(HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ADDR) #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ADDR, m) #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_31_WRITE_DISABLE_BMSK 0x80000000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_31_WRITE_DISABLE_SHFT 0x1f #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_30_WRITE_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_30_WRITE_DISABLE_SHFT 0x1e #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_30_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_30_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_29_WRITE_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_29_WRITE_DISABLE_SHFT 0x1d #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_29_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_29_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_28_WRITE_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_28_WRITE_DISABLE_SHFT 0x1c #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_28_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SPARE_28_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_USER_KEY_DERIVATIONKEY_WRITE_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_USER_KEY_DERIVATIONKEY_WRITE_DISABLE_SHFT 0x1b #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_USER_KEY_DERIVATIONKEY_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_USER_KEY_DERIVATIONKEY_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_WRITE_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_WRITE_DISABLE_SHFT 0x1a #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_IMAGE_ENCRYPTION_KEY_1_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_BOOT_ROM_PATCH_WRITE_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_BOOT_ROM_PATCH_WRITE_DISABLE_SHFT 0x19 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_BOOT_ROM_PATCH_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_BOOT_ROM_PATCH_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_WRITE_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_WRITE_DISABLE_SHFT 0x18 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_SECONDARY_KEY_DERIVATION_KEY_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SECURE_BOOT_WRITE_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SECURE_BOOT_WRITE_DISABLE_SHFT 0x17 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SECURE_BOOT_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_SECURE_BOOT_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_WRITE_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_WRITE_DISABLE_SHFT 0x16 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_IMAGE_ENCRYPTION_KEY_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_QC_SPARE_21_WRITE_DISABLE_BMSK 0x200000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_QC_SPARE_21_WRITE_DISABLE_SHFT 0x15 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_QC_SPARE_21_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_QC_SPARE_21_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_QC_SPARE_20_WRITE_DISABLE_BMSK 0x100000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_QC_SPARE_20_WRITE_DISABLE_SHFT 0x14 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_QC_SPARE_20_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_QC_SPARE_20_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_MEMORY_CONFIGURATION_WRITE_DISABLE_BMSK 0x80000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_MEMORY_CONFIGURATION_WRITE_DISABLE_SHFT 0x13 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_MEMORY_CONFIGURATION_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_MEMORY_CONFIGURATION_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CALIBRATION_WRITE_DISABLE_BMSK 0x40000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CALIBRATION_WRITE_DISABLE_SHFT 0x12 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CALIBRATION_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CALIBRATION_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_WRITE_DISABLE_BMSK 0x20000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_WRITE_DISABLE_SHFT 0x11 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PUBLIC_KEY_HASH_0_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_5_WRITE_DISABLE_BMSK 0x10000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_5_WRITE_DISABLE_SHFT 0x10 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_5_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_5_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_4_WRITE_DISABLE_BMSK 0x8000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_4_WRITE_DISABLE_SHFT 0xf #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_4_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_4_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_3_WRITE_DISABLE_BMSK 0x4000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_3_WRITE_DISABLE_SHFT 0xe #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_3_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_3_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_2_WRITE_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_2_WRITE_DISABLE_SHFT 0xd #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_2_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_2_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_1_WRITE_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_1_WRITE_DISABLE_SHFT 0xc #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_1_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_ANTI_ROLLBACK_1_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_WRITE_DISABLE_BMSK 0x800 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_WRITE_DISABLE_SHFT 0xb #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_NM_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_WRITE_DISABLE_BMSK 0x400 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_WRITE_DISABLE_SHFT 0xa #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEATURE_CONFIGURATION_M_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_CONFIGURATION_WRITE_DISABLE_BMSK 0x200 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_CONFIGURATION_WRITE_DISABLE_SHFT 0x9 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_CONFIGURATION_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_OEM_CONFIGURATION_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEC_ENABLES_WRITE_DISABLE_BMSK 0x100 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEC_ENABLES_WRITE_DISABLE_SHFT 0x8 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEC_ENABLES_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_FEC_ENABLES_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_WRITE_PERMISSIONS_WRITE_DISABLE_BMSK 0x80 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_WRITE_PERMISSIONS_WRITE_DISABLE_SHFT 0x7 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_WRITE_PERMISSIONS_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_WRITE_PERMISSIONS_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_READ_PERMISSIONS_WRITE_DISABLE_BMSK 0x40 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_READ_PERMISSIONS_WRITE_DISABLE_SHFT 0x6 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_READ_PERMISSIONS_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_READ_PERMISSIONS_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PTE_WRITE_DISABLE_BMSK 0x20 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PTE_WRITE_DISABLE_SHFT 0x5 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PTE_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PTE_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_MRC_2_0_WRITE_DISABLE_BMSK 0x10 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_MRC_2_0_WRITE_DISABLE_SHFT 0x4 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_MRC_2_0_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_MRC_2_0_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_WRITE_DISABLE_BMSK 0x8 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_WRITE_DISABLE_SHFT 0x3 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CM_FEATURE_CONFIGURATION_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_WRITE_DISABLE_BMSK 0x4 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_WRITE_DISABLE_SHFT 0x2 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_PRIMARY_KEY_DERIVATION_KEY_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_LCM_WRITE_DISABLE_BMSK 0x2 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_LCM_WRITE_DISABLE_SHFT 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_LCM_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_LCM_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CM_PRIVATE_WRITE_DISABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CM_PRIVATE_WRITE_DISABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CM_PRIVATE_WRITE_DISABLE_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_LSB_CM_PRIVATE_WRITE_DISABLE_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041ac) #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041ac) #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041ac) #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_MSB_IN \ in_dword(HWIO_QFPROM_CORR_WRITE_PERMISSIONS_MSB_ADDR) #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_WRITE_PERMISSIONS_MSB_ADDR, m) #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_MSB_RSVD0_55_BMSK 0xffffffff #define HWIO_QFPROM_CORR_WRITE_PERMISSIONS_MSB_RSVD0_55_SHFT 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041b0) #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041b0) #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041b0) #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_IN \ in_dword(HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ADDR) #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ADDR, m) #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_31_FEC_ENABLE_BMSK 0x80000000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_31_FEC_ENABLE_SHFT 0x1f #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_30_FEC_ENABLE_BMSK 0x40000000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_30_FEC_ENABLE_SHFT 0x1e #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_30_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_30_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_29_FEC_ENABLE_BMSK 0x20000000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_29_FEC_ENABLE_SHFT 0x1d #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_29_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_29_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_28_FEC_ENABLE_BMSK 0x10000000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_28_FEC_ENABLE_SHFT 0x1c #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_28_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SPARE_28_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_USER_KEY_DERIVATION_KEY_FEC_ENABLE_BMSK 0x8000000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_USER_KEY_DERIVATION_KEY_FEC_ENABLE_SHFT 0x1b #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_USER_KEY_DERIVATION_KEY_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_USER_KEY_DERIVATION_KEY_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_IMAGE_ENCRYPTION_KEY_1_FEC_ENABLE_BMSK 0x4000000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_IMAGE_ENCRYPTION_KEY_1_FEC_ENABLE_SHFT 0x1a #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_IMAGE_ENCRYPTION_KEY_1_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_IMAGE_ENCRYPTION_KEY_1_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_BOOT_ROM_PATCH_FEC_ENABLE_BMSK 0x2000000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_BOOT_ROM_PATCH_FEC_ENABLE_SHFT 0x19 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_BOOT_ROM_PATCH_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_BOOT_ROM_PATCH_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_SECONDARY_KEY_DERIVATION_KEY_FEC_ENABLE_BMSK 0x1000000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_SECONDARY_KEY_DERIVATION_KEY_FEC_ENABLE_SHFT 0x18 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_SECONDARY_KEY_DERIVATION_KEY_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_SECONDARY_KEY_DERIVATION_KEY_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SECURE_BOOT_FEC_ENABLE_BMSK 0x800000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SECURE_BOOT_FEC_ENABLE_SHFT 0x17 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SECURE_BOOT_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_SECURE_BOOT_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_IMAGE_ENCRYPTION_KEY_FEC_ENABLE_BMSK 0x400000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_IMAGE_ENCRYPTION_KEY_FEC_ENABLE_SHFT 0x16 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_IMAGE_ENCRYPTION_KEY_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_IMAGE_ENCRYPTION_KEY_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_QC_SPARE_21_FEC_ENABLE_BMSK 0x200000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_QC_SPARE_21_FEC_ENABLE_SHFT 0x15 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_QC_SPARE_21_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_QC_SPARE_21_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_QC_SPARE_20_FEC_ENABLE_BMSK 0x100000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_QC_SPARE_20_FEC_ENABLE_SHFT 0x14 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_QC_SPARE_20_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_QC_SPARE_20_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_MEMORY_CONFIGURATION_FEC_ENABLE_BMSK 0x80000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_MEMORY_CONFIGURATION_FEC_ENABLE_SHFT 0x13 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_MEMORY_CONFIGURATION_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_MEMORY_CONFIGURATION_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CALIBRATION_FEC_ENABLE_BMSK 0x40000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CALIBRATION_FEC_ENABLE_SHFT 0x12 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CALIBRATION_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CALIBRATION_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PUBLIC_KEY_HASH_0_FEC_ENABLE_BMSK 0x20000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PUBLIC_KEY_HASH_0_FEC_ENABLE_SHFT 0x11 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PUBLIC_KEY_HASH_0_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PUBLIC_KEY_HASH_0_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_5_FEC_ENABLE_BMSK 0x10000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_5_FEC_ENABLE_SHFT 0x10 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_5_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_5_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_4_FEC_ENABLE_BMSK 0x8000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_4_FEC_ENABLE_SHFT 0xf #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_4_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_4_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_3_FEC_ENABLE_BMSK 0x4000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_3_FEC_ENABLE_SHFT 0xe #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_3_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_3_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_2_FEC_ENABLE_BMSK 0x2000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_2_FEC_ENABLE_SHFT 0xd #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_2_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_2_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_1_FEC_ENABLE_BMSK 0x1000 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_1_FEC_ENABLE_SHFT 0xc #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_1_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_ANTI_ROLLBACK_1_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_NM_FEC_ENABLE_BMSK 0x800 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_NM_FEC_ENABLE_SHFT 0xb #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_NM_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_NM_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_M_FEC_ENABLE_BMSK 0x400 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_M_FEC_ENABLE_SHFT 0xa #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_M_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEATURE_CONFIGURATION_M_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_CONFIGURATION_FEC_ENABLE_BMSK 0x200 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_CONFIGURATION_FEC_ENABLE_SHFT 0x9 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_CONFIGURATION_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_OEM_CONFIGURATION_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEC_ENABLES_FEC_ENABLE_BMSK 0x100 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEC_ENABLES_FEC_ENABLE_SHFT 0x8 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEC_ENABLES_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_FEC_ENABLES_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_WRITE_PERMISSIONS_FEC_ENABLE_BMSK 0x80 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_WRITE_PERMISSIONS_FEC_ENABLE_SHFT 0x7 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_WRITE_PERMISSIONS_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_WRITE_PERMISSIONS_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_READ_PERMISSIONS_FEC_ENABLE_BMSK 0x40 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_READ_PERMISSIONS_FEC_ENABLE_SHFT 0x6 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_READ_PERMISSIONS_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_READ_PERMISSIONS_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PTE_FEC_ENABLE_BMSK 0x20 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PTE_FEC_ENABLE_SHFT 0x5 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PTE_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PTE_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_MRC_2_0_FEC_ENABLE_BMSK 0x10 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_MRC_2_0_FEC_ENABLE_SHFT 0x4 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_MRC_2_0_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_MRC_2_0_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CM_FEATURE_CONFIGURATION_FEC_ENABLE_BMSK 0x8 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CM_FEATURE_CONFIGURATION_FEC_ENABLE_SHFT 0x3 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CM_FEATURE_CONFIGURATION_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CM_FEATURE_CONFIGURATION_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PRIMARY_KEY_DERIVATION_KEY_FEC_ENABLE_BMSK 0x4 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PRIMARY_KEY_DERIVATION_KEY_FEC_ENABLE_SHFT 0x2 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PRIMARY_KEY_DERIVATION_KEY_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_PRIMARY_KEY_DERIVATION_KEY_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_LCM_FEC_ENABLE_BMSK 0x2 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_LCM_FEC_ENABLE_SHFT 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_LCM_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_LCM_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CM_PRIVATE_FEC_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CM_PRIVATE_FEC_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CM_PRIVATE_FEC_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEC_ENABLES_LSB_CM_PRIVATE_FEC_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEC_ENABLES_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041b4) #define HWIO_QFPROM_CORR_FEC_ENABLES_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041b4) #define HWIO_QFPROM_CORR_FEC_ENABLES_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041b4) #define HWIO_QFPROM_CORR_FEC_ENABLES_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEC_ENABLES_MSB_IN \ in_dword(HWIO_QFPROM_CORR_FEC_ENABLES_MSB_ADDR) #define HWIO_QFPROM_CORR_FEC_ENABLES_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEC_ENABLES_MSB_ADDR, m) #define HWIO_QFPROM_CORR_FEC_ENABLES_MSB_RSVD0_56_BMSK 0xffffffff #define HWIO_QFPROM_CORR_FEC_ENABLES_MSB_RSVD0_56_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041b8) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041b8) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041b8) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_BMSK 0x80000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_SHFT 0x1f #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_SHFT 0x1e #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_SHFT 0x1d #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ALL_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_SHFT 0x1c #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_POLICY_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_SHFT 0x1b #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_SHFT 0x1a #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_UDK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_BMSK 0x2000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DEBUG_DISABLE_IN_ROM_SHFT 0x19 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK 0x1000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT 0x18 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_MSS_HASH_INTEGRITY_CHECK_ENABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_SHFT 0x17 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_APPS_HASH_INTEGRITY_CHECK_DISABLE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_SHFT 0x16 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_USB_SS_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_BMSK 0x200000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_SHFT 0x15 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_USE_OEM_ID_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_ROT_USE_SERIAL_NUM_USE_SERIAL_NUM_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_BMSK 0x100000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_SHFT 0x14 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_DISABLE_ROT_TRANSFER_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_BMSK 0x80000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_IMAGE_ENCRYPTION_ENABLE_SHFT 0x13 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_BMSK 0x60000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ROOT_CERT_TOTAL_NUM_SHFT 0x11 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_BMSK 0x10000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_USB_TYPE_C_DISABLE_SHFT 0x10 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_BMSK 0x8000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_LOG_DISABLE_SHFT 0xf #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_BMSK 0x4000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_SHFT 0xe #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_USE_GPIO_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_WDOG_EN_IGNORE_GPIO_ENABLE_WDOG_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE__BMSK 0x2000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE__SHFT 0xd #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE__DISABLE_EDL_RESET_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE__ENABLE_EDL_RESET_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SW_FUSE_PROG_DISABLE_SHFT 0xc #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_BMSK 0x800 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SPI_CLK_BOOT_FREQ_SHFT 0xb #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_BMSK 0x400 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_SHFT 0xa #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_SD_USB_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_PBL_QSPI_BOOT_EDL_ENABLED_QSPI_SD_USB_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_BMSK 0x3e0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SHFT 0x5 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_DEFAULT_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SD_UFS_EDL_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SD_EDL_FVAL 0x2 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_USB_EDL_FVAL 0x3 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_QSPI_EDL_FVAL 0x4 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_SPI_EDL_FVAL 0x5 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FAST_BOOT_UGSG4_SD_USB_EDL_FVAL 0x8 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_ADMA_DISABLE_BMSK 0x10 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_ADMA_DISABLE_SHFT 0x4 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_ADMA_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_SDCC_ADMA_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_BMSK 0x8 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_SHFT 0x3 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_USB_BOOT_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_BMSK 0x4 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_SHFT 0x2 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_FORCE_DLOAD_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_BMSK 0x2 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_SHFT 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_TIMEOUT_DISABLED_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_ENUM_TIMEOUT_TIMEOUT_ENABLED_90S_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_DOWNLOADER_ENABLED_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_LSB_E_DLOAD_DISABLE_DOWNLOADER_DISABLED_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041bc) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041bc) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041bc) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RSVD_BMSK 0xffffc000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_RSVD_SHFT 0xe #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_SHFT 0xd #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_SHFT 0xc #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_BMSK 0x800 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_SHFT 0xb #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_BMSK 0x400 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_SHFT 0xa #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_BMSK 0x200 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_SHFT 0x9 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_BMSK 0x100 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_SHFT 0x8 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_BMSK 0x80 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_SHFT 0x7 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_BMSK 0x40 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_SHFT 0x6 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_APPS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_BMSK 0x20 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_SHFT 0x5 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_BMSK 0x10 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_SHFT 0x4 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_BMSK 0x8 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_SHFT 0x3 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_BMSK 0x4 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_SHFT 0x2 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_BMSK 0x2 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_SHFT 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW0_MSB_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041c0) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041c0) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041c0) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RMSK 0xfffff7fe #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_BMSK 0x80000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_DISABLE_RSA_SHFT 0x1f #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_BMSK 0x40000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_EKU_ENFORCEMENT_EN_SHFT 0x1e #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_29_BMSK 0x20000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_29_SHFT 0x1d #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_28_BMSK 0x10000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_28_SHFT 0x1c #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_27_BMSK 0x8000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_27_SHFT 0x1b #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_26_BMSK 0x4000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_26_SHFT 0x1a #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_25_BMSK 0x2000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_25_SHFT 0x19 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_24_BMSK 0x1000000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_24_SHFT 0x18 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_23_BMSK 0x800000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_23_SHFT 0x17 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_22_BMSK 0x400000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_22_SHFT 0x16 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_21_BMSK 0x200000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_21_SHFT 0x15 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_20_BMSK 0x100000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_20_SHFT 0x14 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_19_BMSK 0x80000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_19_SHFT 0x13 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_18_BMSK 0x40000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_18_SHFT 0x12 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_17_BMSK 0x20000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_17_SHFT 0x11 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_16_BMSK 0x10000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD1_50_16_SHFT 0x10 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_BMSK 0x8000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_SHFT 0xf #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG31_SECURE_SECURE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_BMSK 0x4000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_SHFT 0xe #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG30_SECURE_SECURE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_BMSK 0x2000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_SHFT 0xd #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG29_SECURE_SECURE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_BMSK 0x1000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_SHFT 0xc #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPARE_REG28_SECURE_SECURE_FVAL 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPU_IAR_ENABLED_BMSK 0x400 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SPU_IAR_ENABLED_SHFT 0xa #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD0_50_9_BMSK 0x200 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD0_50_9_SHFT 0x9 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD0_50_8_BMSK 0x100 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_RSVD0_50_8_SHFT 0x8 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_BMSK 0x80 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_OVERRIDE_SHFT 0x7 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_BMSK 0x40 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_OVERRIDE_SHFT 0x6 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_BMSK 0x20 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_MODEM_CRYPTO_FIPS_ENABLE_SHFT 0x5 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_BMSK 0x10 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_TZ_SW_CRYPTO_FIPS_ENABLE_SHFT 0x4 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_BMSK 0x8 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_FIPS_ENABLE_SHFT 0x3 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_BMSK 0x6 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_LSB_SP_NVM_AR_CONFIG_SHFT 0x1 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041c4) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041c4) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041c4) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_BMSK 0xffff0000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_PRODUCT_ID_SHFT 0x10 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_BMSK 0xffff #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW1_MSB_OEM_HW_ID_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041c8) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041c8) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041c8) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_VID_BMSK 0xffff0000 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_VID_SHFT 0x10 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_PID_BMSK 0xffff #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_LSB_PERIPH_PID_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041cc) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041cc) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041cc) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RSVD_BMSK 0xffffff00 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_RSVD_SHFT 0x8 #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_BMSK 0xff #define HWIO_QFPROM_CORR_OEM_CONFIG_ROW2_MSB_ANTI_ROLLBACK_FEATURE_EN_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041d0) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041d0) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041d0) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_BMSK 0xffff8000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_SHFT 0xf #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_HARD_16_0_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_BMSK 0x7fff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_LSB_MODEM_FEATURE_DISABLE_SPARE_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041d4) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041d4) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041d4) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_BMSK 0xffffff00 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_SHFT 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_SOFT_1_23_0_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_BMSK 0xff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW0_MSB_MODEM_FEATURE_DISABLE_HARD_24_17_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041d8) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041d8) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041d8) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_BMSK 0xffffff00 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_SHFT 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_2_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_BMSK 0xff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_LSB_MODEM_FEATURE_DISABLE_SOFT_1_31_24_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041dc) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041dc) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041dc) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_MDSS_RESOLUTION_LIMIT_BMSK 0xc0000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_MDSS_RESOLUTION_LIMIT_SHFT 0x1e #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DP_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DP_DISABLE_SHFT 0x1d #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_HDCP_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_HDCP_DISABLE_SHFT 0x1c #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_HDCP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_HDCP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_MDP_APICAL_LTC_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_MDP_APICAL_LTC_DISABLE_SHFT 0x1b #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_MDP_APICAL_LTC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_MDP_APICAL_LTC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT 0x1a #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DSI_1_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DSI_1_DISABLE_SHFT 0x19 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DSI_1_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DSI_1_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DSI_0_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DSI_0_DISABLE_SHFT 0x18 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DSI_0_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_DSI_0_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_BMSK 0xffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW1_MSB_MODEM_FEATURE_DISABLE_SOFT_3_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041e0) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041e0) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041e0) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_MOCHA_PART_BMSK 0x80000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_MOCHA_PART_SHFT 0x1f #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_QC_SP_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_QC_SP_DISABLE_SHFT 0x1e #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_QC_SP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_QC_SP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SMMU_DISABLE_BMSK 0x20000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SMMU_DISABLE_SHFT 0x1d #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SMMU_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SMMU_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_DISABLE_SEC_BOOT_GPIO_BMSK 0x10000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_DISABLE_SEC_BOOT_GPIO_SHFT 0x1c #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_QC_UDK_DISABLE_BMSK 0x8000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_QC_UDK_DISABLE_SHFT 0x1b #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_QC_UDK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_QC_UDK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_SHFT 0x1a #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_CM_FEAT_CONFIG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_PCIE_1_DISABLE_BMSK 0x2000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_PCIE_1_DISABLE_SHFT 0x19 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_PCIE_1_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_PCIE_1_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_PCIE_0_DISABLE_BMSK 0x1000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_PCIE_0_DISABLE_SHFT 0x18 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_PCIE_0_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_PCIE_0_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_DISABLE_SHFT 0x17 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT 0x16 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_ISLAND_MODE_Q6_CLK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_BMSK 0x200000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_SHFT 0x15 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SSC_SW_ISLAND_MODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_GFX3D_FREQ_LIMIT_VAL_BMSK 0x1fe000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_GFX3D_FREQ_LIMIT_VAL_SHFT 0xd #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_SHFT 0xc #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_MULTIPIPE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_BMSK 0x800 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_SHFT 0xb #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_ENCODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_BMSK 0x400 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_SHFT 0xa #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_HEVC_DECODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_4K_DISABLE_BMSK 0x200 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_4K_DISABLE_SHFT 0x9 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_4K_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_4K_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_CVP_DISABLE_BMSK 0x100 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_CVP_DISABLE_SHFT 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_CVP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_CVP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_DISABLE_VPX_BMSK 0x80 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_DISABLE_VPX_SHFT 0x7 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_DISABLE_VPX_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_IRIS_DISABLE_VPX_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_BMSK 0x40 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_SHFT 0x6 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_EFUSE_CAM_SBI_DISABLE_IF_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_EUD_PORT1_SEL_BMSK 0x20 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_EUD_PORT1_SEL_SHFT 0x5 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_EUD_PORT1_SEL_USB_PORT0_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_EUD_PORT1_SEL_USB_PORT1_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_EUD_IGNR_CSR_BMSK 0x10 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_EUD_IGNR_CSR_SHFT 0x4 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_MDSS_Q_CONFIG_FUSE_BMSK 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_MDSS_Q_CONFIG_FUSE_SHFT 0x3 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_MDSS_Q_CONFIG_FUSE_HANA_FEAT_SET_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_MDSS_Q_CONFIG_FUSE_HANAQ_FEAT_SET_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SPR_DISABLE_BMSK 0x4 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_SPR_DISABLE_SHFT 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_DEMURA_DISABLE_BMSK 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_DEMURA_DISABLE_SHFT 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_MST_DISABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_LSB_MST_DISABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041e4) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041e4) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041e4) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_APPS_BOOT_FSM_FUSE_BMSK 0xfc000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_APPS_BOOT_FSM_FUSE_SHFT 0x1a #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_BMSK 0x2000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_SYS_APCSCFGAPMBOOTONMX_SHFT 0x19 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_BMSK 0x1fe0000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_SYS_APCCCFGCPUPRESENT_N_SHFT 0x11 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_APSS_PDXWRPNTRDELAY_BMSK 0x18000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_APSS_PDXWRPNTRDELAY_SHFT 0xf #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_GATE_SRST_FUSE_BMSK 0x4000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_GATE_SRST_FUSE_SHFT 0xe #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_GATE_SRST_FUSE_UNGATED_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_GATE_SRST_FUSE_GATED_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK 0x2000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT 0xd #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_MOBILE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_FUNCTIONAL_AUTOMOTIVE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_POWER_BMSK 0x1000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_POWER_SHFT 0xc #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_POWER_MOBILE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_AUTOMOTIVE_BIT_POWER_AUTOMOTIVE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_EMAC_DISABLE_BMSK 0x800 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_EMAC_DISABLE_SHFT 0xb #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_EMAC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_EMAC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_BMSK 0x400 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_SHFT 0xa #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_MODEM_TCM_BOOT_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_NAV_EFUSE_DISABLE_BMSK 0x200 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_NAV_EFUSE_DISABLE_SHFT 0x9 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_NAV_EFUSE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_NAV_EFUSE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_FUSE_CORTEX_M3_DISABLE_BMSK 0x100 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_FUSE_CORTEX_M3_DISABLE_SHFT 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_APS_RESET_DISABLE_BMSK 0x80 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_APS_RESET_DISABLE_SHFT 0x7 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_DOLBY_BIT_BMSK 0x40 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_DOLBY_BIT_SHFT 0x6 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_I_MC5_FUSE_BMSK 0x20 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_I_MC5_FUSE_SHFT 0x5 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_I_MC5_FUSE_MC4_MODE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_I_MC5_FUSE_MC5_MODE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_I_MC4_FUSE_BMSK 0x10 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_I_MC4_FUSE_SHFT 0x4 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_I_MC4_FUSE_MC4_MODE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_I_MC4_FUSE_MC5_MODE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_PKA_3PIP_DISABLE_BMSK 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_PKA_3PIP_DISABLE_SHFT 0x3 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_PKA_3PIP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_PKA_3PIP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_FUSE_UFS_SINGLE_LANE_BMSK 0x4 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_FUSE_UFS_SINGLE_LANE_SHFT 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_FUSE_UFS_SINGLE_LANE_ICE_ENGINE_USES_SW_KEY_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_FUSE_UFS_SINGLE_LANE_ICE_ENGINE_USES_HW_KEY_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_UFS_FUSE_ICE_DISABLE_BMSK 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_UFS_FUSE_ICE_DISABLE_SHFT 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_UFS_FUSE_ICE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_UFS_FUSE_ICE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_MSMC_NAV_EN_BMSK 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_MSMC_NAV_EN_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_MSMC_NAV_EN_DISABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW2_MSB_MSMC_NAV_EN_ENABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041e8) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041e8) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041e8) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_7_0_BMSK 0xff000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_TURING_Q6SS_PLL_L_MAX_7_0_SHFT 0x18 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_TURING_Q6SS_L2TCM_EN_BMSK 0xf00000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_TURING_Q6SS_L2TCM_EN_SHFT 0x14 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_LEGACY_MBNV6_OVERRIDE_BMSK 0x80000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_LEGACY_MBNV6_OVERRIDE_SHFT 0x13 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_BMSK 0x7f800 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_GOLDPLUS_PLL_LVAL_SHFT 0xb #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_APC1PLL_LVAL_BMSK 0x7f8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_APC1PLL_LVAL_SHFT 0x3 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_APSS_KRYO_PP_DISABLE_BMSK 0x4 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_APSS_KRYO_PP_DISABLE_SHFT 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_L3_SIZE_RED_BMSK 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_SYS_CFG_L3_SIZE_RED_SHFT 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_AUTO_CCI_RCG_CFG_DISABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_LSB_AUTO_CCI_RCG_CFG_DISABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041ec) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041ec) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041ec) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_RSVD_BMSK 0xfffffc00 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_RSVD_SHFT 0xa #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_EN_BMSK 0x200 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_EN_SHFT 0x9 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_EN_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_EN_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_HALF_BMSK 0x100 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_EFUSE_Q6SS_HVX_HALF_SHFT 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_TURING_Q6SS_PLL_L_MAX_15_8_BMSK 0xff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_M_ROW3_MSB_TURING_Q6SS_PLL_L_MAX_15_8_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041f0) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041f0) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041f0) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_RMSK 0xfeffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_SM_BIST_DISABLE_BMSK 0x80000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_SM_BIST_DISABLE_SHFT 0x1f #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_SM_BIST_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_SM_BIST_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_TIC_DISABLE_BMSK 0x40000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_TIC_DISABLE_SHFT 0x1e #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_TIC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_TIC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_FUSE_SW_OVERRIDE_SOC_HW_VER_EN_BMSK 0x20000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_FUSE_SW_OVERRIDE_SOC_HW_VER_EN_SHFT 0x1d #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRNG_TESTMODE_DISABLE_BMSK 0x10000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRNG_TESTMODE_DISABLE_SHFT 0x1c #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRNG_TESTMODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRNG_TESTMODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_BMSK 0xe000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_SHFT 0x19 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_ENABLE_PATCHING_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_BOOT_ROM_PATCH_DISABLE_DISABLE_PATCHING_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK 0x800000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT 0x17 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK 0x400000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT 0x16 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK 0x200000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT 0x15 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK 0x100000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT 0x14 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK 0x80000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT 0x13 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC_DEBUG_DISABLE_BMSK 0x40000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC_DEBUG_DISABLE_SHFT 0x12 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_NIDEN_DISABLE_BMSK 0x20000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_NIDEN_DISABLE_SHFT 0x11 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_DBGEN_DISABLE_BMSK 0x10000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_DBGEN_DISABLE_SHFT 0x10 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_APPS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_NIDEN_DISABLE_BMSK 0x8000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_NIDEN_DISABLE_SHFT 0xf #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_DBGEN_DISABLE_BMSK 0x4000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_DBGEN_DISABLE_SHFT 0xe #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_NIDEN_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_NIDEN_DISABLE_SHFT 0xd #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_DBGEN_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_DBGEN_DISABLE_SHFT 0xc #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_NIDEN_DISABLE_BMSK 0x800 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_NIDEN_DISABLE_SHFT 0xb #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_DBGEN_DISABLE_BMSK 0x400 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_DBGEN_DISABLE_SHFT 0xa #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK 0x200 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT 0x9 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK 0x100 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_QC_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_NIDEN_DISABLE_BMSK 0x80 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_NIDEN_DISABLE_SHFT 0x7 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_DBGEN_DISABLE_BMSK 0x40 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_DBGEN_DISABLE_SHFT 0x6 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_NS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_NIDEN_DISABLE_BMSK 0x20 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_NIDEN_DISABLE_SHFT 0x5 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_DBGEN_DISABLE_BMSK 0x10 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_DBGEN_DISABLE_SHFT 0x4 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_CP_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_NIDEN_DISABLE_BMSK 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_NIDEN_DISABLE_SHFT 0x3 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_DBGEN_DISABLE_BMSK 0x4 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_DBGEN_DISABLE_SHFT 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_MSS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_LSB_PRIVATE_QSEE_SPIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041f4) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041f4) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041f4) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_RSVD_BMSK 0x80000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_RSVD_SHFT 0x1f #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_MODEM_PBL_BOOT_BMSK 0x40000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_MODEM_PBL_BOOT_SHFT 0x1e #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_APPS_BOOT_FROM_ROM_BMSK 0x20000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_APPS_BOOT_FROM_ROM_SHFT 0x1d #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ENABLE_DEVICE_IN_TEST_MODE_BMSK 0x10000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ENABLE_DEVICE_IN_TEST_MODE_SHFT 0x1c #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_QTI_ROOT_SIG_FORMAT_SEL_BMSK 0x8000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_QTI_ROOT_SIG_FORMAT_SEL_SHFT 0x1b #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_CE_BAM_DISABLE_BMSK 0x4000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_CE_BAM_DISABLE_SHFT 0x1a #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_CE_BAM_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_CE_BAM_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_BMSK 0x2000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_SHFT 0x19 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ARM_CE_DISABLE_USAGE_BMSK 0x1000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ARM_CE_DISABLE_USAGE_SHFT 0x18 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_BOOT_ROM_CFG_BMSK 0xff0000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_BOOT_ROM_CFG_SHFT 0x10 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_7_BMSK 0x8000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_7_SHFT 0xf #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_6_BMSK 0x4000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_6_SHFT 0xe #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_5_BMSK 0x2000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_5_SHFT 0xd #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_4_BMSK 0x1000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_4_SHFT 0xc #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_3_BMSK 0x800 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_3_SHFT 0xb #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_2_BMSK 0x400 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_2_SHFT 0xa #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_1_BMSK 0x200 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_1_SHFT 0x9 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_0_BMSK 0x100 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_ACCU_RED_DEC_END_VAL_0_SHFT 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE7_BMSK 0x80 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE7_SHFT 0x7 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK 0x40 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT 0x6 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK 0x20 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT 0x5 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK 0x10 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT 0x4 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT 0x3 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK 0x4 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW0_MSB_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041f8) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041f8) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041f8) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK 0xfffc0000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT 0x12 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_TAP_INSTR_DISABLE_BMSK 0x3ffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_LSB_TAP_INSTR_DISABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000041fc) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000041fc) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000041fc) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_SEC_TAP_ACCESS_DISABLE_BMSK 0xfffc0000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_SEC_TAP_ACCESS_DISABLE_SHFT 0x12 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK 0x3ffff #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW1_MSB_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004200) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004200) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004200) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_RMSK 0xffff7bdf #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_MODEM_PBL_PATCH_VERSION_BMSK 0xfe000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_MODEM_PBL_PATCH_VERSION_SHFT 0x19 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_PATCH_VERSION_BMSK 0x1fc0000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_PATCH_VERSION_SHFT 0x12 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_BMSK 0x30000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_SHFT 0x10 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_ENUM_600_MHZ_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_XO_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_ENUM_1200_MHZ_FVAL 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_APPS_PBL_BOOT_SPEED_NA_FVAL 0x3 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_VENDOR_LOCK_BMSK 0x7800 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_VENDOR_LOCK_SHFT 0xb #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_BMSK 0x3c0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_SHFT 0x6 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_TSMC_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_GLOBAL_FOUNDRIES_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_SAMSUNG_FVAL 0x2 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_IBM_FVAL 0x3 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_UMC_FVAL 0x4 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_FOUNDRY_ID_SMIC_FVAL 0x5 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_STACKED_MEMORY_ID_BMSK 0x1f #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_LSB_STACKED_MEMORY_ID_SHFT 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004204) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004204) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004204) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_RMSK 0xffffbfef #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_RSVD_BMSK 0xf0000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_RSVD_SHFT 0x1c #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_BMSK 0xe000000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_SHFT 0x19 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_DISABLED_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_INITIALIZING_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_ACTIVATED_FVAL 0x3 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_SPU_MIRROR_IAR_STATE_DISABLED_ARI_EOL_FVAL 0x7 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_ACCU_RED_DEC_END_VAL_MODEM_BMSK 0x1fe0000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_ACCU_RED_DEC_END_VAL_MODEM_SHFT 0x11 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_KM_BOOT_INIT1_DISABLE_BMSK 0x10000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_KM_BOOT_INIT1_DISABLE_SHFT 0x10 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_KM_BOOT_INIT0_DISABLE_BMSK 0x8000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_KM_BOOT_INIT0_DISABLE_SHFT 0xf #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_APCS_BOOT_TRIGGER_DISABLE_BMSK 0x2000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_APCS_BOOT_TRIGGER_DISABLE_SHFT 0xd #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_APCS_BOOT_TRIGGER_DISABLE_ENABLE_FVAL 0x0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_APCS_BOOT_TRIGGER_DISABLE_DISABLE_FVAL 0x1 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK 0x1000 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT 0xc #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_XBL_SEC_AUTH_DISABLE_BMSK 0x800 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_XBL_SEC_AUTH_DISABLE_SHFT 0xb #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_MSM_PKG_TYPE_BMSK 0x400 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_MSM_PKG_TYPE_SHFT 0xa #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_SPSS_CONFIG_MODE_BMSK 0x300 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_SPSS_CONFIG_MODE_SHFT 0x8 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_PERIPH_DRV_STRENGTH_SETTING__BMSK 0xe0 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_PERIPH_DRV_STRENGTH_SETTING__SHFT 0x5 #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_APPS_PBL_PLL_CTRL_BMSK 0xf #define HWIO_QFPROM_CORR_FEATURE_CONFIG_NM_ROW2_MSB_APPS_PBL_PLL_CTRL_SHFT 0x0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004208) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004208) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004208) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_XBL0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_LSB_XBL0_SHFT 0x0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000420c) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000420c) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000420c) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_XBL1_BMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_1_MSB_XBL1_SHFT 0x0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004210) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004210) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004210) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_LSB_PIL_SUBSYSTEM_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004214) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004214) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004214) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_XBL_SEC_BMSK 0xfe000000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_XBL_SEC_SHFT 0x19 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_SPARE_66_56_BMSK 0x1000000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_SPARE_66_56_SHFT 0x18 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_RPM_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_RPM_SHFT 0x11 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_TZ_BMSK 0x1ffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_2_MSB_TZ_SHFT 0x0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004218) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004218) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004218) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_BMSK 0xc0000000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_XBL_CONFIG_SHFT 0x1e #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_BMSK 0x3e000000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_TQS_HASH_ACTIVE_SHFT 0x19 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_BMSK 0x1000000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_SHFT 0x18 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_RPMB_KEY_NOT_PROVISIONED_FVAL 0x0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_RPMB_KEY_PROVISIONED_RPMB_KEY_PROVISIONED_FVAL 0x1 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_BMSK 0xffff00 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_PIL_SUBSYSTEM_47_32_SHFT 0x8 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_SAFESWITCH_BMSK 0xff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_LSB_SAFESWITCH_SHFT 0x0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000421c) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000421c) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000421c) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_BMSK 0xf0000000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_XBL_CONFIG_SHFT 0x1c #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_BMSK 0xffe0000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEVICE_CFG_SHFT 0x11 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_BMSK 0x1f000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_DEBUG_POLICY_SHFT 0xc #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_HYPERVISOR_BMSK 0xfff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_3_MSB_HYPERVISOR_SHFT 0x0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004220) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004220) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004220) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_IN \ in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_ADDR, m) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MSS_BMSK 0xffff0000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MSS_SHFT 0x10 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MISC_BMSK 0xffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_LSB_MISC_SHFT 0x0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004224) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004224) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004224) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_IN \ in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ADDR, m) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_SIMLOCK_BMSK 0x80000000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_SIMLOCK_SHFT 0x1f #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RSVD0_70_BMSK 0x7ffffff0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_RSVD0_70_SHFT 0x4 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_BMSK 0xf #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_4_MSB_ROOT_CERT_PK_HASH_INDEX_SHFT 0x0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004228) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004228) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004228) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_IN \ in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_ADDR) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_ADDR, m) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_ANTI_ROLLBACK_5_31_13_BMSK 0xffffe000 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_ANTI_ROLLBACK_5_31_13_SHFT 0xd #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_SHRM_BMSK 0x1f00 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_SHRM_SHFT 0x8 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_CPUCP_FW_BMSK 0xff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_LSB_CPUCP_FW_SHFT 0x0 #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000422c) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000422c) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000422c) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_IN \ in_dword(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_ADDR) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_ADDR, m) #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_ANTI_ROLLBACK_5_63_32_BMSK 0xffffffff #define HWIO_QFPROM_CORR_ANTI_ROLLBACK_5_MSB_ANTI_ROLLBACK_5_63_32_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004230) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004230) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004230) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_LSB_PK_HASH_0_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_LSB_PK_HASH_0_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004234) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004234) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004234) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_MSB_PK_HASH_0_63_32_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW0_MSB_PK_HASH_0_63_32_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004238) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004238) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004238) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_LSB_PK_HASH_0_95_64_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_LSB_PK_HASH_0_95_64_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000423c) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000423c) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000423c) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_MSB_PK_HASH_0_127_96_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW1_MSB_PK_HASH_0_127_96_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004240) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004240) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004240) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_LSB_PK_HASH_0_159_128_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_LSB_PK_HASH_0_159_128_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004244) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004244) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004244) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_MSB_PK_HASH_0_191_160_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW2_MSB_PK_HASH_0_191_160_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004248) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004248) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004248) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW3_LSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_LSB_PK_HASH_0_223_192_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_LSB_PK_HASH_0_223_192_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000424c) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000424c) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000424c) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW3_MSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_MSB_PK_HASH_0_255_224_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW3_MSB_PK_HASH_0_255_224_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004250) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004250) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004250) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW4_LSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_LSB_PK_HASH_0_287_256_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_LSB_PK_HASH_0_287_256_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004254) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004254) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004254) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW4_MSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_MSB_PK_HASH_0_319_288_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW4_MSB_PK_HASH_0_319_288_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004258) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004258) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004258) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_LSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW5_LSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW5_LSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_LSB_PK_HASH_0_351_320_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_LSB_PK_HASH_0_351_320_SHFT 0x0 #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000425c) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000425c) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000425c) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_MSB_IN \ in_dword(HWIO_QFPROM_CORR_PK_HASH_0_ROW5_MSB_ADDR) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_PK_HASH_0_ROW5_MSB_ADDR, m) #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_MSB_PK_HASH_0_383_352_BMSK 0xffffffff #define HWIO_QFPROM_CORR_PK_HASH_0_ROW5_MSB_PK_HASH_0_383_352_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004260) #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004260) #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004260) #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_REFGEN_SOUTHEAST_BGV_TRIM_4_0_BMSK 0xf8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_REFGEN_SOUTHEAST_BGV_TRIM_4_0_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_USB2PHY_RCAL_CODE_BMSK 0x7800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_USB2PHY_RCAL_CODE_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_BANDGAP_TRIM_BMSK 0x7f0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_BANDGAP_TRIM_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_REFGEN_NORTH_BGV_TRIM_BMSK 0xff00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_REFGEN_NORTH_BGV_TRIM_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_REFGEN_SOUTH_BGV_TRIM_BMSK 0xff #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_LSB_REFGEN_SOUTH_BGV_TRIM_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004264) #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004264) #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004264) #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_RMSK 0xffffffe7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B63_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B63_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B62_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B62_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B61_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B61_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B60_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B60_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B59_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B59_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B58_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B58_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B57_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B57_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B56_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B56_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B55_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B55_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B54_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B54_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B53_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B53_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B52_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B52_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B51_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B51_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B50_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B50_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B49_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B49_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B48_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B48_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B47_BMSK 0x8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B47_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B46_BMSK 0x4000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B46_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B45_BMSK 0x2000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B45_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B44_BMSK 0x1000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B44_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B43_BMSK 0x800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B43_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B42_BMSK 0x400 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B42_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B41_BMSK 0x200 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B41_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B40_BMSK 0x100 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B40_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B39_BMSK 0x80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B39_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B38_BMSK 0x40 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B38_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B37_BMSK 0x20 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_SPARE_R76_B37_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_REFGEN_SOUTHEAST_BGV_TRIM_7_5_BMSK 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW0_MSB_REFGEN_SOUTHEAST_BGV_TRIM_7_5_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004268) #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004268) #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004268) #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B31_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B31_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B30_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B30_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B29_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B29_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B28_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B28_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B27_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B27_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B26_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B26_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B25_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B25_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B24_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B24_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B23_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B23_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B22_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B22_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B21_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B21_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B20_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B20_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B19_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B19_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B18_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B18_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B17_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B17_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B16_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B16_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B15_BMSK 0x8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B15_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B14_BMSK 0x4000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B14_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B13_BMSK 0x2000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B13_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B12_BMSK 0x1000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B12_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B11_BMSK 0x800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B11_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B10_BMSK 0x400 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B10_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B9_BMSK 0x200 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B9_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B8_BMSK 0x100 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B8_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B7_BMSK 0x80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B7_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B6_BMSK 0x40 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B6_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B5_BMSK 0x20 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B5_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B4_BMSK 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B4_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B3_BMSK 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B3_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B2_BMSK 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B2_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B1_BMSK 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B1_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B0_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_LSB_SPARE_R77_B0_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000426c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000426c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000426c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B63_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B63_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B62_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B62_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B61_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B61_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B60_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B60_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B59_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B59_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B58_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B58_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B57_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B57_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B56_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B56_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B55_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B55_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B54_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B54_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B53_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B53_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B52_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B52_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B51_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B51_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B50_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B50_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B49_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B49_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B48_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B48_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B47_BMSK 0x8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B47_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B46_BMSK 0x4000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B46_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B45_BMSK 0x2000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B45_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B44_BMSK 0x1000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B44_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B43_BMSK 0x800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B43_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B42_BMSK 0x400 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B42_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B41_BMSK 0x200 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B41_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B40_BMSK 0x100 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B40_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B39_BMSK 0x80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B39_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B38_BMSK 0x40 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B38_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B37_BMSK 0x20 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B37_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B36_BMSK 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B36_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B35_BMSK 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B35_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B34_BMSK 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B34_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B33_BMSK 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B33_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B32_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW1_MSB_SPARE_R77_B32_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004270) #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004270) #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004270) #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_NOM_BMSK 0xf0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_NOM_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_TUR_BMSK 0xf000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_TUR_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_SUT_BMSK 0xf00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_OFFSET_SUT_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SVS2_BMSK 0xf8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SVS2_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SVS_BMSK 0x7c00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SVS_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_NOM_BMSK 0x3e0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_NOM_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SUT_BMSK 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_LSB_CPR0_TARG_VOLT_SUT_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004274) #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004274) #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004274) #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_SVS_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_SVS_1_0_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_NOM_BMSK 0x3e000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_NOM_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_TUR_BMSK 0x1f00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR1_TARG_VOLT_TUR_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR0_AGING_BMSK 0xff000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR0_AGING_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_BMSK 0xf00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVS2_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVS_BMSK 0xf0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVS_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVSL1_BMSK 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW2_MSB_CPR0_TARG_VOLT_OFFSET_SVSL1_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004278) #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004278) #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004278) #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_AGING_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_AGING_3_0_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVS2_BMSK 0xf000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVS2_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVS_BMSK 0xf00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVS_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVSL1_BMSK 0xf0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_SVSL1_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_NOM_BMSK 0xf000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_NOM_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_TUR_BMSK 0xf00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_OFFSET_TUR_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_SVS2_BMSK 0xf8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_SVS2_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_SVS_4_2_BMSK 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_LSB_CPR1_TARG_VOLT_SVS_4_2_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000427c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000427c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000427c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_OFFSET_TUR_2_0_BMSK 0xe0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_OFFSET_TUR_2_0_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVS2_BMSK 0x1f000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVS2_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVS_BMSK 0xf80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVS_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVSP_BMSK 0x7c000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SVSP_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_NOM_BMSK 0x3e00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_NOM_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SUT_BMSK 0x1f0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR2_TARG_VOLT_SUT_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR1_AGING_7_4_BMSK 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW3_MSB_CPR1_AGING_7_4_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004280) #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004280) #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004280) #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_AGING_2_0_BMSK 0xe0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_AGING_2_0_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SUT_BMSK 0x1e000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SUT_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVS2_BMSK 0x1e00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVS2_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVS_BMSK 0x1e0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVS_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVSL2_BMSK 0x1e000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVSL2_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVSL1_BMSK 0x1e00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_SVSL1_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_NOMP_BMSK 0x1e0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_NOMP_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_NOM_BMSK 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_NOM_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_TUR_3_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_LSB_CPR2_TARG_VOLT_OFFSET_TUR_3_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004284) #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004284) #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004284) #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR4_TARG_VOLT_NOM_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR4_TARG_VOLT_NOM_1_0_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR4_TARG_VOLT_TUR_BMSK 0x3e000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR4_TARG_VOLT_TUR_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SVS2_BMSK 0x1f00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SVS2_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SVS_BMSK 0xf8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SVS_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_NOM_BMSK 0x7c00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_NOM_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SUT_BMSK 0x3e0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR3_TARG_VOLT_SUT_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR2_AGING_7_3_BMSK 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW4_MSB_CPR2_AGING_7_3_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004288) #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004288) #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004288) #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR5_TARG_VOLT_SUT_2_0_BMSK 0xe0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR5_TARG_VOLT_SUT_2_0_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SUT_BMSK 0x1e000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SUT_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SVSP_BMSK 0x1e00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_SVSP_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_NOM_BMSK 0x1e0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_NOM_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_TUR_BMSK 0x1e000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_OFFSET_TUR_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_SUT_BMSK 0x1f00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_SUT_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_SVSP_BMSK 0xf8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_SVSP_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_NOM_4_2_BMSK 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_LSB_CPR4_TARG_VOLT_NOM_4_2_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000428c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000428c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000428c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_SVS_BMSK 0xf8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_SVS_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_NOM_BMSK 0x7c00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_NOM_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_TUR_BMSK 0x3e0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR6_TARG_VOLT_TUR_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_TUR_BMSK 0x1f000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_TUR_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_SVSP_BMSK 0xf80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_SVSP_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_NOM_BMSK 0x7c #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_NOM_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_SUT_4_3_BMSK 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW5_MSB_CPR5_TARG_VOLT_SUT_4_3_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004290) #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004290) #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004290) #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_SVSL1_BMSK 0xf0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_SVSL1_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_NOM_BMSK 0xf000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_NOM_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_TUR_BMSK 0xf00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_OFFSET_TUR_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_SVS2_BMSK 0xf8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_SVS2_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_SVS_BMSK 0x7c00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_SVS_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_NOM_BMSK 0x3e0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_NOM_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_TUR_BMSK 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_LSB_CPR7_TARG_VOLT_TUR_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004294) #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004294) #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004294) #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_SVS2_0_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_SVS2_0_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_SVS_BMSK 0x7c000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_SVS_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_NOM_BMSK 0x3e00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_NOM_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_TUR_BMSK 0x1f0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR8_TARG_VOLT_TUR_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR7_AGING_BMSK 0xff00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR7_AGING_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR7_TARG_VOLT_OFFSET_SVS2_BMSK 0xf0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR7_TARG_VOLT_OFFSET_SVS2_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR7_TARG_VOLT_OFFSET_SVS_BMSK 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW6_MSB_CPR7_TARG_VOLT_OFFSET_SVS_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004298) #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004298) #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004298) #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_AGING_BMSK 0xff000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_AGING_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVS2_BMSK 0xf00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVS2_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVS_BMSK 0xf0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVS_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVSL1_BMSK 0xf000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_SVSL1_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_NOM_BMSK 0xf00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_NOM_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_TUR_BMSK 0xf0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_OFFSET_TUR_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_SVS2_4_1_BMSK 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_LSB_CPR8_TARG_VOLT_SVS2_4_1_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000429c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000429c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000429c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_SVS_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_SVS_3_0_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_NOM_BMSK 0xfc00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_NOM_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_TUR_BMSK 0x3f0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_CPR9_TARG_VOLT_TUR_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_CPR_GLOBAL_RC_BMSK 0xe000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_CPR_GLOBAL_RC_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_AON_AGING_BMSK 0x1fe0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_AON_AGING_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_AON_TARG_VOLT_BMSK 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW7_MSB_AON_TARG_VOLT_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042a0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042a0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042a0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_CPR9_NOMINAL_QUOT_MIN_BMSK 0xfff00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_CPR9_NOMINAL_QUOT_MIN_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_CPR9_TURBO_QUOT_MIN_BMSK 0xfff00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_CPR9_TURBO_QUOT_MIN_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_CPR9_TARG_VOLT_SVS2_BMSK 0xfc #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_CPR9_TARG_VOLT_SVS2_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_CPR9_TARG_VOLT_SVS_5_4_BMSK 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_LSB_CPR9_TARG_VOLT_SVS_5_4_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042a4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042a4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042a4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_CPR9_QUOT_OFFSET_TUR_BMSK 0xff000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_CPR9_QUOT_OFFSET_TUR_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_CPR9_SVS2_QUOT_MIN_BMSK 0xfff000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_CPR9_SVS2_QUOT_MIN_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_CPR9_SVS_QUOT_MIN_BMSK 0xfff #define HWIO_QFPROM_CORR_CALIBRATION_ROW8_MSB_CPR9_SVS_QUOT_MIN_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042a8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042a8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042a8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_CPR10_TARG_VOLT_NOM_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_CPR10_TARG_VOLT_NOM_3_0_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_CPR10_TARG_VOLT_TUR_BMSK 0xfc00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_CPR10_TARG_VOLT_TUR_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_CPR9_AGING_BMSK 0x3fc000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_CPR9_AGING_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_CPR9_QUOT_OFFSET_SVS_BMSK 0x3f80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_CPR9_QUOT_OFFSET_SVS_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_CPR9_QUOT_OFFSET_NOM_BMSK 0x7f #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_LSB_CPR9_QUOT_OFFSET_NOM_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042ac) #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042ac) #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042ac) #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_CPR10_NOMINAL_QUOT_MIN_5_0_BMSK 0xfc000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_CPR10_NOMINAL_QUOT_MIN_5_0_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_CPR10_TURBO_QUOT_MIN_BMSK 0x3ffc000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_CPR10_TURBO_QUOT_MIN_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_SVS2_BMSK 0x3f00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_SVS2_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_SVS_BMSK 0xfc #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_SVS_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_NOM_5_4_BMSK 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW9_MSB_CPR10_TARG_VOLT_NOM_5_4_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042b0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042b0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042b0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_CPR10_QUOT_OFFSET_TUR_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_CPR10_QUOT_OFFSET_TUR_1_0_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_CPR10_SVS2_QUOT_MIN_BMSK 0x3ffc0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_CPR10_SVS2_QUOT_MIN_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_CPR10_SVS_QUOT_MIN_BMSK 0x3ffc0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_CPR10_SVS_QUOT_MIN_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_CPR10_NOMINAL_QUOT_MIN_11_6_BMSK 0x3f #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_LSB_CPR10_NOMINAL_QUOT_MIN_11_6_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042b4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042b4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042b4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_CPR11_TARG_VOLT_NOM_BMSK 0xfc000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_CPR11_TARG_VOLT_NOM_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_CPR11_TARG_VOLT_TUR_BMSK 0x3f00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_CPR11_TARG_VOLT_TUR_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_SVS_BMSK 0xfe000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_SVS_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_NOM_BMSK 0x1fc0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_NOM_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_TUR_7_2_BMSK 0x3f #define HWIO_QFPROM_CORR_CALIBRATION_ROW10_MSB_CPR10_QUOT_OFFSET_TUR_7_2_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042b8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042b8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042b8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_CPR11_NOMINAL_QUOT_MIN_7_0_BMSK 0xff000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_CPR11_NOMINAL_QUOT_MIN_7_0_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_CPR11_TURBO_QUOT_MIN_BMSK 0xfff000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_CPR11_TURBO_QUOT_MIN_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_CPR11_TARG_VOLT_SVS2_BMSK 0xfc0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_CPR11_TARG_VOLT_SVS2_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_CPR11_TARG_VOLT_SVS_BMSK 0x3f #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_LSB_CPR11_TARG_VOLT_SVS_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042bc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042bc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042bc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_CPR11_QUOT_OFFSET_TUR_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_CPR11_QUOT_OFFSET_TUR_3_0_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_CPR11_SVS2_QUOT_MIN_BMSK 0xfff0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_CPR11_SVS2_QUOT_MIN_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_CPR11_SVS_QUOT_MIN_BMSK 0xfff0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_CPR11_SVS_QUOT_MIN_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_CPR11_NOMINAL_QUOT_MIN_11_8_BMSK 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW11_MSB_CPR11_NOMINAL_QUOT_MIN_11_8_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042c0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042c0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042c0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_CPR12_TARG_VOLT_TUR_BMSK 0xfc000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_CPR12_TARG_VOLT_TUR_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_CPR11_AGING_BMSK 0x3fc0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_CPR11_AGING_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_SVS_BMSK 0x3f800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_SVS_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_NOM_BMSK 0x7f0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_NOM_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_TUR_7_4_BMSK 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_LSB_CPR11_QUOT_OFFSET_TUR_7_4_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042c4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042c4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042c4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_CPR12_NOMINAL_QUOT_MIN_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_CPR12_NOMINAL_QUOT_MIN_1_0_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_CPR12_TURBO_QUOT_MIN_BMSK 0x3ffc0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_CPR12_TURBO_QUOT_MIN_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_SVS2_BMSK 0x3f000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_SVS2_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_SVS_BMSK 0xfc0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_SVS_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_NOM_BMSK 0x3f #define HWIO_QFPROM_CORR_CALIBRATION_ROW12_MSB_CPR12_TARG_VOLT_NOM_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042c8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042c8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042c8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_CPR12_SVS2_QUOT_MIN_9_0_BMSK 0xffc00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_CPR12_SVS2_QUOT_MIN_9_0_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_CPR12_SVS_QUOT_MIN_BMSK 0x3ffc00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_CPR12_SVS_QUOT_MIN_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_CPR12_NOMINAL_QUOT_MIN_11_2_BMSK 0x3ff #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_LSB_CPR12_NOMINAL_QUOT_MIN_11_2_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042cc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042cc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042cc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR_MSS_MODE_DISABLE_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR_MSS_MODE_DISABLE_1_0_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR_CX_MODE_DISABLE_BMSK 0x38000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR_CX_MODE_DISABLE_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR_LOCAL_RC_BMSK 0x7000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR_LOCAL_RC_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_SVS_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_SVS_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_NOM_BMSK 0x1fc00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_NOM_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_TUR_BMSK 0x3fc #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR12_QUOT_OFFSET_TUR_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR12_SVS2_QUOT_MIN_11_10_BMSK 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW13_MSB_CPR12_SVS2_QUOT_MIN_11_10_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042d0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042d0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042d0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_RESERVED_12_0_BMSK 0xfff80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_RESERVED_12_0_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_MMCX_MODE_DISABLE_BMSK 0x70000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_MMCX_MODE_DISABLE_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_SSCX_MODE_DISABLE_BMSK 0xe000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_SSCX_MODE_DISABLE_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_LPIMX_MODE_DISABLE_BMSK 0x1c00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_LPIMX_MODE_DISABLE_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_MX_MODE_DISABLE_BMSK 0x380 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_MX_MODE_DISABLE_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_DDR_MODE_DISABLE_BMSK 0x70 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_DDR_MODE_DISABLE_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_GFX_MODE_DISABLE_BMSK 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_GFX_MODE_DISABLE_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_MSS_MODE_DISABLE_2_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_LSB_CPR_MSS_MODE_DISABLE_2_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042d4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042d4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042d4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_SPARE_R90_B63_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_SPARE_R90_B63_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_SPARE_R90_B62_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_SPARE_R90_B62_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_SPARE_R90_B61_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_SPARE_R90_B61_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_SPARE_R90_B60_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_SPARE_R90_B60_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_CPR_RESERVED_40_13_BMSK 0xfffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW14_MSB_CPR_RESERVED_40_13_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042d8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042d8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042d8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_TSENS1_BASE1_1_0_BMSK 0xc0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_TSENS1_BASE1_1_0_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_TSENS0_BASE1_BMSK 0x3ff00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_TSENS0_BASE1_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_TSENS1_BASE0_BMSK 0xffc00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_TSENS1_BASE0_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_TSENS0_BASE0_BMSK 0x3ff #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_LSB_TSENS0_BASE0_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042dc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042dc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042dc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS4_OFFSET_3_0_BMSK 0xf0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS4_OFFSET_3_0_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS3_OFFSET_BMSK 0xf800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS3_OFFSET_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS2_OFFSET_BMSK 0x7c0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS2_OFFSET_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS1_OFFSET_BMSK 0x3e000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS1_OFFSET_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS0_OFFSET_BMSK 0x1f00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS0_OFFSET_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS1_BASE1_9_2_BMSK 0xff #define HWIO_QFPROM_CORR_CALIBRATION_ROW15_MSB_TSENS1_BASE1_9_2_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042e0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042e0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042e0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS11_OFFSET_0_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS11_OFFSET_0_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS10_OFFSET_BMSK 0x7c000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS10_OFFSET_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS9_OFFSET_BMSK 0x3e00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS9_OFFSET_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS8_OFFSET_BMSK 0x1f0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS8_OFFSET_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS7_OFFSET_BMSK 0xf800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS7_OFFSET_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS6_OFFSET_BMSK 0x7c0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS6_OFFSET_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS5_OFFSET_BMSK 0x3e #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS5_OFFSET_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS4_OFFSET_4_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_LSB_TSENS4_OFFSET_4_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042e4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042e4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042e4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS17_OFFSET_2_0_BMSK 0xe0000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS17_OFFSET_2_0_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS16_OFFSET_BMSK 0x1f000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS16_OFFSET_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS15_OFFSET_BMSK 0xf80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS15_OFFSET_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS14_OFFSET_BMSK 0x7c000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS14_OFFSET_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS13_OFFSET_BMSK 0x3e00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS13_OFFSET_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS12_OFFSET_BMSK 0x1f0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS12_OFFSET_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS11_OFFSET_4_1_BMSK 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW16_MSB_TSENS11_OFFSET_4_1_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042e8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042e8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042e8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS23_OFFSET_BMSK 0xf8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS23_OFFSET_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS22_OFFSET_BMSK 0x7c00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS22_OFFSET_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS21_OFFSET_BMSK 0x3e0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS21_OFFSET_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS20_OFFSET_BMSK 0x1f000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS20_OFFSET_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS19_OFFSET_BMSK 0xf80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS19_OFFSET_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS18_OFFSET_BMSK 0x7c #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS18_OFFSET_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS17_OFFSET_4_3_BMSK 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_LSB_TSENS17_OFFSET_4_3_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042ec) #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042ec) #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042ec) #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_SPARE_R93_B63_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_SPARE_R93_B63_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_SPARE_R93_B62_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_SPARE_R93_B62_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_SPARE_R93_B61_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_SPARE_R93_B61_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_SPARE_R93_B60_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_SPARE_R93_B60_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS_CAL_SEL_BMSK 0xe000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS_CAL_SEL_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS28_OFFSET_BMSK 0x1f00000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS28_OFFSET_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS27_OFFSET_BMSK 0xf8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS27_OFFSET_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS26_OFFSET_BMSK 0x7c00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS26_OFFSET_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS25_OFFSET_BMSK 0x3e0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS25_OFFSET_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS24_OFFSET_BMSK 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW17_MSB_TSENS24_OFFSET_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042f0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042f0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042f0) #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_LSB_RMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW18_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW18_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_LSB_SPARE_R94_B0_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_LSB_SPARE_R94_B0_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042f4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042f4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042f4) #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW18_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW18_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW18_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042f8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042f8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042f8) #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW19_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW19_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_LSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_LSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000042fc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000042fc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000042fc) #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW19_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW19_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW19_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004300) #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004300) #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004300) #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW20_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW20_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_LSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_LSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004304) #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004304) #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004304) #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW20_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW20_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW20_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004308) #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004308) #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004308) #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW21_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW21_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_LSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_LSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000430c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000430c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000430c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW21_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW21_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW21_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004310) #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004310) #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004310) #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW22_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW22_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_LSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_LSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004314) #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004314) #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004314) #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW22_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW22_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_MSB_RSVD_BMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW22_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004318) #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004318) #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004318) #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_RMSK 0xfffffffe #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_AOSS_P1_12_0_BMSK 0xfff80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_AOSS_P1_12_0_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_AOSS_N1_BMSK 0x7fffe #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_LSB_AOSS_N1_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000431c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000431c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000431c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_LPASS_N1_4_0_BMSK 0xf8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_LPASS_N1_4_0_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_AOSS_K_BMSK 0x7fff800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_AOSS_K_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_AOSS_TDOPCODE_BMSK 0x700 #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_AOSS_TDOPCODE_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_AOSS_RDOPCODE_BMSK 0xe0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_AOSS_RDOPCODE_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_AOSS_P1_17_13_BMSK 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW23_MSB_AOSS_P1_17_13_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004320) #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004320) #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004320) #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_LPASS_RDOPCODE_0_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_LPASS_RDOPCODE_0_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_LPASS_P1_BMSK 0x7fffe000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_LPASS_P1_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_LPASS_N1_17_5_BMSK 0x1fff #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_LSB_LPASS_N1_17_5_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004324) #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004324) #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004324) #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B63_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B63_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B62_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B62_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B61_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B61_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B60_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B60_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B59_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B59_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B58_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B58_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B57_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B57_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B56_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B56_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B55_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B55_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B54_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B54_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B53_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_SPARE_R100_B53_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_LPASS_K_BMSK 0x1fffe0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_LPASS_K_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_LPASS_TDOPCODE_BMSK 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_LPASS_TDOPCODE_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_LPASS_RDOPCODE_2_1_BMSK 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW24_MSB_LPASS_RDOPCODE_2_1_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004328) #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004328) #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004328) #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B31_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B31_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B30_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B30_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B29_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B29_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B28_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B28_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B27_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B27_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B26_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B26_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B25_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B25_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B24_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B24_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B23_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B23_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B22_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B22_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B21_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B21_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B20_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B20_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B19_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B19_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B18_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B18_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B17_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B17_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B16_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B16_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B15_BMSK 0x8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B15_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B14_BMSK 0x4000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B14_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B13_BMSK 0x2000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B13_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B12_BMSK 0x1000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B12_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B11_BMSK 0x800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B11_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B10_BMSK 0x400 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B10_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B9_BMSK 0x200 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B9_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B8_BMSK 0x100 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B8_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B7_BMSK 0x80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B7_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B6_BMSK 0x40 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B6_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B5_BMSK 0x20 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B5_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B4_BMSK 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B4_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B3_BMSK 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B3_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B2_BMSK 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B2_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B1_BMSK 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B1_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B0_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_LSB_SPARE_R101_B0_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000432c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000432c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000432c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B63_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B63_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B62_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B62_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B61_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B61_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B60_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B60_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B59_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B59_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B58_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B58_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B57_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B57_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B56_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B56_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B55_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B55_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B54_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B54_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B53_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B53_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B52_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B52_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B51_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B51_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B50_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B50_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B49_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B49_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B48_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B48_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B47_BMSK 0x8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B47_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B46_BMSK 0x4000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B46_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B45_BMSK 0x2000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B45_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B44_BMSK 0x1000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B44_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B43_BMSK 0x800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B43_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B42_BMSK 0x400 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B42_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B41_BMSK 0x200 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B41_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B40_BMSK 0x100 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B40_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B39_BMSK 0x80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B39_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B38_BMSK 0x40 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B38_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B37_BMSK 0x20 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B37_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B36_BMSK 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B36_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B35_BMSK 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B35_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B34_BMSK 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B34_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B33_BMSK 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B33_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B32_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW25_MSB_SPARE_R101_B32_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004330) #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004330) #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004330) #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B31_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B31_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B30_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B30_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B29_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B29_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B28_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B28_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B27_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B27_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B26_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B26_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B25_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B25_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B24_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B24_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B23_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B23_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B22_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B22_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B21_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B21_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B20_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B20_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B19_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B19_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B18_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B18_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B17_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B17_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B16_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B16_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B15_BMSK 0x8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B15_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B14_BMSK 0x4000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B14_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B13_BMSK 0x2000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B13_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B12_BMSK 0x1000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B12_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B11_BMSK 0x800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B11_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B10_BMSK 0x400 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B10_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B9_BMSK 0x200 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B9_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B8_BMSK 0x100 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B8_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B7_BMSK 0x80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B7_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B6_BMSK 0x40 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B6_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B5_BMSK 0x20 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B5_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B4_BMSK 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B4_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B3_BMSK 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B3_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B2_BMSK 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B2_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B1_BMSK 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B1_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B0_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_LSB_SPARE_R102_B0_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004334) #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004334) #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004334) #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B63_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B63_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B62_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B62_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B61_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B61_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B60_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B60_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B59_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B59_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B58_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B58_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B57_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B57_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B56_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B56_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B55_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B55_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B54_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B54_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B53_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B53_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B52_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B52_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B51_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B51_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B50_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B50_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B49_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B49_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B48_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B48_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B47_BMSK 0x8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B47_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B46_BMSK 0x4000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B46_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B45_BMSK 0x2000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B45_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B44_BMSK 0x1000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B44_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B43_BMSK 0x800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B43_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B42_BMSK 0x400 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B42_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B41_BMSK 0x200 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B41_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B40_BMSK 0x100 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B40_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B39_BMSK 0x80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B39_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B38_BMSK 0x40 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B38_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B37_BMSK 0x20 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B37_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B36_BMSK 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B36_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B35_BMSK 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B35_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B34_BMSK 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B34_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B33_BMSK 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B33_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B32_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW26_MSB_SPARE_R102_B32_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004338) #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004338) #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004338) #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B31_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B31_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B30_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B30_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B29_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B29_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B28_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B28_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B27_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B27_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B26_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B26_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B25_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B25_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B24_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B24_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B23_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B23_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B22_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B22_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B21_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B21_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B20_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B20_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B19_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B19_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B18_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B18_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B17_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B17_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B16_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B16_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B15_BMSK 0x8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B15_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B14_BMSK 0x4000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B14_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B13_BMSK 0x2000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B13_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B12_BMSK 0x1000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B12_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B11_BMSK 0x800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B11_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B10_BMSK 0x400 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B10_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B9_BMSK 0x200 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B9_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B8_BMSK 0x100 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B8_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B7_BMSK 0x80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B7_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B6_BMSK 0x40 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B6_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B5_BMSK 0x20 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B5_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B4_BMSK 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B4_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B3_BMSK 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B3_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B2_BMSK 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B2_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B1_BMSK 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B1_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B0_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_LSB_SPARE_R103_B0_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000433c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000433c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000433c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B63_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B63_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B62_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B62_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B61_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B61_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B60_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B60_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B59_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B59_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B58_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B58_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B57_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B57_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B56_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B56_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B55_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B55_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B54_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B54_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B53_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B53_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B52_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B52_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B51_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B51_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B50_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B50_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B49_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B49_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B48_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B48_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B47_BMSK 0x8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B47_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B46_BMSK 0x4000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B46_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B45_BMSK 0x2000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B45_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B44_BMSK 0x1000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B44_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B43_BMSK 0x800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B43_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B42_BMSK 0x400 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B42_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B41_BMSK 0x200 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B41_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B40_BMSK 0x100 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B40_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B39_BMSK 0x80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B39_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B38_BMSK 0x40 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B38_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B37_BMSK 0x20 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B37_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B36_BMSK 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B36_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B35_BMSK 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B35_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B34_BMSK 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B34_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B33_BMSK 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B33_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B32_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW27_MSB_SPARE_R103_B32_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004340) #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004340) #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004340) #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B31_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B31_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B30_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B30_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B29_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B29_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B28_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B28_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B27_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B27_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B26_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B26_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B25_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B25_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B24_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B24_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B23_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B23_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B22_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B22_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B21_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B21_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B20_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B20_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B19_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B19_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B18_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B18_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B17_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B17_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B16_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B16_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B15_BMSK 0x8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B15_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B14_BMSK 0x4000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B14_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B13_BMSK 0x2000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B13_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B12_BMSK 0x1000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B12_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B11_BMSK 0x800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B11_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B10_BMSK 0x400 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B10_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B9_BMSK 0x200 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B9_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B8_BMSK 0x100 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B8_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B7_BMSK 0x80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B7_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B6_BMSK 0x40 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B6_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B5_BMSK 0x20 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B5_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B4_BMSK 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B4_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B3_BMSK 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B3_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B2_BMSK 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B2_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B1_BMSK 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B1_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B0_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_LSB_SPARE_R104_B0_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004344) #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004344) #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004344) #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B63_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B63_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B62_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B62_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B61_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B61_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B60_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B60_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B59_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B59_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B58_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B58_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B57_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B57_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B56_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B56_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B55_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B55_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B54_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B54_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B53_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B53_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B52_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B52_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B51_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B51_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B50_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B50_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B49_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B49_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B48_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B48_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B47_BMSK 0x8000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B47_SHFT 0xf #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B46_BMSK 0x4000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B46_SHFT 0xe #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B45_BMSK 0x2000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B45_SHFT 0xd #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B44_BMSK 0x1000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B44_SHFT 0xc #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B43_BMSK 0x800 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B43_SHFT 0xb #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B42_BMSK 0x400 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B42_SHFT 0xa #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B41_BMSK 0x200 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B41_SHFT 0x9 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B40_BMSK 0x100 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B40_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B39_BMSK 0x80 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B39_SHFT 0x7 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B38_BMSK 0x40 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B38_SHFT 0x6 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B37_BMSK 0x20 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B37_SHFT 0x5 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B36_BMSK 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B36_SHFT 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B35_BMSK 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B35_SHFT 0x3 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B34_BMSK 0x4 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B34_SHFT 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B33_BMSK 0x2 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B33_SHFT 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B32_BMSK 0x1 #define HWIO_QFPROM_CORR_CALIBRATION_ROW28_MSB_SPARE_R104_B32_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004348) #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004348) #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004348) #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_Q6_ACD_DVM_VAL1_7_0_BMSK 0xff000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_Q6_ACD_DVM_VAL1_7_0_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_Q6_ACD_DVM_VAL0_BMSK 0xffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_LSB_Q6_ACD_DVM_VAL0_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000434c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000434c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000434c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_Q6_ACD_DVM_VAL2_15_0_BMSK 0xffff0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_Q6_ACD_DVM_VAL2_15_0_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_Q6_ACD_DVM_VAL1_23_8_BMSK 0xffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW29_MSB_Q6_ACD_DVM_VAL1_23_8_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004350) #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004350) #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004350) #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_Q6_ACD_DVM_VAL3_BMSK 0xffffff00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_Q6_ACD_DVM_VAL3_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_Q6_ACD_DVM_VAL2_23_16_BMSK 0xff #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_LSB_Q6_ACD_DVM_VAL2_23_16_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004354) #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004354) #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004354) #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_Q6_ACD_DVM_VAL5_7_0_BMSK 0xff000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_Q6_ACD_DVM_VAL5_7_0_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_Q6_ACD_DVM_VAL4_BMSK 0xffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW30_MSB_Q6_ACD_DVM_VAL4_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004358) #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004358) #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004358) #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_Q6_ACD_DVM_VAL6_15_0_BMSK 0xffff0000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_Q6_ACD_DVM_VAL6_15_0_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_Q6_ACD_DVM_VAL5_23_8_BMSK 0xffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_LSB_Q6_ACD_DVM_VAL5_23_8_SHFT 0x0 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000435c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000435c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000435c) #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_IN \ in_dword(HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_ADDR) #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_ADDR, m) #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B63_BMSK 0x80000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B63_SHFT 0x1f #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B62_BMSK 0x40000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B62_SHFT 0x1e #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B61_BMSK 0x20000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B61_SHFT 0x1d #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B60_BMSK 0x10000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B60_SHFT 0x1c #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B59_BMSK 0x8000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B59_SHFT 0x1b #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B58_BMSK 0x4000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B58_SHFT 0x1a #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B57_BMSK 0x2000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B57_SHFT 0x19 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B56_BMSK 0x1000000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B56_SHFT 0x18 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B55_BMSK 0x800000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B55_SHFT 0x17 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B54_BMSK 0x400000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B54_SHFT 0x16 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B53_BMSK 0x200000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B53_SHFT 0x15 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B52_BMSK 0x100000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B52_SHFT 0x14 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B51_BMSK 0x80000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B51_SHFT 0x13 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B50_BMSK 0x40000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B50_SHFT 0x12 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B49_BMSK 0x20000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B49_SHFT 0x11 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B48_BMSK 0x10000 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_SPARE_R107_B48_SHFT 0x10 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_Q6_ACD_DVM_ENABLE_BMSK 0xff00 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_Q6_ACD_DVM_ENABLE_SHFT 0x8 #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_Q6_ACD_DVM_VAL6_23_16_BMSK 0xff #define HWIO_QFPROM_CORR_CALIBRATION_ROW31_MSB_Q6_ACD_DVM_VAL6_23_16_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004360) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004360) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004360) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_LSB_MEMORY_REDUNDANCY_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_LSB_MEMORY_REDUNDANCY_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004364) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004364) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004364) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_MSB_MEMORY_REDUNDANCY_63_32_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW0_MSB_MEMORY_REDUNDANCY_63_32_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004368) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004368) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004368) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_LSB_MEMORY_REDUNDANCY_95_64_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_LSB_MEMORY_REDUNDANCY_95_64_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000436c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000436c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000436c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_MSB_MEMORY_REDUNDANCY_127_96_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW1_MSB_MEMORY_REDUNDANCY_127_96_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004370) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004370) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004370) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_LSB_MEMORY_REDUNDANCY_159_128_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_LSB_MEMORY_REDUNDANCY_159_128_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004374) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004374) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004374) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_MSB_MEMORY_REDUNDANCY_191_160_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW2_MSB_MEMORY_REDUNDANCY_191_160_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004378) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004378) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004378) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_LSB_MEMORY_REDUNDANCY_223_192_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_LSB_MEMORY_REDUNDANCY_223_192_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000437c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000437c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000437c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_MSB_MEMORY_REDUNDANCY_255_224_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW3_MSB_MEMORY_REDUNDANCY_255_224_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004380) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004380) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004380) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_LSB_MEMORY_REDUNDANCY_287_256_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_LSB_MEMORY_REDUNDANCY_287_256_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004384) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004384) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004384) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_MSB_MEMORY_REDUNDANCY_319_288_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW4_MSB_MEMORY_REDUNDANCY_319_288_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004388) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004388) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004388) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_LSB_MEMORY_REDUNDANCY_351_320_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_LSB_MEMORY_REDUNDANCY_351_320_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000438c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000438c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000438c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_MSB_MEMORY_REDUNDANCY_383_352_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW5_MSB_MEMORY_REDUNDANCY_383_352_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004390) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004390) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004390) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_LSB_MEMORY_REDUNDANCY_415_384_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_LSB_MEMORY_REDUNDANCY_415_384_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004394) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004394) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004394) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_MSB_MEMORY_REDUNDANCY_447_416_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW6_MSB_MEMORY_REDUNDANCY_447_416_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004398) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004398) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004398) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_LSB_MEMORY_REDUNDANCY_479_448_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_LSB_MEMORY_REDUNDANCY_479_448_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000439c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000439c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000439c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_MSB_MEMORY_REDUNDANCY_511_480_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW7_MSB_MEMORY_REDUNDANCY_511_480_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043a0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043a0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043a0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_LSB_MEMORY_REDUNDANCY_543_512_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_LSB_MEMORY_REDUNDANCY_543_512_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043a4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043a4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043a4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_MSB_MEMORY_REDUNDANCY_575_544_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW8_MSB_MEMORY_REDUNDANCY_575_544_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043a8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043a8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043a8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_LSB_MEMORY_REDUNDANCY_607_576_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_LSB_MEMORY_REDUNDANCY_607_576_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043ac) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043ac) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043ac) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_MSB_MEMORY_REDUNDANCY_639_608_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW9_MSB_MEMORY_REDUNDANCY_639_608_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043b0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043b0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043b0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_LSB_MEMORY_REDUNDANCY_671_640_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_LSB_MEMORY_REDUNDANCY_671_640_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043b4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043b4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043b4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_MSB_MEMORY_REDUNDANCY_703_672_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW10_MSB_MEMORY_REDUNDANCY_703_672_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043b8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043b8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043b8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_LSB_MEMORY_REDUNDANCY_735_704_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_LSB_MEMORY_REDUNDANCY_735_704_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043bc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043bc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043bc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_MSB_MEMORY_REDUNDANCY_767_736_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW11_MSB_MEMORY_REDUNDANCY_767_736_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043c0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043c0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043c0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_LSB_MEMORY_REDUNDANCY_799_768_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_LSB_MEMORY_REDUNDANCY_799_768_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043c4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043c4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043c4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_MSB_MEMORY_REDUNDANCY_831_800_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW12_MSB_MEMORY_REDUNDANCY_831_800_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043c8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043c8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043c8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_LSB_MEMORY_REDUNDANCY_863_832_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_LSB_MEMORY_REDUNDANCY_863_832_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043cc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043cc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043cc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_MSB_MEMORY_REDUNDANCY_895_864_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW13_MSB_MEMORY_REDUNDANCY_895_864_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043d0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043d0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043d0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_LSB_MEMORY_REDUNDANCY_927_896_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_LSB_MEMORY_REDUNDANCY_927_896_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043d4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043d4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043d4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_MSB_MEMORY_REDUNDANCY_959_928_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW14_MSB_MEMORY_REDUNDANCY_959_928_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043d8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043d8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043d8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_LSB_MEMORY_REDUNDANCY_991_960_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_LSB_MEMORY_REDUNDANCY_991_960_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043dc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043dc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043dc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_MSB_MEMORY_REDUNDANCY_1023_992_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW15_MSB_MEMORY_REDUNDANCY_1023_992_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043e0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043e0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043e0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_LSB_MEMORY_REDUNDANCY_1055_1024_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_LSB_MEMORY_REDUNDANCY_1055_1024_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043e4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043e4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043e4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_MSB_MEMORY_REDUNDANCY_1087_1056_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW16_MSB_MEMORY_REDUNDANCY_1087_1056_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043e8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043e8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043e8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_LSB_MEMORY_REDUNDANCY_1119_1088_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_LSB_MEMORY_REDUNDANCY_1119_1088_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043ec) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043ec) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043ec) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_MSB_MEMORY_REDUNDANCY_1151_1120_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW17_MSB_MEMORY_REDUNDANCY_1151_1120_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043f0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043f0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043f0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_LSB_MEMORY_REDUNDANCY_1183_1152_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_LSB_MEMORY_REDUNDANCY_1183_1152_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043f4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043f4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043f4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_MSB_MEMORY_REDUNDANCY_1215_1184_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW18_MSB_MEMORY_REDUNDANCY_1215_1184_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043f8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043f8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043f8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_LSB_MEMORY_REDUNDANCY_1247_1216_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_LSB_MEMORY_REDUNDANCY_1247_1216_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000043fc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000043fc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000043fc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_MSB_MEMORY_REDUNDANCY_1279_1248_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW19_MSB_MEMORY_REDUNDANCY_1279_1248_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004400) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004400) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004400) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_LSB_MEMORY_REDUNDANCY_1311_1280_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_LSB_MEMORY_REDUNDANCY_1311_1280_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004404) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004404) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004404) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_MSB_MEMORY_REDUNDANCY_1343_1312_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW20_MSB_MEMORY_REDUNDANCY_1343_1312_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004408) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004408) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004408) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_LSB_MEMORY_REDUNDANCY_1375_1344_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_LSB_MEMORY_REDUNDANCY_1375_1344_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000440c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000440c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000440c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_MSB_MEMORY_REDUNDANCY_1407_1376_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW21_MSB_MEMORY_REDUNDANCY_1407_1376_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004410) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004410) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004410) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_LSB_MEMORY_REDUNDANCY_1439_1408_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_LSB_MEMORY_REDUNDANCY_1439_1408_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004414) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004414) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004414) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_MSB_MEMORY_REDUNDANCY_1471_1440_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW22_MSB_MEMORY_REDUNDANCY_1471_1440_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004418) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004418) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004418) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_LSB_MEMORY_REDUNDANCY_1503_1472_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_LSB_MEMORY_REDUNDANCY_1503_1472_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000441c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000441c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000441c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_MSB_MEMORY_REDUNDANCY_1535_1504_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW23_MSB_MEMORY_REDUNDANCY_1535_1504_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004420) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004420) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004420) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_LSB_MEMORY_REDUNDANCY_1567_1536_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_LSB_MEMORY_REDUNDANCY_1567_1536_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004424) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004424) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004424) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_MSB_MEMORY_REDUNDANCY_1599_1568_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW24_MSB_MEMORY_REDUNDANCY_1599_1568_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004428) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004428) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004428) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_LSB_MEMORY_REDUNDANCY_1631_1600_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_LSB_MEMORY_REDUNDANCY_1631_1600_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000442c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000442c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000442c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_MSB_MEMORY_REDUNDANCY_1663_1632_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW25_MSB_MEMORY_REDUNDANCY_1663_1632_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004430) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004430) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004430) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_LSB_MEMORY_REDUNDANCY_1695_1664_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_LSB_MEMORY_REDUNDANCY_1695_1664_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004434) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004434) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004434) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_MSB_MEMORY_REDUNDANCY_1727_1696_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW26_MSB_MEMORY_REDUNDANCY_1727_1696_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004438) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004438) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004438) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_LSB_MEMORY_REDUNDANCY_1759_1728_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_LSB_MEMORY_REDUNDANCY_1759_1728_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000443c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000443c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000443c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_MSB_MEMORY_REDUNDANCY_1791_1760_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW27_MSB_MEMORY_REDUNDANCY_1791_1760_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004440) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004440) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004440) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_LSB_MEMORY_REDUNDANCY_1823_1792_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_LSB_MEMORY_REDUNDANCY_1823_1792_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004444) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004444) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004444) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_MSB_MEMORY_REDUNDANCY_1855_1824_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW28_MSB_MEMORY_REDUNDANCY_1855_1824_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004448) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004448) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004448) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_LSB_MEMORY_REDUNDANCY_1887_1856_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_LSB_MEMORY_REDUNDANCY_1887_1856_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000444c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000444c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000444c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_MSB_MEMORY_REDUNDANCY_1919_1888_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW29_MSB_MEMORY_REDUNDANCY_1919_1888_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004450) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004450) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004450) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_LSB_MEMORY_REDUNDANCY_1951_1920_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_LSB_MEMORY_REDUNDANCY_1951_1920_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004454) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004454) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004454) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_MSB_MEMORY_REDUNDANCY_1983_1952_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW30_MSB_MEMORY_REDUNDANCY_1983_1952_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004458) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004458) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004458) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_LSB_MEMORY_REDUNDANCY_2015_1984_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_LSB_MEMORY_REDUNDANCY_2015_1984_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000445c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000445c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000445c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_MSB_MEMORY_REDUNDANCY_2047_2016_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW31_MSB_MEMORY_REDUNDANCY_2047_2016_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004460) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004460) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004460) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_LSB_MEMORY_REDUNDANCY_2079_2048_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_LSB_MEMORY_REDUNDANCY_2079_2048_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004464) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004464) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004464) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_MSB_MEMORY_REDUNDANCY_2111_2080_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW32_MSB_MEMORY_REDUNDANCY_2111_2080_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004468) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004468) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004468) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_LSB_MEMORY_REDUNDANCY_2143_2112_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_LSB_MEMORY_REDUNDANCY_2143_2112_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000446c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000446c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000446c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_MSB_MEMORY_REDUNDANCY_2175_2144_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW33_MSB_MEMORY_REDUNDANCY_2175_2144_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004470) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004470) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004470) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_LSB_MEMORY_REDUNDANCY_2207_2176_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_LSB_MEMORY_REDUNDANCY_2207_2176_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004474) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004474) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004474) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_MSB_MEMORY_REDUNDANCY_2239_2208_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW34_MSB_MEMORY_REDUNDANCY_2239_2208_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004478) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004478) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004478) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_LSB_MEMORY_REDUNDANCY_2271_2240_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_LSB_MEMORY_REDUNDANCY_2271_2240_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000447c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000447c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000447c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_MSB_MEMORY_REDUNDANCY_2303_2272_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW35_MSB_MEMORY_REDUNDANCY_2303_2272_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004480) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004480) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004480) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_LSB_MEMORY_REDUNDANCY_2335_2304_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_LSB_MEMORY_REDUNDANCY_2335_2304_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004484) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004484) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004484) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_MSB_MEMORY_REDUNDANCY_2367_2336_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW36_MSB_MEMORY_REDUNDANCY_2367_2336_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004488) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004488) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004488) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_LSB_MEMORY_REDUNDANCY_2399_2368_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_LSB_MEMORY_REDUNDANCY_2399_2368_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000448c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000448c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000448c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_MSB_MEMORY_REDUNDANCY_2431_2400_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW37_MSB_MEMORY_REDUNDANCY_2431_2400_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004490) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004490) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004490) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_LSB_MEMORY_REDUNDANCY_2463_2432_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_LSB_MEMORY_REDUNDANCY_2463_2432_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004494) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004494) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004494) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_MSB_MEMORY_REDUNDANCY_2495_2464_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW38_MSB_MEMORY_REDUNDANCY_2495_2464_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004498) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004498) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004498) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_LSB_MEMORY_REDUNDANCY_2527_2496_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_LSB_MEMORY_REDUNDANCY_2527_2496_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000449c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000449c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000449c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_MSB_MEMORY_REDUNDANCY_2559_2528_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW39_MSB_MEMORY_REDUNDANCY_2559_2528_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044a0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044a0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044a0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_LSB_MEMORY_REDUNDANCY_2591_2560_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_LSB_MEMORY_REDUNDANCY_2591_2560_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044a4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044a4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044a4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_MSB_MEMORY_REDUNDANCY_2623_2592_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW40_MSB_MEMORY_REDUNDANCY_2623_2592_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044a8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044a8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044a8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_LSB_MEMORY_REDUNDANCY_2655_2624_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_LSB_MEMORY_REDUNDANCY_2655_2624_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044ac) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044ac) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044ac) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_MSB_MEMORY_REDUNDANCY_2687_2656_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW41_MSB_MEMORY_REDUNDANCY_2687_2656_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044b0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044b0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044b0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_LSB_MEMORY_REDUNDANCY_2719_2688_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_LSB_MEMORY_REDUNDANCY_2719_2688_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044b4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044b4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044b4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_MSB_MEMORY_REDUNDANCY_2751_2720_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW42_MSB_MEMORY_REDUNDANCY_2751_2720_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044b8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044b8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044b8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_LSB_MEMORY_REDUNDANCY_2783_2752_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_LSB_MEMORY_REDUNDANCY_2783_2752_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044bc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044bc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044bc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_MSB_MEMORY_REDUNDANCY_2815_2784_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW43_MSB_MEMORY_REDUNDANCY_2815_2784_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044c0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044c0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044c0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_LSB_MEMORY_REDUNDANCY_2847_2816_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_LSB_MEMORY_REDUNDANCY_2847_2816_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044c4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044c4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044c4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_MSB_MEMORY_REDUNDANCY_2879_2848_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW44_MSB_MEMORY_REDUNDANCY_2879_2848_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044c8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044c8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044c8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_LSB_MEMORY_REDUNDANCY_2911_2880_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_LSB_MEMORY_REDUNDANCY_2911_2880_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044cc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044cc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044cc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_MSB_MEMORY_REDUNDANCY_2943_2912_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW45_MSB_MEMORY_REDUNDANCY_2943_2912_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044d0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044d0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044d0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_LSB_MEMORY_REDUNDANCY_2975_2944_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_LSB_MEMORY_REDUNDANCY_2975_2944_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044d4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044d4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044d4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_MSB_MEMORY_REDUNDANCY_3007_2976_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW46_MSB_MEMORY_REDUNDANCY_3007_2976_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044d8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044d8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044d8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_LSB_MEMORY_REDUNDANCY_3039_3008_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_LSB_MEMORY_REDUNDANCY_3039_3008_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044dc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044dc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044dc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_MSB_MEMORY_REDUNDANCY_3071_3040_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW47_MSB_MEMORY_REDUNDANCY_3071_3040_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044e0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044e0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044e0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_LSB_MEMORY_REDUNDANCY_3103_3072_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_LSB_MEMORY_REDUNDANCY_3103_3072_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044e4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044e4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044e4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_MSB_MEMORY_REDUNDANCY_3135_3104_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW48_MSB_MEMORY_REDUNDANCY_3135_3104_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044e8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044e8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044e8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_LSB_MEMORY_REDUNDANCY_3167_3136_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_LSB_MEMORY_REDUNDANCY_3167_3136_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044ec) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044ec) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044ec) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_MSB_MEMORY_REDUNDANCY_3199_3168_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW49_MSB_MEMORY_REDUNDANCY_3199_3168_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044f0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044f0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044f0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_LSB_MEMORY_REDUNDANCY_3231_3200_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_LSB_MEMORY_REDUNDANCY_3231_3200_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044f4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044f4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044f4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_MSB_MEMORY_REDUNDANCY_3263_3232_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW50_MSB_MEMORY_REDUNDANCY_3263_3232_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044f8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044f8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044f8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_LSB_MEMORY_REDUNDANCY_3295_3264_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_LSB_MEMORY_REDUNDANCY_3295_3264_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000044fc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000044fc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000044fc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_MSB_MEMORY_REDUNDANCY_3327_3296_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW51_MSB_MEMORY_REDUNDANCY_3327_3296_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004500) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004500) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004500) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_LSB_MEMORY_REDUNDANCY_3359_3328_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_LSB_MEMORY_REDUNDANCY_3359_3328_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004504) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004504) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004504) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_MSB_MEMORY_REDUNDANCY_3391_3360_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW52_MSB_MEMORY_REDUNDANCY_3391_3360_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004508) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004508) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004508) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_LSB_MEMORY_REDUNDANCY_3423_3392_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_LSB_MEMORY_REDUNDANCY_3423_3392_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000450c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000450c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000450c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_MSB_MEMORY_REDUNDANCY_3455_3424_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW53_MSB_MEMORY_REDUNDANCY_3455_3424_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004510) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004510) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004510) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_LSB_MEMORY_REDUNDANCY_3487_3456_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_LSB_MEMORY_REDUNDANCY_3487_3456_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004514) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004514) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004514) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_MSB_MEMORY_REDUNDANCY_3519_3488_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW54_MSB_MEMORY_REDUNDANCY_3519_3488_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004518) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004518) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004518) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_LSB_MEMORY_REDUNDANCY_3551_3520_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_LSB_MEMORY_REDUNDANCY_3551_3520_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000451c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000451c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000451c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_MSB_MEMORY_REDUNDANCY_3583_3552_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW55_MSB_MEMORY_REDUNDANCY_3583_3552_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004520) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004520) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004520) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_LSB_MEMORY_REDUNDANCY_3615_3584_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_LSB_MEMORY_REDUNDANCY_3615_3584_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004524) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004524) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004524) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_MSB_MEMORY_REDUNDANCY_3647_3616_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW56_MSB_MEMORY_REDUNDANCY_3647_3616_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004528) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004528) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004528) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_LSB_MEMORY_REDUNDANCY_3679_3648_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_LSB_MEMORY_REDUNDANCY_3679_3648_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000452c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000452c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000452c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_MSB_MEMORY_REDUNDANCY_3711_3680_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW57_MSB_MEMORY_REDUNDANCY_3711_3680_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004530) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004530) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004530) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_LSB_MEMORY_REDUNDANCY_3743_3712_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_LSB_MEMORY_REDUNDANCY_3743_3712_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004534) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004534) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004534) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_MSB_MEMORY_REDUNDANCY_3775_3744_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW58_MSB_MEMORY_REDUNDANCY_3775_3744_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004538) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004538) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004538) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_LSB_MEMORY_REDUNDANCY_3807_3776_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_LSB_MEMORY_REDUNDANCY_3807_3776_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000453c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000453c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000453c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_MSB_MEMORY_REDUNDANCY_3839_3808_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW59_MSB_MEMORY_REDUNDANCY_3839_3808_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004540) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004540) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004540) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_LSB_MEMORY_REDUNDANCY_3871_3840_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_LSB_MEMORY_REDUNDANCY_3871_3840_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004544) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004544) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004544) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_MSB_MEMORY_REDUNDANCY_3903_3872_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW60_MSB_MEMORY_REDUNDANCY_3903_3872_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004548) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004548) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004548) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_LSB_MEMORY_REDUNDANCY_3935_3904_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_LSB_MEMORY_REDUNDANCY_3935_3904_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000454c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000454c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000454c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_MSB_MEMORY_REDUNDANCY_3967_3936_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW61_MSB_MEMORY_REDUNDANCY_3967_3936_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004550) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004550) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004550) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_LSB_MEMORY_REDUNDANCY_3999_3968_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_LSB_MEMORY_REDUNDANCY_3999_3968_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004554) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004554) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004554) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_MSB_MEMORY_REDUNDANCY_4031_4000_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW62_MSB_MEMORY_REDUNDANCY_4031_4000_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004558) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004558) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004558) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_LSB_MEMORY_REDUNDANCY_4063_4032_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_LSB_MEMORY_REDUNDANCY_4063_4032_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000455c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000455c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000455c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_MSB_MEMORY_REDUNDANCY_4095_4064_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW63_MSB_MEMORY_REDUNDANCY_4095_4064_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004560) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004560) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004560) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_LSB_MEMORY_REDUNDANCY_4127_4096_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_LSB_MEMORY_REDUNDANCY_4127_4096_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004564) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004564) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004564) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_MSB_MEMORY_REDUNDANCY_4159_4128_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW64_MSB_MEMORY_REDUNDANCY_4159_4128_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004568) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004568) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004568) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_LSB_MEMORY_REDUNDANCY_4191_4160_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_LSB_MEMORY_REDUNDANCY_4191_4160_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000456c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000456c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000456c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_MSB_MEMORY_REDUNDANCY_4223_4192_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW65_MSB_MEMORY_REDUNDANCY_4223_4192_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004570) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004570) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004570) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_LSB_MEMORY_REDUNDANCY_4255_4224_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_LSB_MEMORY_REDUNDANCY_4255_4224_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004574) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004574) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004574) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_MSB_MEMORY_REDUNDANCY_4287_4256_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW66_MSB_MEMORY_REDUNDANCY_4287_4256_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004578) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004578) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004578) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_LSB_MEMORY_REDUNDANCY_4319_4288_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_LSB_MEMORY_REDUNDANCY_4319_4288_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000457c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000457c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000457c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_MSB_MEMORY_REDUNDANCY_4351_4320_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW67_MSB_MEMORY_REDUNDANCY_4351_4320_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004580) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004580) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004580) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_LSB_MEMORY_REDUNDANCY_4383_4352_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_LSB_MEMORY_REDUNDANCY_4383_4352_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004584) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004584) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004584) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_MSB_MEMORY_REDUNDANCY_4415_4384_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW68_MSB_MEMORY_REDUNDANCY_4415_4384_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004588) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004588) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004588) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_LSB_MEMORY_REDUNDANCY_4447_4416_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_LSB_MEMORY_REDUNDANCY_4447_4416_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000458c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000458c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000458c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_MSB_MEMORY_REDUNDANCY_4479_4448_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW69_MSB_MEMORY_REDUNDANCY_4479_4448_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004590) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004590) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004590) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_LSB_MEMORY_REDUNDANCY_4511_4480_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_LSB_MEMORY_REDUNDANCY_4511_4480_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004594) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004594) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004594) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_MSB_MEMORY_REDUNDANCY_4543_4512_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW70_MSB_MEMORY_REDUNDANCY_4543_4512_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004598) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004598) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004598) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_LSB_MEMORY_REDUNDANCY_4575_4544_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_LSB_MEMORY_REDUNDANCY_4575_4544_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000459c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000459c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000459c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_MSB_MEMORY_REDUNDANCY_4607_4576_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW71_MSB_MEMORY_REDUNDANCY_4607_4576_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045a0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045a0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045a0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_LSB_MEMORY_REDUNDANCY_4639_4608_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_LSB_MEMORY_REDUNDANCY_4639_4608_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045a4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045a4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045a4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_MSB_MEMORY_REDUNDANCY_4671_4640_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW72_MSB_MEMORY_REDUNDANCY_4671_4640_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045a8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045a8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045a8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_LSB_MEMORY_REDUNDANCY_4703_4672_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_LSB_MEMORY_REDUNDANCY_4703_4672_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045ac) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045ac) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045ac) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_MSB_MEMORY_REDUNDANCY_4735_4704_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW73_MSB_MEMORY_REDUNDANCY_4735_4704_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045b0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045b0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045b0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_LSB_MEMORY_REDUNDANCY_4767_4736_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_LSB_MEMORY_REDUNDANCY_4767_4736_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045b4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045b4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045b4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_MSB_MEMORY_REDUNDANCY_4799_4768_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW74_MSB_MEMORY_REDUNDANCY_4799_4768_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045b8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045b8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045b8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_LSB_MEMORY_REDUNDANCY_4831_4800_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_LSB_MEMORY_REDUNDANCY_4831_4800_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045bc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045bc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045bc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_MSB_MEMORY_REDUNDANCY_4863_4832_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW75_MSB_MEMORY_REDUNDANCY_4863_4832_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045c0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045c0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045c0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_LSB_MEMORY_REDUNDANCY_4895_4864_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_LSB_MEMORY_REDUNDANCY_4895_4864_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045c4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045c4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045c4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_MSB_MEMORY_REDUNDANCY_4927_4896_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW76_MSB_MEMORY_REDUNDANCY_4927_4896_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045c8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045c8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045c8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_LSB_MEMORY_REDUNDANCY_4959_4928_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_LSB_MEMORY_REDUNDANCY_4959_4928_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045cc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045cc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045cc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_MSB_MEMORY_REDUNDANCY_4991_4960_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW77_MSB_MEMORY_REDUNDANCY_4991_4960_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045d0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045d0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045d0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_LSB_MEMORY_REDUNDANCY_5023_4992_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_LSB_MEMORY_REDUNDANCY_5023_4992_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045d4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045d4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045d4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_MSB_MEMORY_REDUNDANCY_5055_5024_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW78_MSB_MEMORY_REDUNDANCY_5055_5024_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045d8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045d8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045d8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_LSB_MEMORY_REDUNDANCY_5087_5056_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_LSB_MEMORY_REDUNDANCY_5087_5056_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045dc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045dc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045dc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_MSB_MEMORY_REDUNDANCY_5119_5088_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW79_MSB_MEMORY_REDUNDANCY_5119_5088_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045e0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045e0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045e0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_LSB_MEMORY_REDUNDANCY_5151_5120_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_LSB_MEMORY_REDUNDANCY_5151_5120_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045e4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045e4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045e4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_MSB_MEMORY_REDUNDANCY_5183_5152_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW80_MSB_MEMORY_REDUNDANCY_5183_5152_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045e8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045e8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045e8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_LSB_MEMORY_REDUNDANCY_5215_5184_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_LSB_MEMORY_REDUNDANCY_5215_5184_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045ec) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045ec) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045ec) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_MSB_MEMORY_REDUNDANCY_5247_5216_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW81_MSB_MEMORY_REDUNDANCY_5247_5216_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045f0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045f0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045f0) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_LSB_MEMORY_REDUNDANCY_5279_5248_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_LSB_MEMORY_REDUNDANCY_5279_5248_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045f4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045f4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045f4) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_MSB_MEMORY_REDUNDANCY_5311_5280_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW82_MSB_MEMORY_REDUNDANCY_5311_5280_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045f8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045f8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045f8) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_LSB_MEMORY_REDUNDANCY_5343_5312_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_LSB_MEMORY_REDUNDANCY_5343_5312_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000045fc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000045fc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000045fc) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_MSB_MEMORY_REDUNDANCY_5375_5344_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW83_MSB_MEMORY_REDUNDANCY_5375_5344_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004600) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004600) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004600) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_LSB_MEMORY_ACCELERATION_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_LSB_MEMORY_ACCELERATION_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004604) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004604) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004604) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_MSB_MEMORY_ACCELERATION_63_32_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW84_MSB_MEMORY_ACCELERATION_63_32_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004608) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004608) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004608) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_LSB_MEMORY_ACCELERATION_95_64_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_LSB_MEMORY_ACCELERATION_95_64_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000460c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000460c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000460c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_MSB_MEMORY_ACCELERATION_127_96_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW85_MSB_MEMORY_ACCELERATION_127_96_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004610) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004610) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004610) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_LSB_MEMORY_ACCELERATION_159_128_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_LSB_MEMORY_ACCELERATION_159_128_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004614) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004614) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004614) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_MSB_MEMORY_ACCELERATION_191_160_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW86_MSB_MEMORY_ACCELERATION_191_160_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004618) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004618) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004618) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_LSB_MEMORY_ACCELERATION_223_192_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_LSB_MEMORY_ACCELERATION_223_192_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000461c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000461c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000461c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_MSB_MEMORY_ACCELERATION_255_224_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW87_MSB_MEMORY_ACCELERATION_255_224_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004620) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004620) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004620) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_LSB_MEMORY_ACCELERATION_287_256_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_LSB_MEMORY_ACCELERATION_287_256_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004624) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004624) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004624) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_MSB_MEMORY_ACCELERATION_319_288_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW88_MSB_MEMORY_ACCELERATION_319_288_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004628) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004628) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004628) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_LSB_MEMORY_ACCELERATION_351_320_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_LSB_MEMORY_ACCELERATION_351_320_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000462c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000462c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000462c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_MSB_MEMORY_ACCELERATION_383_352_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW89_MSB_MEMORY_ACCELERATION_383_352_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004630) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004630) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004630) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_LSB_MEMORY_ACCELERATION_415_384_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_LSB_MEMORY_ACCELERATION_415_384_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004634) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004634) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004634) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_MSB_MEMORY_ACCELERATION_447_416_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW90_MSB_MEMORY_ACCELERATION_447_416_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004638) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004638) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004638) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_LSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_LSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_LSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_LSB_MEMORY_ACCELERATION_479_448_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_LSB_MEMORY_ACCELERATION_479_448_SHFT 0x0 #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000463c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000463c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000463c) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_MSB_IN \ in_dword(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_MSB_ADDR) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_MSB_ADDR, m) #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_MSB_MEMORY_ACCELERATION_511_480_BMSK 0xffffffff #define HWIO_QFPROM_CORR_MEMORY_CONFIGURATION_ROW91_MSB_MEMORY_ACCELERATION_511_480_SHFT 0x0 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004640) #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004640) #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004640) #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_IN \ in_dword(HWIO_QFPROM_CORR_QC_SPARE_20_LSB_ADDR) #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_20_LSB_ADDR, m) #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_RSVD_BMSK 0xfffc0000 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_RSVD_SHFT 0x12 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_RET_FT_BMSK 0x20000 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_RET_FT_SHFT 0x11 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_RET_WS_BMSK 0x10000 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_RET_WS_SHFT 0x10 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_IDDQ_FT_BMSK 0x8000 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_IDDQ_FT_SHFT 0xf #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_IDDQ_WS_BMSK 0x4000 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_IDDQ_WS_SHFT 0xe #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_PONGO_FT_BMSK 0x2000 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_PONGO_FT_SHFT 0xd #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_PONGO_WS_BMSK 0x1000 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_PONGO_WS_SHFT 0xc #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_Q6_FT_BMSK 0x800 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_Q6_FT_SHFT 0xb #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_Q6_WS_BMSK 0x400 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_Q6_WS_SHFT 0xa #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_TSENS_FT_BMSK 0x200 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_TSENS_FT_SHFT 0x9 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_TSENS_WS_BMSK 0x100 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_TSENS_WS_SHFT 0x8 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_MSIP_FT_BMSK 0x80 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_MSIP_FT_SHFT 0x7 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_MSIP_WS_BMSK 0x40 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_MSIP_WS_SHFT 0x6 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_HSIO_FT_BMSK 0x20 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_HSIO_FT_SHFT 0x5 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_HSIO_WS_BMSK 0x10 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_HSIO_WS_SHFT 0x4 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_CPR_FT_BMSK 0x8 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_CPR_FT_SHFT 0x3 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_CPR_WS_BMSK 0x4 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_CPR_WS_SHFT 0x2 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_QFPROM_FT_BMSK 0x2 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_QFPROM_FT_SHFT 0x1 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_QFPROM_WS_BMSK 0x1 #define HWIO_QFPROM_CORR_QC_SPARE_20_LSB_QFPROM_WS_SHFT 0x0 #define HWIO_QFPROM_CORR_QC_SPARE_20_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004644) #define HWIO_QFPROM_CORR_QC_SPARE_20_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004644) #define HWIO_QFPROM_CORR_QC_SPARE_20_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004644) #define HWIO_QFPROM_CORR_QC_SPARE_20_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_QC_SPARE_20_MSB_IN \ in_dword(HWIO_QFPROM_CORR_QC_SPARE_20_MSB_ADDR) #define HWIO_QFPROM_CORR_QC_SPARE_20_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_20_MSB_ADDR, m) #define HWIO_QFPROM_CORR_QC_SPARE_20_MSB_RSVD_BMSK 0xffffff #define HWIO_QFPROM_CORR_QC_SPARE_20_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_QC_SPARE_21_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004648) #define HWIO_QFPROM_CORR_QC_SPARE_21_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004648) #define HWIO_QFPROM_CORR_QC_SPARE_21_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004648) #define HWIO_QFPROM_CORR_QC_SPARE_21_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_QC_SPARE_21_LSB_IN \ in_dword(HWIO_QFPROM_CORR_QC_SPARE_21_LSB_ADDR) #define HWIO_QFPROM_CORR_QC_SPARE_21_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_21_LSB_ADDR, m) #define HWIO_QFPROM_CORR_QC_SPARE_21_LSB_GPU_ISENS_CAL_BMSK 0xffffffff #define HWIO_QFPROM_CORR_QC_SPARE_21_LSB_GPU_ISENS_CAL_SHFT 0x0 #define HWIO_QFPROM_CORR_QC_SPARE_21_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000464c) #define HWIO_QFPROM_CORR_QC_SPARE_21_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000464c) #define HWIO_QFPROM_CORR_QC_SPARE_21_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000464c) #define HWIO_QFPROM_CORR_QC_SPARE_21_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_QC_SPARE_21_MSB_IN \ in_dword(HWIO_QFPROM_CORR_QC_SPARE_21_MSB_ADDR) #define HWIO_QFPROM_CORR_QC_SPARE_21_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_QC_SPARE_21_MSB_ADDR, m) #define HWIO_QFPROM_CORR_QC_SPARE_21_MSB_RSVD_BMSK 0xffffff #define HWIO_QFPROM_CORR_QC_SPARE_21_MSB_RSVD_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004650) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004650) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004650) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_OEM_IMAGE_ENCRYPTION_KEY_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_LSB_OEM_IMAGE_ENCRYPTION_KEY_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004654) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004654) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004654) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_OEM_IMAGE_ENCRYPTION_KEY_55_32_BMSK 0xffffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW0_MSB_OEM_IMAGE_ENCRYPTION_KEY_55_32_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004658) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004658) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004658) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_OEM_IMAGE_ENCRYPTION_KEY_87_56_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_LSB_OEM_IMAGE_ENCRYPTION_KEY_87_56_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000465c) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000465c) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000465c) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_OEM_IMAGE_ENCRYPTION_KEY_111_88_BMSK 0xffffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW1_MSB_OEM_IMAGE_ENCRYPTION_KEY_111_88_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004660) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004660) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004660) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_SPARE_188_16_15_0_BMSK 0xffff0000 #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_SPARE_188_16_15_0_SHFT 0x10 #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_OEM_IMAGE_ENCRYPTION_KEY_127_112_BMSK 0xffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_LSB_OEM_IMAGE_ENCRYPTION_KEY_127_112_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004664) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004664) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004664) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_SPARE_188_16_39_16_BMSK 0xffffff #define HWIO_QFPROM_CORR_OEM_IMAGE_ENCRYPTION_KEY_ROW2_MSB_SPARE_188_16_39_16_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004668) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004668) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004668) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_RESERVED_BMSK 0x80000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_RESERVED_SHFT 0x1f #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_USE_SERIAL_NUM_BMSK 0x40000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_USE_SERIAL_NUM_SHFT 0x1e #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_AUTH_EN_BMSK 0x20000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_AUTH_EN_SHFT 0x1d #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_PK_HASH_IN_FUSE_BMSK 0x10000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_PK_HASH_IN_FUSE_SHFT 0x1c #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX3_BMSK 0x8000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX3_SHFT 0x1b #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX2_BMSK 0x4000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX2_SHFT 0x1a #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX1_BMSK 0x2000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX1_SHFT 0x19 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX0_BMSK 0x1000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT4_ROM_PK_HASH_IDX0_SHFT 0x18 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_RESERVED_BMSK 0x800000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_RESERVED_SHFT 0x17 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_USE_SERIAL_NUM_BMSK 0x400000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_USE_SERIAL_NUM_SHFT 0x16 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_AUTH_EN_BMSK 0x200000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_AUTH_EN_SHFT 0x15 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_PK_HASH_IN_FUSE_BMSK 0x100000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_PK_HASH_IN_FUSE_SHFT 0x14 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX3_BMSK 0x80000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX3_SHFT 0x13 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX2_BMSK 0x40000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX2_SHFT 0x12 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX1_BMSK 0x20000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX1_SHFT 0x11 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX0_BMSK 0x10000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT3_ROM_PK_HASH_IDX0_SHFT 0x10 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_RESERVED_BMSK 0x8000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_RESERVED_SHFT 0xf #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_USE_SERIAL_NUM_BMSK 0x4000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_USE_SERIAL_NUM_SHFT 0xe #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_AUTH_EN_BMSK 0x2000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_AUTH_EN_SHFT 0xd #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_PK_HASH_IN_FUSE_BMSK 0x1000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_PK_HASH_IN_FUSE_SHFT 0xc #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX3_BMSK 0x800 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX3_SHFT 0xb #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX2_BMSK 0x400 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX2_SHFT 0xa #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX1_BMSK 0x200 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX1_SHFT 0x9 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX0_BMSK 0x100 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT2_ROM_PK_HASH_IDX0_SHFT 0x8 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_RESERVED_BMSK 0x80 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_RESERVED_SHFT 0x7 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_USE_SERIAL_NUM_BMSK 0x40 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_USE_SERIAL_NUM_SHFT 0x6 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_AUTH_EN_BMSK 0x20 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_AUTH_EN_SHFT 0x5 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_PK_HASH_IN_FUSE_BMSK 0x10 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_PK_HASH_IN_FUSE_SHFT 0x4 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX3_BMSK 0x8 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX3_SHFT 0x3 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX2_BMSK 0x4 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX2_SHFT 0x2 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX1_BMSK 0x2 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX1_SHFT 0x1 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX0_BMSK 0x1 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_LSB_OEM_SECURE_BOOT1_ROM_PK_HASH_IDX0_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000466c) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000466c) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000466c) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_RESERVED_BMSK 0x800000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_RESERVED_SHFT 0x17 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_USE_SERIAL_NUM_BMSK 0x400000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_USE_SERIAL_NUM_SHFT 0x16 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_AUTH_EN_BMSK 0x200000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_AUTH_EN_SHFT 0x15 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_PK_HASH_IN_FUSE_BMSK 0x100000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_PK_HASH_IN_FUSE_SHFT 0x14 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX3_BMSK 0x80000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX3_SHFT 0x13 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX2_BMSK 0x40000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX2_SHFT 0x12 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX1_BMSK 0x20000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX1_SHFT 0x11 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX0_BMSK 0x10000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT7_ROM_PK_HASH_IDX0_SHFT 0x10 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_RESERVED_BMSK 0x8000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_RESERVED_SHFT 0xf #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_USE_SERIAL_NUM_BMSK 0x4000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_USE_SERIAL_NUM_SHFT 0xe #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_AUTH_EN_BMSK 0x2000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_AUTH_EN_SHFT 0xd #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_PK_HASH_IN_FUSE_BMSK 0x1000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_PK_HASH_IN_FUSE_SHFT 0xc #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX3_BMSK 0x800 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX3_SHFT 0xb #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX2_BMSK 0x400 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX2_SHFT 0xa #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX1_BMSK 0x200 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX1_SHFT 0x9 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX0_BMSK 0x100 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT6_ROM_PK_HASH_IDX0_SHFT 0x8 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_RESERVED_BMSK 0x80 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_RESERVED_SHFT 0x7 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_USE_SERIAL_NUM_BMSK 0x40 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_USE_SERIAL_NUM_SHFT 0x6 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_AUTH_EN_BMSK 0x20 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_AUTH_EN_SHFT 0x5 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_PK_HASH_IN_FUSE_BMSK 0x10 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_PK_HASH_IN_FUSE_SHFT 0x4 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX3_BMSK 0x8 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX3_SHFT 0x3 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX2_BMSK 0x4 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX2_SHFT 0x2 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX1_BMSK 0x2 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX1_SHFT 0x1 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX0_BMSK 0x1 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW0_MSB_OEM_SECURE_BOOT5_ROM_PK_HASH_IDX0_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004670) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004670) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004670) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_RESERVED_BMSK 0x80000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_RESERVED_SHFT 0x1f #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_USE_SERIAL_NUM_BMSK 0x40000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_USE_SERIAL_NUM_SHFT 0x1e #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_AUTH_EN_BMSK 0x20000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_AUTH_EN_SHFT 0x1d #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_PK_HASH_IN_FUSE_BMSK 0x10000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_PK_HASH_IN_FUSE_SHFT 0x1c #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX3_BMSK 0x8000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX3_SHFT 0x1b #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX2_BMSK 0x4000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX2_SHFT 0x1a #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX1_BMSK 0x2000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX1_SHFT 0x19 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX0_BMSK 0x1000000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT11_ROM_PK_HASH_IDX0_SHFT 0x18 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_RESERVED_BMSK 0x800000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_RESERVED_SHFT 0x17 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_USE_SERIAL_NUM_BMSK 0x400000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_USE_SERIAL_NUM_SHFT 0x16 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_AUTH_EN_BMSK 0x200000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_AUTH_EN_SHFT 0x15 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_PK_HASH_IN_FUSE_BMSK 0x100000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_PK_HASH_IN_FUSE_SHFT 0x14 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX3_BMSK 0x80000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX3_SHFT 0x13 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX2_BMSK 0x40000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX2_SHFT 0x12 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX1_BMSK 0x20000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX1_SHFT 0x11 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX0_BMSK 0x10000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT10_ROM_PK_HASH_IDX0_SHFT 0x10 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_RESERVED_BMSK 0x8000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_RESERVED_SHFT 0xf #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_USE_SERIAL_NUM_BMSK 0x4000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_USE_SERIAL_NUM_SHFT 0xe #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_AUTH_EN_BMSK 0x2000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_AUTH_EN_SHFT 0xd #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_PK_HASH_IN_FUSE_BMSK 0x1000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_PK_HASH_IN_FUSE_SHFT 0xc #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX3_BMSK 0x800 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX3_SHFT 0xb #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX2_BMSK 0x400 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX2_SHFT 0xa #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX1_BMSK 0x200 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX1_SHFT 0x9 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX0_BMSK 0x100 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT9_ROM_PK_HASH_IDX0_SHFT 0x8 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_RESERVED_BMSK 0x80 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_RESERVED_SHFT 0x7 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_USE_SERIAL_NUM_BMSK 0x40 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_USE_SERIAL_NUM_SHFT 0x6 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_AUTH_EN_BMSK 0x20 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_AUTH_EN_SHFT 0x5 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_PK_HASH_IN_FUSE_BMSK 0x10 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_PK_HASH_IN_FUSE_SHFT 0x4 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX3_BMSK 0x8 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX3_SHFT 0x3 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX2_BMSK 0x4 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX2_SHFT 0x2 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX1_BMSK 0x2 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX1_SHFT 0x1 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX0_BMSK 0x1 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_LSB_OEM_SECURE_BOOT8_ROM_PK_HASH_IDX0_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004674) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004674) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004674) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_RESERVED_BMSK 0x800000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_RESERVED_SHFT 0x17 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_USE_SERIAL_NUM_BMSK 0x400000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_USE_SERIAL_NUM_SHFT 0x16 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_AUTH_EN_BMSK 0x200000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_AUTH_EN_SHFT 0x15 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_PK_HASH_IN_FUSE_BMSK 0x100000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_PK_HASH_IN_FUSE_SHFT 0x14 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX3_BMSK 0x80000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX3_SHFT 0x13 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX2_BMSK 0x40000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX2_SHFT 0x12 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX1_BMSK 0x20000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX1_SHFT 0x11 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX0_BMSK 0x10000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT14_ROM_PK_HASH_IDX0_SHFT 0x10 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_RESERVED_BMSK 0x8000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_RESERVED_SHFT 0xf #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_USE_SERIAL_NUM_BMSK 0x4000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_USE_SERIAL_NUM_SHFT 0xe #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_AUTH_EN_BMSK 0x2000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_AUTH_EN_SHFT 0xd #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_PK_HASH_IN_FUSE_BMSK 0x1000 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_PK_HASH_IN_FUSE_SHFT 0xc #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX3_BMSK 0x800 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX3_SHFT 0xb #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX2_BMSK 0x400 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX2_SHFT 0xa #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX1_BMSK 0x200 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX1_SHFT 0x9 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX0_BMSK 0x100 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT13_ROM_PK_HASH_IDX0_SHFT 0x8 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_RESERVED_BMSK 0x80 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_RESERVED_SHFT 0x7 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_USE_SERIAL_NUM_BMSK 0x40 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_USE_SERIAL_NUM_SHFT 0x6 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_AUTH_EN_BMSK 0x20 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_AUTH_EN_SHFT 0x5 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_PK_HASH_IN_FUSE_BMSK 0x10 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_PK_HASH_IN_FUSE_SHFT 0x4 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX3_BMSK 0x8 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX3_SHFT 0x3 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX2_BMSK 0x4 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX2_SHFT 0x2 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX1_BMSK 0x2 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX1_SHFT 0x1 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX0_BMSK 0x1 #define HWIO_QFPROM_CORR_OEM_SECURE_BOOT_ROW1_MSB_OEM_SECURE_BOOT12_ROM_PK_HASH_IDX0_SHFT 0x0 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004678) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004678) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004678) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_LSB_SEC_KEY_DERIVATION_KEY_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_LSB_SEC_KEY_DERIVATION_KEY_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000467c) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000467c) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000467c) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_MSB_SEC_KEY_DERIVATION_KEY_55_32_BMSK 0xffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW0_MSB_SEC_KEY_DERIVATION_KEY_55_32_SHFT 0x0 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004680) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004680) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004680) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_LSB_SEC_KEY_DERIVATION_KEY_87_56_BMSK 0xffffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_LSB_SEC_KEY_DERIVATION_KEY_87_56_SHFT 0x0 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004684) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004684) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004684) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_MSB_SEC_KEY_DERIVATION_KEY_111_88_BMSK 0xffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW1_MSB_SEC_KEY_DERIVATION_KEY_111_88_SHFT 0x0 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004688) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004688) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004688) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_LSB_SEC_KEY_DERIVATION_KEY_143_112_BMSK 0xffffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_LSB_SEC_KEY_DERIVATION_KEY_143_112_SHFT 0x0 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000468c) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000468c) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000468c) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_MSB_SEC_KEY_DERIVATION_KEY_167_144_BMSK 0xffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW2_MSB_SEC_KEY_DERIVATION_KEY_167_144_SHFT 0x0 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004690) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004690) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004690) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_LSB_ADDR) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_LSB_SEC_KEY_DERIVATION_KEY_199_168_BMSK 0xffffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_LSB_SEC_KEY_DERIVATION_KEY_199_168_SHFT 0x0 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004694) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004694) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004694) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_MSB_ADDR) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_MSB_SEC_KEY_DERIVATION_KEY_223_200_BMSK 0xffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW3_MSB_SEC_KEY_DERIVATION_KEY_223_200_SHFT 0x0 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004698) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004698) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004698) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_SEC_KEY_DERIVATION_KEY_255_224_BMSK 0xffffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_LSB_SEC_KEY_DERIVATION_KEY_255_224_SHFT 0x0 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000469c) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000469c) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000469c) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_55_BMSK 0x800000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_55_SHFT 0x17 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_54_BMSK 0x400000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_54_SHFT 0x16 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_53_BMSK 0x200000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_53_SHFT 0x15 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_52_BMSK 0x100000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_52_SHFT 0x14 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_51_BMSK 0x80000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_51_SHFT 0x13 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_50_BMSK 0x40000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_50_SHFT 0x12 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_49_BMSK 0x20000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_49_SHFT 0x11 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_48_BMSK 0x10000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_48_SHFT 0x10 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_47_BMSK 0x8000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_47_SHFT 0xf #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_46_BMSK 0x4000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_46_SHFT 0xe #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_45_BMSK 0x2000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_45_SHFT 0xd #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_44_BMSK 0x1000 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_44_SHFT 0xc #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_43_BMSK 0x800 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_43_SHFT 0xb #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_42_BMSK 0x400 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_42_SHFT 0xa #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_41_BMSK 0x200 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_41_SHFT 0x9 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_40_BMSK 0x100 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_40_SHFT 0x8 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_39_BMSK 0x80 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_39_SHFT 0x7 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_38_BMSK 0x40 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_38_SHFT 0x6 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_37_BMSK 0x20 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_37_SHFT 0x5 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_36_BMSK 0x10 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_36_SHFT 0x4 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_35_BMSK 0x8 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_35_SHFT 0x3 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_34_BMSK 0x4 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_34_SHFT 0x2 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_33_BMSK 0x2 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_33_SHFT 0x1 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_32_BMSK 0x1 #define HWIO_QFPROM_CORR_SEC_KEY_DERIVATION_KEY_ROW4_MSB_SPARE_187_32_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046a0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046a0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046a0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_LSB_BOOT_PATCH_0_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_LSB_BOOT_PATCH_0_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046a4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046a4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046a4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_BOOT_PATCH_0_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_BOOT_PATCH_0_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_BOOT_PATCH_0_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW0_MSB_BOOT_PATCH_0_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046a8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046a8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046a8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_LSB_BOOT_PATCH_1_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_LSB_BOOT_PATCH_1_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046ac) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046ac) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046ac) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_BOOT_PATCH_1_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_BOOT_PATCH_1_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_BOOT_PATCH_1_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW1_MSB_BOOT_PATCH_1_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046b0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046b0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046b0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_LSB_BOOT_PATCH_2_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_LSB_BOOT_PATCH_2_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046b4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046b4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046b4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_BOOT_PATCH_2_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_BOOT_PATCH_2_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_BOOT_PATCH_2_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW2_MSB_BOOT_PATCH_2_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046b8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046b8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046b8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_LSB_BOOT_PATCH_3_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_LSB_BOOT_PATCH_3_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046bc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046bc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046bc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_BOOT_PATCH_3_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_BOOT_PATCH_3_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_BOOT_PATCH_3_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW3_MSB_BOOT_PATCH_3_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046c0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046c0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046c0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_LSB_BOOT_PATCH_4_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_LSB_BOOT_PATCH_4_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046c4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046c4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046c4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_BOOT_PATCH_4_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_BOOT_PATCH_4_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_BOOT_PATCH_4_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW4_MSB_BOOT_PATCH_4_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046c8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046c8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046c8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_LSB_BOOT_PATCH_5_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_LSB_BOOT_PATCH_5_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046cc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046cc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046cc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_BOOT_PATCH_5_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_BOOT_PATCH_5_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_BOOT_PATCH_5_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW5_MSB_BOOT_PATCH_5_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046d0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046d0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046d0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_LSB_BOOT_PATCH_6_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_LSB_BOOT_PATCH_6_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046d4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046d4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046d4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_BOOT_PATCH_6_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_BOOT_PATCH_6_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_BOOT_PATCH_6_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW6_MSB_BOOT_PATCH_6_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046d8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046d8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046d8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_LSB_BOOT_PATCH_7_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_LSB_BOOT_PATCH_7_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046dc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046dc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046dc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_BOOT_PATCH_7_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_BOOT_PATCH_7_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_BOOT_PATCH_7_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW7_MSB_BOOT_PATCH_7_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046e0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046e0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046e0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_LSB_BOOT_PATCH_8_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_LSB_BOOT_PATCH_8_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046e4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046e4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046e4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_BOOT_PATCH_8_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_BOOT_PATCH_8_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_BOOT_PATCH_8_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW8_MSB_BOOT_PATCH_8_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046e8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046e8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046e8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_LSB_BOOT_PATCH_9_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_LSB_BOOT_PATCH_9_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046ec) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046ec) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046ec) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_BOOT_PATCH_9_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_BOOT_PATCH_9_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_BOOT_PATCH_9_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW9_MSB_BOOT_PATCH_9_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046f0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046f0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046f0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_LSB_BOOT_PATCH_10_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_LSB_BOOT_PATCH_10_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046f4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046f4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046f4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_BOOT_PATCH_10_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_BOOT_PATCH_10_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_BOOT_PATCH_10_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW10_MSB_BOOT_PATCH_10_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046f8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046f8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046f8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_LSB_BOOT_PATCH_11_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_LSB_BOOT_PATCH_11_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000046fc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000046fc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000046fc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_BOOT_PATCH_11_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_BOOT_PATCH_11_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_BOOT_PATCH_11_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW11_MSB_BOOT_PATCH_11_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004700) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004700) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004700) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_LSB_BOOT_PATCH_12_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_LSB_BOOT_PATCH_12_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004704) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004704) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004704) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_BOOT_PATCH_12_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_BOOT_PATCH_12_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_BOOT_PATCH_12_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW12_MSB_BOOT_PATCH_12_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004708) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004708) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004708) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_LSB_BOOT_PATCH_13_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_LSB_BOOT_PATCH_13_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000470c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000470c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000470c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_BOOT_PATCH_13_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_BOOT_PATCH_13_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_BOOT_PATCH_13_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW13_MSB_BOOT_PATCH_13_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004710) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004710) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004710) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_LSB_BOOT_PATCH_14_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_LSB_BOOT_PATCH_14_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004714) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004714) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004714) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_BOOT_PATCH_14_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_BOOT_PATCH_14_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_BOOT_PATCH_14_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW14_MSB_BOOT_PATCH_14_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004718) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004718) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004718) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_LSB_BOOT_PATCH_15_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_LSB_BOOT_PATCH_15_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000471c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000471c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000471c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_BOOT_PATCH_15_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_BOOT_PATCH_15_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_BOOT_PATCH_15_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW15_MSB_BOOT_PATCH_15_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004720) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004720) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004720) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_LSB_BOOT_PATCH_16_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_LSB_BOOT_PATCH_16_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004724) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004724) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004724) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_BOOT_PATCH_16_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_BOOT_PATCH_16_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_BOOT_PATCH_16_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW16_MSB_BOOT_PATCH_16_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004728) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004728) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004728) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_LSB_BOOT_PATCH_17_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_LSB_BOOT_PATCH_17_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000472c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000472c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000472c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_BOOT_PATCH_17_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_BOOT_PATCH_17_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_BOOT_PATCH_17_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW17_MSB_BOOT_PATCH_17_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004730) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004730) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004730) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_LSB_BOOT_PATCH_18_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_LSB_BOOT_PATCH_18_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004734) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004734) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004734) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_BOOT_PATCH_18_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_BOOT_PATCH_18_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_BOOT_PATCH_18_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW18_MSB_BOOT_PATCH_18_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004738) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004738) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004738) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_LSB_BOOT_PATCH_19_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_LSB_BOOT_PATCH_19_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000473c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000473c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000473c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_BOOT_PATCH_19_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_BOOT_PATCH_19_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_BOOT_PATCH_19_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW19_MSB_BOOT_PATCH_19_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004740) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004740) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004740) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_LSB_BOOT_PATCH_20_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_LSB_BOOT_PATCH_20_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004744) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004744) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004744) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_BOOT_PATCH_20_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_BOOT_PATCH_20_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_BOOT_PATCH_20_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW20_MSB_BOOT_PATCH_20_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004748) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004748) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004748) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_LSB_BOOT_PATCH_21_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_LSB_BOOT_PATCH_21_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000474c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000474c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000474c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_BOOT_PATCH_21_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_BOOT_PATCH_21_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_BOOT_PATCH_21_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW21_MSB_BOOT_PATCH_21_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004750) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004750) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004750) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_LSB_BOOT_PATCH_22_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_LSB_BOOT_PATCH_22_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004754) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004754) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004754) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_BOOT_PATCH_22_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_BOOT_PATCH_22_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_BOOT_PATCH_22_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW22_MSB_BOOT_PATCH_22_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004758) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004758) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004758) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_LSB_BOOT_PATCH_23_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_LSB_BOOT_PATCH_23_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000475c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000475c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000475c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_BOOT_PATCH_23_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_BOOT_PATCH_23_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_BOOT_PATCH_23_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW23_MSB_BOOT_PATCH_23_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004760) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004760) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004760) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_LSB_BOOT_PATCH_24_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_LSB_BOOT_PATCH_24_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004764) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004764) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004764) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_BOOT_PATCH_24_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_BOOT_PATCH_24_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_BOOT_PATCH_24_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW24_MSB_BOOT_PATCH_24_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004768) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004768) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004768) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_LSB_BOOT_PATCH_25_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_LSB_BOOT_PATCH_25_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000476c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000476c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000476c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_BOOT_PATCH_25_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_BOOT_PATCH_25_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_BOOT_PATCH_25_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW25_MSB_BOOT_PATCH_25_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004770) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004770) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004770) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_LSB_BOOT_PATCH_26_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_LSB_BOOT_PATCH_26_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004774) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004774) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004774) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_BOOT_PATCH_26_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_BOOT_PATCH_26_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_BOOT_PATCH_26_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW26_MSB_BOOT_PATCH_26_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004778) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004778) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004778) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_LSB_BOOT_PATCH_27_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_LSB_BOOT_PATCH_27_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000477c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000477c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000477c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_BOOT_PATCH_27_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_BOOT_PATCH_27_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_BOOT_PATCH_27_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW27_MSB_BOOT_PATCH_27_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004780) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004780) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004780) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_LSB_BOOT_PATCH_28_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_LSB_BOOT_PATCH_28_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004784) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004784) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004784) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_BOOT_PATCH_28_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_BOOT_PATCH_28_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_BOOT_PATCH_28_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW28_MSB_BOOT_PATCH_28_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004788) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004788) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004788) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_LSB_BOOT_PATCH_29_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_LSB_BOOT_PATCH_29_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000478c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000478c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000478c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_BOOT_PATCH_29_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_BOOT_PATCH_29_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_BOOT_PATCH_29_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW29_MSB_BOOT_PATCH_29_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004790) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004790) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004790) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_LSB_BOOT_PATCH_30_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_LSB_BOOT_PATCH_30_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004794) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004794) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004794) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_BOOT_PATCH_30_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_BOOT_PATCH_30_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_BOOT_PATCH_30_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW30_MSB_BOOT_PATCH_30_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004798) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004798) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004798) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_LSB_BOOT_PATCH_31_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_LSB_BOOT_PATCH_31_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000479c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000479c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000479c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_BOOT_PATCH_31_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_BOOT_PATCH_31_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_BOOT_PATCH_31_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW31_MSB_BOOT_PATCH_31_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047a0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047a0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047a0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_LSB_BOOT_PATCH_32_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_LSB_BOOT_PATCH_32_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047a4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047a4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047a4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_BOOT_PATCH_32_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_BOOT_PATCH_32_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_BOOT_PATCH_32_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW32_MSB_BOOT_PATCH_32_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047a8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047a8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047a8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_LSB_BOOT_PATCH_33_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_LSB_BOOT_PATCH_33_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047ac) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047ac) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047ac) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_BOOT_PATCH_33_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_BOOT_PATCH_33_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_BOOT_PATCH_33_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW33_MSB_BOOT_PATCH_33_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047b0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047b0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047b0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_LSB_BOOT_PATCH_34_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_LSB_BOOT_PATCH_34_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047b4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047b4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047b4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_BOOT_PATCH_34_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_BOOT_PATCH_34_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_BOOT_PATCH_34_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW34_MSB_BOOT_PATCH_34_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047b8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047b8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047b8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_LSB_BOOT_PATCH_35_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_LSB_BOOT_PATCH_35_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047bc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047bc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047bc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_BOOT_PATCH_35_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_BOOT_PATCH_35_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_BOOT_PATCH_35_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW35_MSB_BOOT_PATCH_35_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047c0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047c0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047c0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_LSB_BOOT_PATCH_36_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_LSB_BOOT_PATCH_36_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047c4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047c4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047c4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_BOOT_PATCH_36_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_BOOT_PATCH_36_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_BOOT_PATCH_36_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW36_MSB_BOOT_PATCH_36_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047c8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047c8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047c8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_LSB_BOOT_PATCH_37_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_LSB_BOOT_PATCH_37_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047cc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047cc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047cc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_BOOT_PATCH_37_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_BOOT_PATCH_37_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_BOOT_PATCH_37_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW37_MSB_BOOT_PATCH_37_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047d0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047d0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047d0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_LSB_BOOT_PATCH_38_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_LSB_BOOT_PATCH_38_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047d4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047d4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047d4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_BOOT_PATCH_38_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_BOOT_PATCH_38_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_BOOT_PATCH_38_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW38_MSB_BOOT_PATCH_38_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047d8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047d8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047d8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_LSB_BOOT_PATCH_39_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_LSB_BOOT_PATCH_39_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047dc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047dc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047dc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_BOOT_PATCH_39_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_BOOT_PATCH_39_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_BOOT_PATCH_39_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW39_MSB_BOOT_PATCH_39_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047e0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047e0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047e0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_LSB_BOOT_PATCH_40_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_LSB_BOOT_PATCH_40_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047e4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047e4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047e4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_BOOT_PATCH_40_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_BOOT_PATCH_40_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_BOOT_PATCH_40_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW40_MSB_BOOT_PATCH_40_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047e8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047e8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047e8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_LSB_BOOT_PATCH_41_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_LSB_BOOT_PATCH_41_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047ec) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047ec) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047ec) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_BOOT_PATCH_41_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_BOOT_PATCH_41_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_BOOT_PATCH_41_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW41_MSB_BOOT_PATCH_41_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047f0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047f0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047f0) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_LSB_BOOT_PATCH_42_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_LSB_BOOT_PATCH_42_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047f4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047f4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047f4) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_BOOT_PATCH_42_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_BOOT_PATCH_42_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_BOOT_PATCH_42_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW42_MSB_BOOT_PATCH_42_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047f8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047f8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047f8) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_LSB_BOOT_PATCH_43_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_LSB_BOOT_PATCH_43_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000047fc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000047fc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000047fc) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_BOOT_PATCH_43_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_BOOT_PATCH_43_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_BOOT_PATCH_43_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW43_MSB_BOOT_PATCH_43_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004800) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004800) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004800) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_LSB_BOOT_PATCH_44_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_LSB_BOOT_PATCH_44_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004804) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004804) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004804) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_BOOT_PATCH_44_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_BOOT_PATCH_44_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_BOOT_PATCH_44_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW44_MSB_BOOT_PATCH_44_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004808) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004808) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004808) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_LSB_BOOT_PATCH_45_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_LSB_BOOT_PATCH_45_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000480c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000480c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000480c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_BOOT_PATCH_45_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_BOOT_PATCH_45_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_BOOT_PATCH_45_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW45_MSB_BOOT_PATCH_45_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004810) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004810) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004810) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_LSB_BOOT_PATCH_46_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_LSB_BOOT_PATCH_46_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004814) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004814) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004814) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_BOOT_PATCH_46_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_BOOT_PATCH_46_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_BOOT_PATCH_46_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW46_MSB_BOOT_PATCH_46_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004818) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004818) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004818) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_LSB_BOOT_PATCH_47_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_LSB_BOOT_PATCH_47_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000481c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000481c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000481c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_BOOT_PATCH_47_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_BOOT_PATCH_47_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_BOOT_PATCH_47_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW47_MSB_BOOT_PATCH_47_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004820) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004820) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004820) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_LSB_BOOT_PATCH_48_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_LSB_BOOT_PATCH_48_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004824) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004824) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004824) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_BOOT_PATCH_48_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_BOOT_PATCH_48_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_BOOT_PATCH_48_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW48_MSB_BOOT_PATCH_48_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004828) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004828) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004828) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_LSB_BOOT_PATCH_49_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_LSB_BOOT_PATCH_49_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000482c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000482c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000482c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_BOOT_PATCH_49_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_BOOT_PATCH_49_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_BOOT_PATCH_49_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW49_MSB_BOOT_PATCH_49_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004830) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004830) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004830) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_LSB_BOOT_PATCH_50_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_LSB_BOOT_PATCH_50_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004834) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004834) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004834) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_BOOT_PATCH_50_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_BOOT_PATCH_50_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_BOOT_PATCH_50_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW50_MSB_BOOT_PATCH_50_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004838) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004838) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004838) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_LSB_BOOT_PATCH_51_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_LSB_BOOT_PATCH_51_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000483c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000483c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000483c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_BOOT_PATCH_51_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_BOOT_PATCH_51_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_BOOT_PATCH_51_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW51_MSB_BOOT_PATCH_51_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004840) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004840) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004840) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_LSB_BOOT_PATCH_52_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_LSB_BOOT_PATCH_52_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004844) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004844) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004844) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_BOOT_PATCH_52_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_BOOT_PATCH_52_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_BOOT_PATCH_52_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW52_MSB_BOOT_PATCH_52_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004848) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004848) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004848) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_LSB_BOOT_PATCH_53_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_LSB_BOOT_PATCH_53_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000484c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000484c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000484c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_BOOT_PATCH_53_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_BOOT_PATCH_53_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_BOOT_PATCH_53_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW53_MSB_BOOT_PATCH_53_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004850) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004850) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004850) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_LSB_BOOT_PATCH_54_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_LSB_BOOT_PATCH_54_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004854) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004854) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004854) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_BOOT_PATCH_54_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_BOOT_PATCH_54_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_BOOT_PATCH_54_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW54_MSB_BOOT_PATCH_54_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004858) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004858) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004858) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_LSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_LSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_LSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_LSB_BOOT_PATCH_55_DATA_BMSK 0xffffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_LSB_BOOT_PATCH_55_DATA_SHFT 0x0 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000485c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000485c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000485c) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_IN \ in_dword(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_ADDR) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_ADDR, m) #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_RSVD0_BMSK 0xfe0000 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_RSVD0_SHFT 0x11 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_BOOT_PATCH_55_ADDR_BMSK 0x1fffe #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_BOOT_PATCH_55_ADDR_SHFT 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_BOOT_PATCH_55_ENABLE_BMSK 0x1 #define HWIO_QFPROM_CORR_BOOT_ROM_PATCH_ROW55_MSB_BOOT_PATCH_55_ENABLE_SHFT 0x0 #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004860) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004860) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004860) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_IMAGE_ENCRYPTION_KEY_1_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_LSB_IMAGE_ENCRYPTION_KEY_1_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004864) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004864) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004864) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_IMAGE_ENCRYPTION_KEY_1_55_32_BMSK 0xffffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW0_MSB_IMAGE_ENCRYPTION_KEY_1_55_32_SHFT 0x0 #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004868) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004868) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004868) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_IMAGE_ENCRYPTION_KEY_1_87_56_BMSK 0xffffffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_LSB_IMAGE_ENCRYPTION_KEY_1_87_56_SHFT 0x0 #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000486c) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000486c) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000486c) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_IMAGE_ENCRYPTION_KEY_1_111_88_BMSK 0xffffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW1_MSB_IMAGE_ENCRYPTION_KEY_1_111_88_SHFT 0x0 #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004870) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004870) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004870) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_UNUSED_254_15_0_BMSK 0xffff0000 #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_UNUSED_254_15_0_SHFT 0x10 #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_IMAGE_ENCRYPTION_KEY_1_127_112_BMSK 0xffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_LSB_IMAGE_ENCRYPTION_KEY_1_127_112_SHFT 0x0 #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004874) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004874) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004874) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_UNUSED_254_39_16_BMSK 0xffffff #define HWIO_QFPROM_CORR_IMAGE_ENCRYPTION_KEY_1_ROW2_MSB_UNUSED_254_39_16_SHFT 0x0 #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004878) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004878) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004878) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_LSB_USER_KEY_DERIVATION_KEY_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_LSB_USER_KEY_DERIVATION_KEY_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000487c) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000487c) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000487c) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_MSB_USER_KEY_DERIVATION_KEY_55_32_BMSK 0xffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW0_MSB_USER_KEY_DERIVATION_KEY_55_32_SHFT 0x0 #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004880) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004880) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004880) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_LSB_USER_KEY_DERIVATION_KEY_87_56_BMSK 0xffffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_LSB_USER_KEY_DERIVATION_KEY_87_56_SHFT 0x0 #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004884) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004884) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004884) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_MSB_USER_KEY_DERIVATION_KEY_111_88_BMSK 0xffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW1_MSB_USER_KEY_DERIVATION_KEY_111_88_SHFT 0x0 #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004888) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004888) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004888) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_LSB_IN \ in_dword(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_LSB_ADDR) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_LSB_ADDR, m) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_LSB_USER_KEY_DERIVATION_KEY_143_112_BMSK 0xffffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_LSB_USER_KEY_DERIVATION_KEY_143_112_SHFT 0x0 #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000488c) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000488c) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000488c) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_MSB_IN \ in_dword(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_MSB_ADDR) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_MSB_ADDR, m) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_MSB_USER_KEY_DERIVATION_KEY_167_144_BMSK 0xffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW2_MSB_USER_KEY_DERIVATION_KEY_167_144_SHFT 0x0 #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004890) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004890) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004890) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_LSB_IN \ in_dword(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_LSB_ADDR) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_LSB_ADDR, m) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_LSB_USER_KEY_DERIVATION_KEY_199_168_BMSK 0xffffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_LSB_USER_KEY_DERIVATION_KEY_199_168_SHFT 0x0 #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004894) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004894) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004894) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_MSB_IN \ in_dword(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_MSB_ADDR) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_MSB_ADDR, m) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_MSB_USER_KEY_DERIVATION_KEY_223_200_BMSK 0xffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW3_MSB_USER_KEY_DERIVATION_KEY_223_200_SHFT 0x0 #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00004898) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00004898) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00004898) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_LSB_IN \ in_dword(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_LSB_ADDR) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_LSB_ADDR, m) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_LSB_USER_KEY_DERIVATION_KEY_255_224_BMSK 0xffffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_LSB_USER_KEY_DERIVATION_KEY_255_224_SHFT 0x0 #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000489c) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000489c) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000489c) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_MSB_RMSK 0xffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_MSB_IN \ in_dword(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_MSB_ADDR) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_MSB_ADDR, m) #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_MSB_UNUSED_259_BMSK 0xffffff #define HWIO_QFPROM_CORR_USER_KEY_DERIVATION_KEY_ROW4_MSB_UNUSED_259_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048a0) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048a0) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048a0) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_LSB_OEM_SPARE_28_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_LSB_OEM_SPARE_28_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048a4) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048a4) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048a4) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_MSB_OEM_SPARE_28_63_32_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW0_MSB_OEM_SPARE_28_63_32_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048a8) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048a8) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048a8) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_LSB_OEM_SPARE_28_95_64_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_LSB_OEM_SPARE_28_95_64_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048ac) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048ac) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048ac) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_MSB_OEM_SPARE_28_127_96_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_28_ROW1_MSB_OEM_SPARE_28_127_96_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048b0) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048b0) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048b0) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_LSB_OEM_SPARE_29_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_LSB_OEM_SPARE_29_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048b4) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048b4) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048b4) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_MSB_OEM_SPARE_29_63_32_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW0_MSB_OEM_SPARE_29_63_32_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048b8) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048b8) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048b8) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_LSB_OEM_SPARE_29_95_64_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_LSB_OEM_SPARE_29_95_64_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048bc) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048bc) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048bc) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_MSB_OEM_SPARE_29_127_96_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_29_ROW1_MSB_OEM_SPARE_29_127_96_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048c0) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048c0) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048c0) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_LSB_OEM_SPARE_30_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_LSB_OEM_SPARE_30_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048c4) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048c4) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048c4) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_MSB_OEM_SPARE_30_63_32_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW0_MSB_OEM_SPARE_30_63_32_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048c8) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048c8) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048c8) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_LSB_OEM_SPARE_30_95_64_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_LSB_OEM_SPARE_30_95_64_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048cc) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048cc) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048cc) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_MSB_OEM_SPARE_30_127_96_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_30_ROW1_MSB_OEM_SPARE_30_127_96_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048d0) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048d0) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048d0) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_LSB_OEM_SPARE_31_31_0_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_LSB_OEM_SPARE_31_31_0_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048d4) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048d4) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048d4) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_MSB_OEM_SPARE_31_63_32_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW0_MSB_OEM_SPARE_31_63_32_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048d8) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_LSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048d8) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_LSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048d8) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_LSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_LSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_LSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_LSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_LSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_LSB_OEM_SPARE_31_95_64_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_LSB_OEM_SPARE_31_95_64_SHFT 0x0 #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_MSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000048dc) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_MSB_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000048dc) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_MSB_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000048dc) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_MSB_RMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_MSB_IN \ in_dword(HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_MSB_ADDR) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_MSB_INM(m) \ in_dword_masked(HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_MSB_ADDR, m) #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_MSB_OEM_SPARE_31_127_96_BMSK 0xffffffff #define HWIO_QFPROM_CORR_OEM_SPARE_31_ROW1_MSB_OEM_SPARE_31_127_96_SHFT 0x0 #define HWIO_SEC_CTRL_HW_VERSION_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006000) #define HWIO_SEC_CTRL_HW_VERSION_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006000) #define HWIO_SEC_CTRL_HW_VERSION_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006000) #define HWIO_SEC_CTRL_HW_VERSION_RMSK 0xffffffff #define HWIO_SEC_CTRL_HW_VERSION_IN \ in_dword(HWIO_SEC_CTRL_HW_VERSION_ADDR) #define HWIO_SEC_CTRL_HW_VERSION_INM(m) \ in_dword_masked(HWIO_SEC_CTRL_HW_VERSION_ADDR, m) #define HWIO_SEC_CTRL_HW_VERSION_MAJOR_BMSK 0xf0000000 #define HWIO_SEC_CTRL_HW_VERSION_MAJOR_SHFT 0x1c #define HWIO_SEC_CTRL_HW_VERSION_MINOR_BMSK 0xfff0000 #define HWIO_SEC_CTRL_HW_VERSION_MINOR_SHFT 0x10 #define HWIO_SEC_CTRL_HW_VERSION_STEP_BMSK 0xffff #define HWIO_SEC_CTRL_HW_VERSION_STEP_SHFT 0x0 #define HWIO_FEATURE_CONFIG_M0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006004) #define HWIO_FEATURE_CONFIG_M0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006004) #define HWIO_FEATURE_CONFIG_M0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006004) #define HWIO_FEATURE_CONFIG_M0_RMSK 0xffffffff #define HWIO_FEATURE_CONFIG_M0_IN \ in_dword(HWIO_FEATURE_CONFIG_M0_ADDR) #define HWIO_FEATURE_CONFIG_M0_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_M0_ADDR, m) #define HWIO_FEATURE_CONFIG_M0_MODEM_FEATURE_DISABLE_HARD_16_0_BMSK 0xffff8000 #define HWIO_FEATURE_CONFIG_M0_MODEM_FEATURE_DISABLE_HARD_16_0_SHFT 0xf #define HWIO_FEATURE_CONFIG_M0_MODEM_FEATURE_DISABLE_HARD_16_0_DISABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M0_MODEM_FEATURE_DISABLE_HARD_16_0_ENABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M0_MODEM_FEATURE_DISABLE_SPARE_BMSK 0x7fff #define HWIO_FEATURE_CONFIG_M0_MODEM_FEATURE_DISABLE_SPARE_SHFT 0x0 #define HWIO_FEATURE_CONFIG_M0_MODEM_FEATURE_DISABLE_SPARE_DISABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M0_MODEM_FEATURE_DISABLE_SPARE_ENABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006008) #define HWIO_FEATURE_CONFIG_M1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006008) #define HWIO_FEATURE_CONFIG_M1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006008) #define HWIO_FEATURE_CONFIG_M1_RMSK 0xffffffff #define HWIO_FEATURE_CONFIG_M1_IN \ in_dword(HWIO_FEATURE_CONFIG_M1_ADDR) #define HWIO_FEATURE_CONFIG_M1_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_M1_ADDR, m) #define HWIO_FEATURE_CONFIG_M1_MODEM_FEATURE_DISABLE_SOFT_1_23_0_BMSK 0xffffff00 #define HWIO_FEATURE_CONFIG_M1_MODEM_FEATURE_DISABLE_SOFT_1_23_0_SHFT 0x8 #define HWIO_FEATURE_CONFIG_M1_MODEM_FEATURE_DISABLE_SOFT_1_23_0_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M1_MODEM_FEATURE_DISABLE_SOFT_1_23_0_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M1_MODEM_FEATURE_DISABLE_HARD_24_17_BMSK 0xff #define HWIO_FEATURE_CONFIG_M1_MODEM_FEATURE_DISABLE_HARD_24_17_SHFT 0x0 #define HWIO_FEATURE_CONFIG_M1_MODEM_FEATURE_DISABLE_HARD_24_17_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M1_MODEM_FEATURE_DISABLE_HARD_24_17_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M2_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000600c) #define HWIO_FEATURE_CONFIG_M2_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000600c) #define HWIO_FEATURE_CONFIG_M2_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000600c) #define HWIO_FEATURE_CONFIG_M2_RMSK 0xffffffff #define HWIO_FEATURE_CONFIG_M2_IN \ in_dword(HWIO_FEATURE_CONFIG_M2_ADDR) #define HWIO_FEATURE_CONFIG_M2_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_M2_ADDR, m) #define HWIO_FEATURE_CONFIG_M2_MODEM_FEATURE_DISABLE_SOFT_2_BMSK 0xffffff00 #define HWIO_FEATURE_CONFIG_M2_MODEM_FEATURE_DISABLE_SOFT_2_SHFT 0x8 #define HWIO_FEATURE_CONFIG_M2_MODEM_FEATURE_DISABLE_SOFT_2_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M2_MODEM_FEATURE_DISABLE_SOFT_2_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M2_MODEM_FEATURE_DISABLE_SOFT_1_31_24_BMSK 0xff #define HWIO_FEATURE_CONFIG_M2_MODEM_FEATURE_DISABLE_SOFT_1_31_24_SHFT 0x0 #define HWIO_FEATURE_CONFIG_M2_MODEM_FEATURE_DISABLE_SOFT_1_31_24_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M2_MODEM_FEATURE_DISABLE_SOFT_1_31_24_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M3_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006010) #define HWIO_FEATURE_CONFIG_M3_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006010) #define HWIO_FEATURE_CONFIG_M3_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006010) #define HWIO_FEATURE_CONFIG_M3_RMSK 0xffffffff #define HWIO_FEATURE_CONFIG_M3_IN \ in_dword(HWIO_FEATURE_CONFIG_M3_ADDR) #define HWIO_FEATURE_CONFIG_M3_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_M3_ADDR, m) #define HWIO_FEATURE_CONFIG_M3_MDSS_RESOLUTION_LIMIT_BMSK 0xc0000000 #define HWIO_FEATURE_CONFIG_M3_MDSS_RESOLUTION_LIMIT_SHFT 0x1e #define HWIO_FEATURE_CONFIG_M3_DP_DISABLE_BMSK 0x20000000 #define HWIO_FEATURE_CONFIG_M3_DP_DISABLE_SHFT 0x1d #define HWIO_FEATURE_CONFIG_M3_DP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M3_DP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M3_HDCP_DISABLE_BMSK 0x10000000 #define HWIO_FEATURE_CONFIG_M3_HDCP_DISABLE_SHFT 0x1c #define HWIO_FEATURE_CONFIG_M3_HDCP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M3_HDCP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M3_MDP_APICAL_LTC_DISABLE_BMSK 0x8000000 #define HWIO_FEATURE_CONFIG_M3_MDP_APICAL_LTC_DISABLE_SHFT 0x1b #define HWIO_FEATURE_CONFIG_M3_MDP_APICAL_LTC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M3_MDP_APICAL_LTC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M3_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_BMSK 0x4000000 #define HWIO_FEATURE_CONFIG_M3_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_SHFT 0x1a #define HWIO_FEATURE_CONFIG_M3_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M3_HDCP_GLOBAL_KEY_SPLIT2_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M3_DSI_1_DISABLE_BMSK 0x2000000 #define HWIO_FEATURE_CONFIG_M3_DSI_1_DISABLE_SHFT 0x19 #define HWIO_FEATURE_CONFIG_M3_DSI_1_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M3_DSI_1_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M3_DSI_0_DISABLE_BMSK 0x1000000 #define HWIO_FEATURE_CONFIG_M3_DSI_0_DISABLE_SHFT 0x18 #define HWIO_FEATURE_CONFIG_M3_DSI_0_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M3_DSI_0_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M3_MODEM_FEATURE_DISABLE_SOFT_3_BMSK 0xffffff #define HWIO_FEATURE_CONFIG_M3_MODEM_FEATURE_DISABLE_SOFT_3_SHFT 0x0 #define HWIO_FEATURE_CONFIG_M3_MODEM_FEATURE_DISABLE_SOFT_3_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M3_MODEM_FEATURE_DISABLE_SOFT_3_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006014) #define HWIO_FEATURE_CONFIG_M4_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006014) #define HWIO_FEATURE_CONFIG_M4_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006014) #define HWIO_FEATURE_CONFIG_M4_RMSK 0xffffffff #define HWIO_FEATURE_CONFIG_M4_IN \ in_dword(HWIO_FEATURE_CONFIG_M4_ADDR) #define HWIO_FEATURE_CONFIG_M4_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_M4_ADDR, m) #define HWIO_FEATURE_CONFIG_M4_MOCHA_PART_BMSK 0x80000000 #define HWIO_FEATURE_CONFIG_M4_MOCHA_PART_SHFT 0x1f #define HWIO_FEATURE_CONFIG_M4_QC_SP_DISABLE_BMSK 0x40000000 #define HWIO_FEATURE_CONFIG_M4_QC_SP_DISABLE_SHFT 0x1e #define HWIO_FEATURE_CONFIG_M4_QC_SP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_QC_SP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_SMMU_DISABLE_BMSK 0x20000000 #define HWIO_FEATURE_CONFIG_M4_SMMU_DISABLE_SHFT 0x1d #define HWIO_FEATURE_CONFIG_M4_SMMU_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_SMMU_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_DISABLE_SEC_BOOT_GPIO_BMSK 0x10000000 #define HWIO_FEATURE_CONFIG_M4_DISABLE_SEC_BOOT_GPIO_SHFT 0x1c #define HWIO_FEATURE_CONFIG_M4_QC_UDK_DISABLE_BMSK 0x8000000 #define HWIO_FEATURE_CONFIG_M4_QC_UDK_DISABLE_SHFT 0x1b #define HWIO_FEATURE_CONFIG_M4_QC_UDK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_QC_UDK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_CM_FEAT_CONFIG_DISABLE_BMSK 0x4000000 #define HWIO_FEATURE_CONFIG_M4_CM_FEAT_CONFIG_DISABLE_SHFT 0x1a #define HWIO_FEATURE_CONFIG_M4_CM_FEAT_CONFIG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_CM_FEAT_CONFIG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_PCIE_1_DISABLE_BMSK 0x2000000 #define HWIO_FEATURE_CONFIG_M4_PCIE_1_DISABLE_SHFT 0x19 #define HWIO_FEATURE_CONFIG_M4_PCIE_1_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_PCIE_1_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_PCIE_0_DISABLE_BMSK 0x1000000 #define HWIO_FEATURE_CONFIG_M4_PCIE_0_DISABLE_SHFT 0x18 #define HWIO_FEATURE_CONFIG_M4_PCIE_0_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_PCIE_0_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_SSC_DISABLE_BMSK 0x800000 #define HWIO_FEATURE_CONFIG_M4_SSC_DISABLE_SHFT 0x17 #define HWIO_FEATURE_CONFIG_M4_SSC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_SSC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_SSC_ISLAND_MODE_Q6_CLK_DISABLE_BMSK 0x400000 #define HWIO_FEATURE_CONFIG_M4_SSC_ISLAND_MODE_Q6_CLK_DISABLE_SHFT 0x16 #define HWIO_FEATURE_CONFIG_M4_SSC_ISLAND_MODE_Q6_CLK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_SSC_ISLAND_MODE_Q6_CLK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_SSC_SW_ISLAND_MODE_DISABLE_BMSK 0x200000 #define HWIO_FEATURE_CONFIG_M4_SSC_SW_ISLAND_MODE_DISABLE_SHFT 0x15 #define HWIO_FEATURE_CONFIG_M4_SSC_SW_ISLAND_MODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_SSC_SW_ISLAND_MODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_GFX3D_FREQ_LIMIT_VAL_BMSK 0x1fe000 #define HWIO_FEATURE_CONFIG_M4_GFX3D_FREQ_LIMIT_VAL_SHFT 0xd #define HWIO_FEATURE_CONFIG_M4_IRIS_MULTIPIPE_DISABLE_BMSK 0x1000 #define HWIO_FEATURE_CONFIG_M4_IRIS_MULTIPIPE_DISABLE_SHFT 0xc #define HWIO_FEATURE_CONFIG_M4_IRIS_MULTIPIPE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_IRIS_MULTIPIPE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_IRIS_HEVC_ENCODE_DISABLE_BMSK 0x800 #define HWIO_FEATURE_CONFIG_M4_IRIS_HEVC_ENCODE_DISABLE_SHFT 0xb #define HWIO_FEATURE_CONFIG_M4_IRIS_HEVC_ENCODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_IRIS_HEVC_ENCODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_IRIS_HEVC_DECODE_DISABLE_BMSK 0x400 #define HWIO_FEATURE_CONFIG_M4_IRIS_HEVC_DECODE_DISABLE_SHFT 0xa #define HWIO_FEATURE_CONFIG_M4_IRIS_HEVC_DECODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_IRIS_HEVC_DECODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_IRIS_4K_DISABLE_BMSK 0x200 #define HWIO_FEATURE_CONFIG_M4_IRIS_4K_DISABLE_SHFT 0x9 #define HWIO_FEATURE_CONFIG_M4_IRIS_4K_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_IRIS_4K_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_IRIS_CVP_DISABLE_BMSK 0x100 #define HWIO_FEATURE_CONFIG_M4_IRIS_CVP_DISABLE_SHFT 0x8 #define HWIO_FEATURE_CONFIG_M4_IRIS_CVP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_IRIS_CVP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_IRIS_DISABLE_VPX_BMSK 0x80 #define HWIO_FEATURE_CONFIG_M4_IRIS_DISABLE_VPX_SHFT 0x7 #define HWIO_FEATURE_CONFIG_M4_IRIS_DISABLE_VPX_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_IRIS_DISABLE_VPX_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_EFUSE_CAM_SBI_DISABLE_IF_BMSK 0x40 #define HWIO_FEATURE_CONFIG_M4_EFUSE_CAM_SBI_DISABLE_IF_SHFT 0x6 #define HWIO_FEATURE_CONFIG_M4_EFUSE_CAM_SBI_DISABLE_IF_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_EFUSE_CAM_SBI_DISABLE_IF_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_EUD_PORT1_SEL_BMSK 0x20 #define HWIO_FEATURE_CONFIG_M4_EUD_PORT1_SEL_SHFT 0x5 #define HWIO_FEATURE_CONFIG_M4_EUD_PORT1_SEL_USB_PORT0_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_EUD_PORT1_SEL_USB_PORT1_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_EUD_IGNR_CSR_BMSK 0x10 #define HWIO_FEATURE_CONFIG_M4_EUD_IGNR_CSR_SHFT 0x4 #define HWIO_FEATURE_CONFIG_M4_MDSS_Q_CONFIG_FUSE_BMSK 0x8 #define HWIO_FEATURE_CONFIG_M4_MDSS_Q_CONFIG_FUSE_SHFT 0x3 #define HWIO_FEATURE_CONFIG_M4_MDSS_Q_CONFIG_FUSE_HANA_FEAT_SET_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M4_MDSS_Q_CONFIG_FUSE_HANAQ_FEAT_SET_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M4_SPR_DISABLE_BMSK 0x4 #define HWIO_FEATURE_CONFIG_M4_SPR_DISABLE_SHFT 0x2 #define HWIO_FEATURE_CONFIG_M4_DEMURA_DISABLE_BMSK 0x2 #define HWIO_FEATURE_CONFIG_M4_DEMURA_DISABLE_SHFT 0x1 #define HWIO_FEATURE_CONFIG_M4_MST_DISABLE_BMSK 0x1 #define HWIO_FEATURE_CONFIG_M4_MST_DISABLE_SHFT 0x0 #define HWIO_FEATURE_CONFIG_M5_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006018) #define HWIO_FEATURE_CONFIG_M5_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006018) #define HWIO_FEATURE_CONFIG_M5_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006018) #define HWIO_FEATURE_CONFIG_M5_RMSK 0xffffffff #define HWIO_FEATURE_CONFIG_M5_IN \ in_dword(HWIO_FEATURE_CONFIG_M5_ADDR) #define HWIO_FEATURE_CONFIG_M5_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_M5_ADDR, m) #define HWIO_FEATURE_CONFIG_M5_APPS_BOOT_FSM_FUSE_BMSK 0xfc000000 #define HWIO_FEATURE_CONFIG_M5_APPS_BOOT_FSM_FUSE_SHFT 0x1a #define HWIO_FEATURE_CONFIG_M5_SYS_APCSCFGAPMBOOTONMX_BMSK 0x2000000 #define HWIO_FEATURE_CONFIG_M5_SYS_APCSCFGAPMBOOTONMX_SHFT 0x19 #define HWIO_FEATURE_CONFIG_M5_SYS_APCCCFGCPUPRESENT_N_BMSK 0x1fe0000 #define HWIO_FEATURE_CONFIG_M5_SYS_APCCCFGCPUPRESENT_N_SHFT 0x11 #define HWIO_FEATURE_CONFIG_M5_APSS_PDXWRPNTRDELAY_BMSK 0x18000 #define HWIO_FEATURE_CONFIG_M5_APSS_PDXWRPNTRDELAY_SHFT 0xf #define HWIO_FEATURE_CONFIG_M5_GATE_SRST_FUSE_BMSK 0x4000 #define HWIO_FEATURE_CONFIG_M5_GATE_SRST_FUSE_SHFT 0xe #define HWIO_FEATURE_CONFIG_M5_GATE_SRST_FUSE_UNGATED_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_GATE_SRST_FUSE_GATED_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M5_AUTOMOTIVE_BIT_FUNCTIONAL_BMSK 0x2000 #define HWIO_FEATURE_CONFIG_M5_AUTOMOTIVE_BIT_FUNCTIONAL_SHFT 0xd #define HWIO_FEATURE_CONFIG_M5_AUTOMOTIVE_BIT_FUNCTIONAL_MOBILE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_AUTOMOTIVE_BIT_FUNCTIONAL_AUTOMOTIVE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M5_AUTOMOTIVE_BIT_POWER_BMSK 0x1000 #define HWIO_FEATURE_CONFIG_M5_AUTOMOTIVE_BIT_POWER_SHFT 0xc #define HWIO_FEATURE_CONFIG_M5_AUTOMOTIVE_BIT_POWER_MOBILE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_AUTOMOTIVE_BIT_POWER_AUTOMOTIVE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M5_EMAC_DISABLE_BMSK 0x800 #define HWIO_FEATURE_CONFIG_M5_EMAC_DISABLE_SHFT 0xb #define HWIO_FEATURE_CONFIG_M5_EMAC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_EMAC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M5_MODEM_TCM_BOOT_DISABLE_BMSK 0x400 #define HWIO_FEATURE_CONFIG_M5_MODEM_TCM_BOOT_DISABLE_SHFT 0xa #define HWIO_FEATURE_CONFIG_M5_MODEM_TCM_BOOT_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_MODEM_TCM_BOOT_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M5_NAV_EFUSE_DISABLE_BMSK 0x200 #define HWIO_FEATURE_CONFIG_M5_NAV_EFUSE_DISABLE_SHFT 0x9 #define HWIO_FEATURE_CONFIG_M5_NAV_EFUSE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_NAV_EFUSE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M5_FUSE_CORTEX_M3_DISABLE_BMSK 0x100 #define HWIO_FEATURE_CONFIG_M5_FUSE_CORTEX_M3_DISABLE_SHFT 0x8 #define HWIO_FEATURE_CONFIG_M5_APS_RESET_DISABLE_BMSK 0x80 #define HWIO_FEATURE_CONFIG_M5_APS_RESET_DISABLE_SHFT 0x7 #define HWIO_FEATURE_CONFIG_M5_DOLBY_BIT_BMSK 0x40 #define HWIO_FEATURE_CONFIG_M5_DOLBY_BIT_SHFT 0x6 #define HWIO_FEATURE_CONFIG_M5_I_MC5_FUSE_BMSK 0x20 #define HWIO_FEATURE_CONFIG_M5_I_MC5_FUSE_SHFT 0x5 #define HWIO_FEATURE_CONFIG_M5_I_MC5_FUSE_MC4_MODE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_I_MC5_FUSE_MC5_MODE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M5_I_MC4_FUSE_BMSK 0x10 #define HWIO_FEATURE_CONFIG_M5_I_MC4_FUSE_SHFT 0x4 #define HWIO_FEATURE_CONFIG_M5_I_MC4_FUSE_MC4_MODE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_I_MC4_FUSE_MC5_MODE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M5_PKA_3PIP_DISABLE_BMSK 0x8 #define HWIO_FEATURE_CONFIG_M5_PKA_3PIP_DISABLE_SHFT 0x3 #define HWIO_FEATURE_CONFIG_M5_PKA_3PIP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_PKA_3PIP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M5_FUSE_UFS_SINGLE_LANE_BMSK 0x4 #define HWIO_FEATURE_CONFIG_M5_FUSE_UFS_SINGLE_LANE_SHFT 0x2 #define HWIO_FEATURE_CONFIG_M5_FUSE_UFS_SINGLE_LANE_ICE_ENGINE_USES_SW_KEY_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_FUSE_UFS_SINGLE_LANE_ICE_ENGINE_USES_HW_KEY_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M5_UFS_FUSE_ICE_DISABLE_BMSK 0x2 #define HWIO_FEATURE_CONFIG_M5_UFS_FUSE_ICE_DISABLE_SHFT 0x1 #define HWIO_FEATURE_CONFIG_M5_UFS_FUSE_ICE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_UFS_FUSE_ICE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M5_MSMC_NAV_EN_BMSK 0x1 #define HWIO_FEATURE_CONFIG_M5_MSMC_NAV_EN_SHFT 0x0 #define HWIO_FEATURE_CONFIG_M5_MSMC_NAV_EN_DISABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M5_MSMC_NAV_EN_ENABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M6_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000601c) #define HWIO_FEATURE_CONFIG_M6_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000601c) #define HWIO_FEATURE_CONFIG_M6_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000601c) #define HWIO_FEATURE_CONFIG_M6_RMSK 0xffffffff #define HWIO_FEATURE_CONFIG_M6_IN \ in_dword(HWIO_FEATURE_CONFIG_M6_ADDR) #define HWIO_FEATURE_CONFIG_M6_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_M6_ADDR, m) #define HWIO_FEATURE_CONFIG_M6_TURING_Q6SS_PLL_L_MAX_7_0_BMSK 0xff000000 #define HWIO_FEATURE_CONFIG_M6_TURING_Q6SS_PLL_L_MAX_7_0_SHFT 0x18 #define HWIO_FEATURE_CONFIG_M6_TURING_Q6SS_L2TCM_EN_BMSK 0xf00000 #define HWIO_FEATURE_CONFIG_M6_TURING_Q6SS_L2TCM_EN_SHFT 0x14 #define HWIO_FEATURE_CONFIG_M6_LEGACY_MBNV6_OVERRIDE_BMSK 0x80000 #define HWIO_FEATURE_CONFIG_M6_LEGACY_MBNV6_OVERRIDE_SHFT 0x13 #define HWIO_FEATURE_CONFIG_M6_SYS_CFG_GOLDPLUS_PLL_LVAL_BMSK 0x7f800 #define HWIO_FEATURE_CONFIG_M6_SYS_CFG_GOLDPLUS_PLL_LVAL_SHFT 0xb #define HWIO_FEATURE_CONFIG_M6_SYS_CFG_APC1PLL_LVAL_BMSK 0x7f8 #define HWIO_FEATURE_CONFIG_M6_SYS_CFG_APC1PLL_LVAL_SHFT 0x3 #define HWIO_FEATURE_CONFIG_M6_APSS_KRYO_PP_DISABLE_BMSK 0x4 #define HWIO_FEATURE_CONFIG_M6_APSS_KRYO_PP_DISABLE_SHFT 0x2 #define HWIO_FEATURE_CONFIG_M6_SYS_CFG_L3_SIZE_RED_BMSK 0x2 #define HWIO_FEATURE_CONFIG_M6_SYS_CFG_L3_SIZE_RED_SHFT 0x1 #define HWIO_FEATURE_CONFIG_M6_AUTO_CCI_RCG_CFG_DISABLE_BMSK 0x1 #define HWIO_FEATURE_CONFIG_M6_AUTO_CCI_RCG_CFG_DISABLE_SHFT 0x0 #define HWIO_FEATURE_CONFIG_M7_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006020) #define HWIO_FEATURE_CONFIG_M7_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006020) #define HWIO_FEATURE_CONFIG_M7_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006020) #define HWIO_FEATURE_CONFIG_M7_RMSK 0xffffffff #define HWIO_FEATURE_CONFIG_M7_IN \ in_dword(HWIO_FEATURE_CONFIG_M7_ADDR) #define HWIO_FEATURE_CONFIG_M7_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_M7_ADDR, m) #define HWIO_FEATURE_CONFIG_M7_RSVD_BMSK 0xfffffc00 #define HWIO_FEATURE_CONFIG_M7_RSVD_SHFT 0xa #define HWIO_FEATURE_CONFIG_M7_EFUSE_Q6SS_HVX_EN_BMSK 0x200 #define HWIO_FEATURE_CONFIG_M7_EFUSE_Q6SS_HVX_EN_SHFT 0x9 #define HWIO_FEATURE_CONFIG_M7_EFUSE_Q6SS_HVX_EN_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_M7_EFUSE_Q6SS_HVX_EN_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_M7_EFUSE_Q6SS_HVX_HALF_BMSK 0x100 #define HWIO_FEATURE_CONFIG_M7_EFUSE_Q6SS_HVX_HALF_SHFT 0x8 #define HWIO_FEATURE_CONFIG_M7_TURING_Q6SS_PLL_L_MAX_15_8_BMSK 0xff #define HWIO_FEATURE_CONFIG_M7_TURING_Q6SS_PLL_L_MAX_15_8_SHFT 0x0 #define HWIO_FEATURE_CONFIG_NM0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006024) #define HWIO_FEATURE_CONFIG_NM0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006024) #define HWIO_FEATURE_CONFIG_NM0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006024) #define HWIO_FEATURE_CONFIG_NM0_RMSK 0xfeffffff #define HWIO_FEATURE_CONFIG_NM0_IN \ in_dword(HWIO_FEATURE_CONFIG_NM0_ADDR) #define HWIO_FEATURE_CONFIG_NM0_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_NM0_ADDR, m) #define HWIO_FEATURE_CONFIG_NM0_SM_BIST_DISABLE_BMSK 0x80000000 #define HWIO_FEATURE_CONFIG_NM0_SM_BIST_DISABLE_SHFT 0x1f #define HWIO_FEATURE_CONFIG_NM0_SM_BIST_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_SM_BIST_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_TIC_DISABLE_BMSK 0x40000000 #define HWIO_FEATURE_CONFIG_NM0_TIC_DISABLE_SHFT 0x1e #define HWIO_FEATURE_CONFIG_NM0_TIC_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_TIC_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_FUSE_SW_OVERRIDE_SOC_HW_VER_EN_BMSK 0x20000000 #define HWIO_FEATURE_CONFIG_NM0_FUSE_SW_OVERRIDE_SOC_HW_VER_EN_SHFT 0x1d #define HWIO_FEATURE_CONFIG_NM0_PRNG_TESTMODE_DISABLE_BMSK 0x10000000 #define HWIO_FEATURE_CONFIG_NM0_PRNG_TESTMODE_DISABLE_SHFT 0x1c #define HWIO_FEATURE_CONFIG_NM0_PRNG_TESTMODE_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_PRNG_TESTMODE_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_BOOT_ROM_PATCH_DISABLE_BMSK 0xe000000 #define HWIO_FEATURE_CONFIG_NM0_BOOT_ROM_PATCH_DISABLE_SHFT 0x19 #define HWIO_FEATURE_CONFIG_NM0_BOOT_ROM_PATCH_DISABLE_ENABLE_PATCHING_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_BOOT_ROM_PATCH_DISABLE_DISABLE_PATCHING_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC5_DEBUG_DISABLE_BMSK 0x800000 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC5_DEBUG_DISABLE_SHFT 0x17 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC4_DEBUG_DISABLE_BMSK 0x400000 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC4_DEBUG_DISABLE_SHFT 0x16 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC3_DEBUG_DISABLE_BMSK 0x200000 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC3_DEBUG_DISABLE_SHFT 0x15 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC2_DEBUG_DISABLE_BMSK 0x100000 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC2_DEBUG_DISABLE_SHFT 0x14 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC1_DEBUG_DISABLE_BMSK 0x80000 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC1_DEBUG_DISABLE_SHFT 0x13 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC_DEBUG_DISABLE_BMSK 0x40000 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC_DEBUG_DISABLE_SHFT 0x12 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_APPS_NIDEN_DISABLE_BMSK 0x20000 #define HWIO_FEATURE_CONFIG_NM0_QC_APPS_NIDEN_DISABLE_SHFT 0x11 #define HWIO_FEATURE_CONFIG_NM0_QC_APPS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_APPS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_APPS_DBGEN_DISABLE_BMSK 0x10000 #define HWIO_FEATURE_CONFIG_NM0_QC_APPS_DBGEN_DISABLE_SHFT 0x10 #define HWIO_FEATURE_CONFIG_NM0_QC_APPS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_APPS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_NS_NIDEN_DISABLE_BMSK 0x8000 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_NS_NIDEN_DISABLE_SHFT 0xf #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_NS_DBGEN_DISABLE_BMSK 0x4000 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_NS_DBGEN_DISABLE_SHFT 0xe #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_CP_NIDEN_DISABLE_BMSK 0x2000 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_CP_NIDEN_DISABLE_SHFT 0xd #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_CP_DBGEN_DISABLE_BMSK 0x1000 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_CP_DBGEN_DISABLE_SHFT 0xc #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MSS_NIDEN_DISABLE_BMSK 0x800 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MSS_NIDEN_DISABLE_SHFT 0xb #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MSS_DBGEN_DISABLE_BMSK 0x400 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MSS_DBGEN_DISABLE_SHFT 0xa #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_QSEE_SPNIDEN_DISABLE_BMSK 0x200 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_QSEE_SPNIDEN_DISABLE_SHFT 0x9 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_QSEE_SPIDEN_DISABLE_BMSK 0x100 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_QSEE_SPIDEN_DISABLE_SHFT 0x8 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_QC_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_NS_NIDEN_DISABLE_BMSK 0x80 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_NS_NIDEN_DISABLE_SHFT 0x7 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_NS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_NS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_NS_DBGEN_DISABLE_BMSK 0x40 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_NS_DBGEN_DISABLE_SHFT 0x6 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_NS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_NS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_CP_NIDEN_DISABLE_BMSK 0x20 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_CP_NIDEN_DISABLE_SHFT 0x5 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_CP_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_CP_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_CP_DBGEN_DISABLE_BMSK 0x10 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_CP_DBGEN_DISABLE_SHFT 0x4 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_CP_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_CP_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_MSS_NIDEN_DISABLE_BMSK 0x8 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_MSS_NIDEN_DISABLE_SHFT 0x3 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_MSS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_MSS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_MSS_DBGEN_DISABLE_BMSK 0x4 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_MSS_DBGEN_DISABLE_SHFT 0x2 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_MSS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_MSS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_QSEE_SPNIDEN_DISABLE_BMSK 0x2 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_QSEE_SPNIDEN_DISABLE_SHFT 0x1 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_QSEE_SPIDEN_DISABLE_BMSK 0x1 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_QSEE_SPIDEN_DISABLE_SHFT 0x0 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_QSEE_SPIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM0_PRIVATE_QSEE_SPIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006028) #define HWIO_FEATURE_CONFIG_NM1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006028) #define HWIO_FEATURE_CONFIG_NM1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006028) #define HWIO_FEATURE_CONFIG_NM1_RMSK 0xffffffff #define HWIO_FEATURE_CONFIG_NM1_IN \ in_dword(HWIO_FEATURE_CONFIG_NM1_ADDR) #define HWIO_FEATURE_CONFIG_NM1_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_NM1_ADDR, m) #define HWIO_FEATURE_CONFIG_NM1_RSVD_BMSK 0x80000000 #define HWIO_FEATURE_CONFIG_NM1_RSVD_SHFT 0x1f #define HWIO_FEATURE_CONFIG_NM1_MODEM_PBL_BOOT_BMSK 0x40000000 #define HWIO_FEATURE_CONFIG_NM1_MODEM_PBL_BOOT_SHFT 0x1e #define HWIO_FEATURE_CONFIG_NM1_APPS_BOOT_FROM_ROM_BMSK 0x20000000 #define HWIO_FEATURE_CONFIG_NM1_APPS_BOOT_FROM_ROM_SHFT 0x1d #define HWIO_FEATURE_CONFIG_NM1_ENABLE_DEVICE_IN_TEST_MODE_BMSK 0x10000000 #define HWIO_FEATURE_CONFIG_NM1_ENABLE_DEVICE_IN_TEST_MODE_SHFT 0x1c #define HWIO_FEATURE_CONFIG_NM1_QTI_ROOT_SIG_FORMAT_SEL_BMSK 0x8000000 #define HWIO_FEATURE_CONFIG_NM1_QTI_ROOT_SIG_FORMAT_SEL_SHFT 0x1b #define HWIO_FEATURE_CONFIG_NM1_CE_BAM_DISABLE_BMSK 0x4000000 #define HWIO_FEATURE_CONFIG_NM1_CE_BAM_DISABLE_SHFT 0x1a #define HWIO_FEATURE_CONFIG_NM1_CE_BAM_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM1_CE_BAM_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM1_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_BMSK 0x2000000 #define HWIO_FEATURE_CONFIG_NM1_LEGACY_MBNV6_OEM_AUTH_CTRL_SECBOOT_SHFT 0x19 #define HWIO_FEATURE_CONFIG_NM1_ARM_CE_DISABLE_USAGE_BMSK 0x1000000 #define HWIO_FEATURE_CONFIG_NM1_ARM_CE_DISABLE_USAGE_SHFT 0x18 #define HWIO_FEATURE_CONFIG_NM1_BOOT_ROM_CFG_BMSK 0xff0000 #define HWIO_FEATURE_CONFIG_NM1_BOOT_ROM_CFG_SHFT 0x10 #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_7_BMSK 0x8000 #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_7_SHFT 0xf #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_6_BMSK 0x4000 #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_6_SHFT 0xe #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_5_BMSK 0x2000 #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_5_SHFT 0xd #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_4_BMSK 0x1000 #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_4_SHFT 0xc #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_3_BMSK 0x800 #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_3_SHFT 0xb #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_2_BMSK 0x400 #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_2_SHFT 0xa #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_1_BMSK 0x200 #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_1_SHFT 0x9 #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_0_BMSK 0x100 #define HWIO_FEATURE_CONFIG_NM1_ACCU_RED_DEC_END_VAL_0_SHFT 0x8 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE7_BMSK 0x80 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE7_SHFT 0x7 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE6_BMSK 0x40 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE6_SHFT 0x6 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE5_BMSK 0x20 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE5_SHFT 0x5 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE4_BMSK 0x10 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE4_SHFT 0x4 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE3_BMSK 0x8 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE3_SHFT 0x3 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE2_BMSK 0x4 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE2_SHFT 0x2 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE1_BMSK 0x2 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE1_SHFT 0x1 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE0_BMSK 0x1 #define HWIO_FEATURE_CONFIG_NM1_P2S_ACCU_RED_DEC_END_VAL_FUSE0_SHFT 0x0 #define HWIO_FEATURE_CONFIG_NM2_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000602c) #define HWIO_FEATURE_CONFIG_NM2_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000602c) #define HWIO_FEATURE_CONFIG_NM2_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000602c) #define HWIO_FEATURE_CONFIG_NM2_RMSK 0xffffffff #define HWIO_FEATURE_CONFIG_NM2_IN \ in_dword(HWIO_FEATURE_CONFIG_NM2_ADDR) #define HWIO_FEATURE_CONFIG_NM2_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_NM2_ADDR, m) #define HWIO_FEATURE_CONFIG_NM2_TAP_GEN_SPARE_INSTR_DISABLE_13_0_BMSK 0xfffc0000 #define HWIO_FEATURE_CONFIG_NM2_TAP_GEN_SPARE_INSTR_DISABLE_13_0_SHFT 0x12 #define HWIO_FEATURE_CONFIG_NM2_TAP_INSTR_DISABLE_BMSK 0x3ffff #define HWIO_FEATURE_CONFIG_NM2_TAP_INSTR_DISABLE_SHFT 0x0 #define HWIO_FEATURE_CONFIG_NM3_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006030) #define HWIO_FEATURE_CONFIG_NM3_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006030) #define HWIO_FEATURE_CONFIG_NM3_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006030) #define HWIO_FEATURE_CONFIG_NM3_RMSK 0xffffffff #define HWIO_FEATURE_CONFIG_NM3_IN \ in_dword(HWIO_FEATURE_CONFIG_NM3_ADDR) #define HWIO_FEATURE_CONFIG_NM3_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_NM3_ADDR, m) #define HWIO_FEATURE_CONFIG_NM3_SEC_TAP_ACCESS_DISABLE_BMSK 0xfffc0000 #define HWIO_FEATURE_CONFIG_NM3_SEC_TAP_ACCESS_DISABLE_SHFT 0x12 #define HWIO_FEATURE_CONFIG_NM3_TAP_GEN_SPARE_INSTR_DISABLE_31_14_BMSK 0x3ffff #define HWIO_FEATURE_CONFIG_NM3_TAP_GEN_SPARE_INSTR_DISABLE_31_14_SHFT 0x0 #define HWIO_FEATURE_CONFIG_NM4_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006034) #define HWIO_FEATURE_CONFIG_NM4_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006034) #define HWIO_FEATURE_CONFIG_NM4_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006034) #define HWIO_FEATURE_CONFIG_NM4_RMSK 0xffff7bdf #define HWIO_FEATURE_CONFIG_NM4_IN \ in_dword(HWIO_FEATURE_CONFIG_NM4_ADDR) #define HWIO_FEATURE_CONFIG_NM4_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_NM4_ADDR, m) #define HWIO_FEATURE_CONFIG_NM4_MODEM_PBL_PATCH_VERSION_BMSK 0xfe000000 #define HWIO_FEATURE_CONFIG_NM4_MODEM_PBL_PATCH_VERSION_SHFT 0x19 #define HWIO_FEATURE_CONFIG_NM4_APPS_PBL_PATCH_VERSION_BMSK 0x1fc0000 #define HWIO_FEATURE_CONFIG_NM4_APPS_PBL_PATCH_VERSION_SHFT 0x12 #define HWIO_FEATURE_CONFIG_NM4_APPS_PBL_BOOT_SPEED_BMSK 0x30000 #define HWIO_FEATURE_CONFIG_NM4_APPS_PBL_BOOT_SPEED_SHFT 0x10 #define HWIO_FEATURE_CONFIG_NM4_APPS_PBL_BOOT_SPEED_ENUM_600_MHZ_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM4_APPS_PBL_BOOT_SPEED_XO_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM4_APPS_PBL_BOOT_SPEED_ENUM_1200_MHZ_FVAL 0x2 #define HWIO_FEATURE_CONFIG_NM4_APPS_PBL_BOOT_SPEED_NA_FVAL 0x3 #define HWIO_FEATURE_CONFIG_NM4_VENDOR_LOCK_BMSK 0x7800 #define HWIO_FEATURE_CONFIG_NM4_VENDOR_LOCK_SHFT 0xb #define HWIO_FEATURE_CONFIG_NM4_FOUNDRY_ID_BMSK 0x3c0 #define HWIO_FEATURE_CONFIG_NM4_FOUNDRY_ID_SHFT 0x6 #define HWIO_FEATURE_CONFIG_NM4_FOUNDRY_ID_TSMC_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM4_FOUNDRY_ID_GLOBAL_FOUNDRIES_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM4_FOUNDRY_ID_SAMSUNG_FVAL 0x2 #define HWIO_FEATURE_CONFIG_NM4_FOUNDRY_ID_IBM_FVAL 0x3 #define HWIO_FEATURE_CONFIG_NM4_FOUNDRY_ID_UMC_FVAL 0x4 #define HWIO_FEATURE_CONFIG_NM4_FOUNDRY_ID_SMIC_FVAL 0x5 #define HWIO_FEATURE_CONFIG_NM4_STACKED_MEMORY_ID_BMSK 0x1f #define HWIO_FEATURE_CONFIG_NM4_STACKED_MEMORY_ID_SHFT 0x0 #define HWIO_FEATURE_CONFIG_NM5_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006038) #define HWIO_FEATURE_CONFIG_NM5_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006038) #define HWIO_FEATURE_CONFIG_NM5_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006038) #define HWIO_FEATURE_CONFIG_NM5_RMSK 0xffffbfef #define HWIO_FEATURE_CONFIG_NM5_IN \ in_dword(HWIO_FEATURE_CONFIG_NM5_ADDR) #define HWIO_FEATURE_CONFIG_NM5_INM(m) \ in_dword_masked(HWIO_FEATURE_CONFIG_NM5_ADDR, m) #define HWIO_FEATURE_CONFIG_NM5_RSVD_BMSK 0xf0000000 #define HWIO_FEATURE_CONFIG_NM5_RSVD_SHFT 0x1c #define HWIO_FEATURE_CONFIG_NM5_SPU_MIRROR_IAR_STATE_BMSK 0xe000000 #define HWIO_FEATURE_CONFIG_NM5_SPU_MIRROR_IAR_STATE_SHFT 0x19 #define HWIO_FEATURE_CONFIG_NM5_SPU_MIRROR_IAR_STATE_DISABLED_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM5_SPU_MIRROR_IAR_STATE_INITIALIZING_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM5_SPU_MIRROR_IAR_STATE_ACTIVATED_FVAL 0x3 #define HWIO_FEATURE_CONFIG_NM5_SPU_MIRROR_IAR_STATE_DISABLED_ARI_EOL_FVAL 0x7 #define HWIO_FEATURE_CONFIG_NM5_ACCU_RED_DEC_END_VAL_MODEM_BMSK 0x1fe0000 #define HWIO_FEATURE_CONFIG_NM5_ACCU_RED_DEC_END_VAL_MODEM_SHFT 0x11 #define HWIO_FEATURE_CONFIG_NM5_KM_BOOT_INIT1_DISABLE_BMSK 0x10000 #define HWIO_FEATURE_CONFIG_NM5_KM_BOOT_INIT1_DISABLE_SHFT 0x10 #define HWIO_FEATURE_CONFIG_NM5_KM_BOOT_INIT0_DISABLE_BMSK 0x8000 #define HWIO_FEATURE_CONFIG_NM5_KM_BOOT_INIT0_DISABLE_SHFT 0xf #define HWIO_FEATURE_CONFIG_NM5_APCS_BOOT_TRIGGER_DISABLE_BMSK 0x2000 #define HWIO_FEATURE_CONFIG_NM5_APCS_BOOT_TRIGGER_DISABLE_SHFT 0xd #define HWIO_FEATURE_CONFIG_NM5_APCS_BOOT_TRIGGER_DISABLE_ENABLE_FVAL 0x0 #define HWIO_FEATURE_CONFIG_NM5_APCS_BOOT_TRIGGER_DISABLE_DISABLE_FVAL 0x1 #define HWIO_FEATURE_CONFIG_NM5_PBL_QSEE_BOOT_FLOW_DISABLE_BMSK 0x1000 #define HWIO_FEATURE_CONFIG_NM5_PBL_QSEE_BOOT_FLOW_DISABLE_SHFT 0xc #define HWIO_FEATURE_CONFIG_NM5_XBL_SEC_AUTH_DISABLE_BMSK 0x800 #define HWIO_FEATURE_CONFIG_NM5_XBL_SEC_AUTH_DISABLE_SHFT 0xb #define HWIO_FEATURE_CONFIG_NM5_MSM_PKG_TYPE_BMSK 0x400 #define HWIO_FEATURE_CONFIG_NM5_MSM_PKG_TYPE_SHFT 0xa #define HWIO_FEATURE_CONFIG_NM5_SPSS_CONFIG_MODE_BMSK 0x300 #define HWIO_FEATURE_CONFIG_NM5_SPSS_CONFIG_MODE_SHFT 0x8 #define HWIO_FEATURE_CONFIG_NM5_PERIPH_DRV_STRENGTH_SETTING__BMSK 0xe0 #define HWIO_FEATURE_CONFIG_NM5_PERIPH_DRV_STRENGTH_SETTING__SHFT 0x5 #define HWIO_FEATURE_CONFIG_NM5_APPS_PBL_PLL_CTRL_BMSK 0xf #define HWIO_FEATURE_CONFIG_NM5_APPS_PBL_PLL_CTRL_SHFT 0x0 #define HWIO_OEM_CONFIG0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006044) #define HWIO_OEM_CONFIG0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006044) #define HWIO_OEM_CONFIG0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006044) #define HWIO_OEM_CONFIG0_RMSK 0xffffffff #define HWIO_OEM_CONFIG0_IN \ in_dword(HWIO_OEM_CONFIG0_ADDR) #define HWIO_OEM_CONFIG0_INM(m) \ in_dword_masked(HWIO_OEM_CONFIG0_ADDR, m) #define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_BMSK 0x80000000 #define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_SHFT 0x1f #define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG0_SHARED_QSEE_SPNIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_BMSK 0x40000000 #define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_SHFT 0x1e #define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG0_SHARED_QSEE_SPIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_BMSK 0x20000000 #define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_SHFT 0x1d #define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG0_ALL_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_BMSK 0x10000000 #define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_SHFT 0x1c #define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG0_DEBUG_POLICY_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG0_SP_DISABLE_BMSK 0x8000000 #define HWIO_OEM_CONFIG0_SP_DISABLE_SHFT 0x1b #define HWIO_OEM_CONFIG0_SP_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG0_SP_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG0_UDK_DISABLE_BMSK 0x4000000 #define HWIO_OEM_CONFIG0_UDK_DISABLE_SHFT 0x1a #define HWIO_OEM_CONFIG0_UDK_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG0_UDK_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG0_DEBUG_DISABLE_IN_ROM_BMSK 0x2000000 #define HWIO_OEM_CONFIG0_DEBUG_DISABLE_IN_ROM_SHFT 0x19 #define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_BMSK 0x1000000 #define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_SHFT 0x18 #define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_DISABLE_FVAL 0x0 #define HWIO_OEM_CONFIG0_MSS_HASH_INTEGRITY_CHECK_ENABLE_ENABLE_FVAL 0x1 #define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_DISABLE_BMSK 0x800000 #define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_DISABLE_SHFT 0x17 #define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_DISABLE_DISABLE_FVAL 0x0 #define HWIO_OEM_CONFIG0_APPS_HASH_INTEGRITY_CHECK_DISABLE_ENABLE_FVAL 0x1 #define HWIO_OEM_CONFIG0_USB_SS_DISABLE_BMSK 0x400000 #define HWIO_OEM_CONFIG0_USB_SS_DISABLE_SHFT 0x16 #define HWIO_OEM_CONFIG0_USB_SS_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG0_USB_SS_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_BMSK 0x200000 #define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_SHFT 0x15 #define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_USE_OEM_ID_FVAL 0x0 #define HWIO_OEM_CONFIG0_SW_ROT_USE_SERIAL_NUM_USE_SERIAL_NUM_FVAL 0x1 #define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_BMSK 0x100000 #define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_SHFT 0x14 #define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG0_DISABLE_ROT_TRANSFER_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG0_IMAGE_ENCRYPTION_ENABLE_BMSK 0x80000 #define HWIO_OEM_CONFIG0_IMAGE_ENCRYPTION_ENABLE_SHFT 0x13 #define HWIO_OEM_CONFIG0_ROOT_CERT_TOTAL_NUM_BMSK 0x60000 #define HWIO_OEM_CONFIG0_ROOT_CERT_TOTAL_NUM_SHFT 0x11 #define HWIO_OEM_CONFIG0_PBL_USB_TYPE_C_DISABLE_BMSK 0x10000 #define HWIO_OEM_CONFIG0_PBL_USB_TYPE_C_DISABLE_SHFT 0x10 #define HWIO_OEM_CONFIG0_PBL_LOG_DISABLE_BMSK 0x8000 #define HWIO_OEM_CONFIG0_PBL_LOG_DISABLE_SHFT 0xf #define HWIO_OEM_CONFIG0_WDOG_EN_BMSK 0x4000 #define HWIO_OEM_CONFIG0_WDOG_EN_SHFT 0xe #define HWIO_OEM_CONFIG0_WDOG_EN_USE_GPIO_FVAL 0x0 #define HWIO_OEM_CONFIG0_WDOG_EN_IGNORE_GPIO_ENABLE_WDOG_FVAL 0x1 #define HWIO_OEM_CONFIG0_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_BMSK 0x2000 #define HWIO_OEM_CONFIG0_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_SHFT 0xd #define HWIO_OEM_CONFIG0_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_DISABLE_EDL_RESET_FVAL 0x0 #define HWIO_OEM_CONFIG0_PBL_FDL_TIMEOUT_RESET_FEATURE_ENABLE_ENABLE_EDL_RESET_FVAL 0x1 #define HWIO_OEM_CONFIG0_SW_FUSE_PROG_DISABLE_BMSK 0x1000 #define HWIO_OEM_CONFIG0_SW_FUSE_PROG_DISABLE_SHFT 0xc #define HWIO_OEM_CONFIG0_SPI_CLK_BOOT_FREQ_BMSK 0x800 #define HWIO_OEM_CONFIG0_SPI_CLK_BOOT_FREQ_SHFT 0xb #define HWIO_OEM_CONFIG0_PBL_QSPI_BOOT_EDL_ENABLED_BMSK 0x400 #define HWIO_OEM_CONFIG0_PBL_QSPI_BOOT_EDL_ENABLED_SHFT 0xa #define HWIO_OEM_CONFIG0_PBL_QSPI_BOOT_EDL_ENABLED_SD_USB_FVAL 0x0 #define HWIO_OEM_CONFIG0_PBL_QSPI_BOOT_EDL_ENABLED_QSPI_SD_USB_FVAL 0x1 #define HWIO_OEM_CONFIG0_FAST_BOOT_BMSK 0x3e0 #define HWIO_OEM_CONFIG0_FAST_BOOT_SHFT 0x5 #define HWIO_OEM_CONFIG0_FAST_BOOT_DEFAULT_FVAL 0x0 #define HWIO_OEM_CONFIG0_FAST_BOOT_SD_UFS_EDL_FVAL 0x1 #define HWIO_OEM_CONFIG0_FAST_BOOT_SD_EDL_FVAL 0x2 #define HWIO_OEM_CONFIG0_FAST_BOOT_USB_EDL_FVAL 0x3 #define HWIO_OEM_CONFIG0_FAST_BOOT_QSPI_EDL_FVAL 0x4 #define HWIO_OEM_CONFIG0_FAST_BOOT_SPI_EDL_FVAL 0x5 #define HWIO_OEM_CONFIG0_FAST_BOOT_UGSG4_SD_USB_EDL_FVAL 0x8 #define HWIO_OEM_CONFIG0_SDCC_ADMA_DISABLE_BMSK 0x10 #define HWIO_OEM_CONFIG0_SDCC_ADMA_DISABLE_SHFT 0x4 #define HWIO_OEM_CONFIG0_SDCC_ADMA_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG0_SDCC_ADMA_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_BMSK 0x8 #define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_SHFT 0x3 #define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL 0x0 #define HWIO_OEM_CONFIG0_FORCE_USB_BOOT_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL 0x1 #define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_BMSK 0x4 #define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_SHFT 0x2 #define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_USE_FORCE_USB_BOOT_GPIO_TO_FORCE_BOOT_FROM_USB_FVAL 0x0 #define HWIO_OEM_CONFIG0_FORCE_DLOAD_DISABLE_NOT_USE_FORCE_USB_BOOT_PIN_FVAL 0x1 #define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_BMSK 0x2 #define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_SHFT 0x1 #define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_TIMEOUT_DISABLED_FVAL 0x0 #define HWIO_OEM_CONFIG0_ENUM_TIMEOUT_TIMEOUT_ENABLED_90S_FVAL 0x1 #define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_BMSK 0x1 #define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_SHFT 0x0 #define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_DOWNLOADER_ENABLED_FVAL 0x0 #define HWIO_OEM_CONFIG0_E_DLOAD_DISABLE_DOWNLOADER_DISABLED_FVAL 0x1 #define HWIO_OEM_CONFIG1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006048) #define HWIO_OEM_CONFIG1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006048) #define HWIO_OEM_CONFIG1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006048) #define HWIO_OEM_CONFIG1_RMSK 0xffffffff #define HWIO_OEM_CONFIG1_IN \ in_dword(HWIO_OEM_CONFIG1_ADDR) #define HWIO_OEM_CONFIG1_INM(m) \ in_dword_masked(HWIO_OEM_CONFIG1_ADDR, m) #define HWIO_OEM_CONFIG1_RSVD1_BMSK 0xffffc000 #define HWIO_OEM_CONFIG1_RSVD1_SHFT 0xe #define HWIO_OEM_CONFIG1_SHARED_MISC5_DEBUG_DISABLE_BMSK 0x2000 #define HWIO_OEM_CONFIG1_SHARED_MISC5_DEBUG_DISABLE_SHFT 0xd #define HWIO_OEM_CONFIG1_SHARED_MISC5_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_MISC5_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_SHARED_MISC4_DEBUG_DISABLE_BMSK 0x1000 #define HWIO_OEM_CONFIG1_SHARED_MISC4_DEBUG_DISABLE_SHFT 0xc #define HWIO_OEM_CONFIG1_SHARED_MISC4_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_MISC4_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_SHARED_MISC3_DEBUG_DISABLE_BMSK 0x800 #define HWIO_OEM_CONFIG1_SHARED_MISC3_DEBUG_DISABLE_SHFT 0xb #define HWIO_OEM_CONFIG1_SHARED_MISC3_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_MISC3_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_SHARED_MISC2_DEBUG_DISABLE_BMSK 0x400 #define HWIO_OEM_CONFIG1_SHARED_MISC2_DEBUG_DISABLE_SHFT 0xa #define HWIO_OEM_CONFIG1_SHARED_MISC2_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_MISC2_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_SHARED_MISC1_DEBUG_DISABLE_BMSK 0x200 #define HWIO_OEM_CONFIG1_SHARED_MISC1_DEBUG_DISABLE_SHFT 0x9 #define HWIO_OEM_CONFIG1_SHARED_MISC1_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_MISC1_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_SHARED_MISC_DEBUG_DISABLE_BMSK 0x100 #define HWIO_OEM_CONFIG1_SHARED_MISC_DEBUG_DISABLE_SHFT 0x8 #define HWIO_OEM_CONFIG1_SHARED_MISC_DEBUG_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_MISC_DEBUG_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_BMSK 0x80 #define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_SHFT 0x7 #define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_APPS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_BMSK 0x40 #define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_SHFT 0x6 #define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_APPS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_BMSK 0x20 #define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_SHFT 0x5 #define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_NS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_BMSK 0x10 #define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_SHFT 0x4 #define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_NS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_BMSK 0x8 #define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_SHFT 0x3 #define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_CP_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_BMSK 0x4 #define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_SHFT 0x2 #define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_CP_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_BMSK 0x2 #define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_SHFT 0x1 #define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_MSS_NIDEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_BMSK 0x1 #define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_SHFT 0x0 #define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_ENABLE_FVAL 0x0 #define HWIO_OEM_CONFIG1_SHARED_MSS_DBGEN_DISABLE_DISABLE_FVAL 0x1 #define HWIO_OEM_CONFIG2_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000604c) #define HWIO_OEM_CONFIG2_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000604c) #define HWIO_OEM_CONFIG2_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000604c) #define HWIO_OEM_CONFIG2_RMSK 0xffffffff #define HWIO_OEM_CONFIG2_IN \ in_dword(HWIO_OEM_CONFIG2_ADDR) #define HWIO_OEM_CONFIG2_INM(m) \ in_dword_masked(HWIO_OEM_CONFIG2_ADDR, m) #define HWIO_OEM_CONFIG2_DISABLE_RSA_BMSK 0x80000000 #define HWIO_OEM_CONFIG2_DISABLE_RSA_SHFT 0x1f #define HWIO_OEM_CONFIG2_EKU_ENFORCEMENT_EN_BMSK 0x40000000 #define HWIO_OEM_CONFIG2_EKU_ENFORCEMENT_EN_SHFT 0x1e #define HWIO_OEM_CONFIG2_RSVD2_BMSK 0x3fff0000 #define HWIO_OEM_CONFIG2_RSVD2_SHFT 0x10 #define HWIO_OEM_CONFIG2_SPARE_REG31_SECURE_BMSK 0x8000 #define HWIO_OEM_CONFIG2_SPARE_REG31_SECURE_SHFT 0xf #define HWIO_OEM_CONFIG2_SPARE_REG31_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_OEM_CONFIG2_SPARE_REG31_SECURE_SECURE_FVAL 0x1 #define HWIO_OEM_CONFIG2_SPARE_REG30_SECURE_BMSK 0x4000 #define HWIO_OEM_CONFIG2_SPARE_REG30_SECURE_SHFT 0xe #define HWIO_OEM_CONFIG2_SPARE_REG30_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_OEM_CONFIG2_SPARE_REG30_SECURE_SECURE_FVAL 0x1 #define HWIO_OEM_CONFIG2_SPARE_REG29_SECURE_BMSK 0x2000 #define HWIO_OEM_CONFIG2_SPARE_REG29_SECURE_SHFT 0xd #define HWIO_OEM_CONFIG2_SPARE_REG29_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_OEM_CONFIG2_SPARE_REG29_SECURE_SECURE_FVAL 0x1 #define HWIO_OEM_CONFIG2_SPARE_REG28_SECURE_BMSK 0x1000 #define HWIO_OEM_CONFIG2_SPARE_REG28_SECURE_SHFT 0xc #define HWIO_OEM_CONFIG2_SPARE_REG28_SECURE_NOT_SECURE_FVAL 0x0 #define HWIO_OEM_CONFIG2_SPARE_REG28_SECURE_SECURE_FVAL 0x1 #define HWIO_OEM_CONFIG2_RSVD1_BMSK 0xff8 #define HWIO_OEM_CONFIG2_RSVD1_SHFT 0x3 #define HWIO_OEM_CONFIG2_SP_NVM_AR_CONFIG_BMSK 0x6 #define HWIO_OEM_CONFIG2_SP_NVM_AR_CONFIG_SHFT 0x1 #define HWIO_OEM_CONFIG2_RSVD0_BMSK 0x1 #define HWIO_OEM_CONFIG2_RSVD0_SHFT 0x0 #define HWIO_OEM_CONFIG3_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006050) #define HWIO_OEM_CONFIG3_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006050) #define HWIO_OEM_CONFIG3_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006050) #define HWIO_OEM_CONFIG3_RMSK 0xffffffff #define HWIO_OEM_CONFIG3_IN \ in_dword(HWIO_OEM_CONFIG3_ADDR) #define HWIO_OEM_CONFIG3_INM(m) \ in_dword_masked(HWIO_OEM_CONFIG3_ADDR, m) #define HWIO_OEM_CONFIG3_OEM_PRODUCT_ID_BMSK 0xffff0000 #define HWIO_OEM_CONFIG3_OEM_PRODUCT_ID_SHFT 0x10 #define HWIO_OEM_CONFIG3_OEM_HW_ID_BMSK 0xffff #define HWIO_OEM_CONFIG3_OEM_HW_ID_SHFT 0x0 #define HWIO_OEM_CONFIG4_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006054) #define HWIO_OEM_CONFIG4_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006054) #define HWIO_OEM_CONFIG4_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006054) #define HWIO_OEM_CONFIG4_RMSK 0xffffffff #define HWIO_OEM_CONFIG4_IN \ in_dword(HWIO_OEM_CONFIG4_ADDR) #define HWIO_OEM_CONFIG4_INM(m) \ in_dword_masked(HWIO_OEM_CONFIG4_ADDR, m) #define HWIO_OEM_CONFIG4_PERIPH_VID_BMSK 0xffff0000 #define HWIO_OEM_CONFIG4_PERIPH_VID_SHFT 0x10 #define HWIO_OEM_CONFIG4_PERIPH_PID_BMSK 0xffff #define HWIO_OEM_CONFIG4_PERIPH_PID_SHFT 0x0 #define HWIO_OEM_CONFIG5_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006058) #define HWIO_OEM_CONFIG5_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006058) #define HWIO_OEM_CONFIG5_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006058) #define HWIO_OEM_CONFIG5_RMSK 0xffffffff #define HWIO_OEM_CONFIG5_IN \ in_dword(HWIO_OEM_CONFIG5_ADDR) #define HWIO_OEM_CONFIG5_INM(m) \ in_dword_masked(HWIO_OEM_CONFIG5_ADDR, m) #define HWIO_OEM_CONFIG5_RSVD0_BMSK 0xffffff00 #define HWIO_OEM_CONFIG5_RSVD0_SHFT 0x8 #define HWIO_OEM_CONFIG5_ANTI_ROLLBACK_FEATURE_EN_BMSK 0xff #define HWIO_OEM_CONFIG5_ANTI_ROLLBACK_FEATURE_EN_SHFT 0x0 #define HWIO_BOOT_CONFIG_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006070) #define HWIO_BOOT_CONFIG_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006070) #define HWIO_BOOT_CONFIG_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006070) #define HWIO_BOOT_CONFIG_RMSK 0x1ff #define HWIO_BOOT_CONFIG_IN \ in_dword(HWIO_BOOT_CONFIG_ADDR) #define HWIO_BOOT_CONFIG_INM(m) \ in_dword_masked(HWIO_BOOT_CONFIG_ADDR, m) #define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_BMSK 0x180 #define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_SHFT 0x7 #define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_ENUM_600_MHZ_FVAL 0x0 #define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_ENUM_300_MHZ_FVAL 0x1 #define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_CXO_FVAL 0x2 #define HWIO_BOOT_CONFIG_APPS_PBL_BOOT_SPEED_NA_FVAL 0x3 #define HWIO_BOOT_CONFIG_APPS_BOOT_FROM_ROM_BMSK 0x40 #define HWIO_BOOT_CONFIG_APPS_BOOT_FROM_ROM_SHFT 0x6 #define HWIO_BOOT_CONFIG_FAST_BOOT_BMSK 0x3e #define HWIO_BOOT_CONFIG_FAST_BOOT_SHFT 0x1 #define HWIO_BOOT_CONFIG_FAST_BOOT_DEFAULT_FVAL 0x0 #define HWIO_BOOT_CONFIG_FAST_BOOT_PCIE_FVAL 0x1 #define HWIO_BOOT_CONFIG_FAST_BOOT_USB_FVAL 0x2 #define HWIO_BOOT_CONFIG_FAST_BOOT_EMMC_USB_FVAL 0x3 #define HWIO_BOOT_CONFIG_WDOG_EN_BMSK 0x1 #define HWIO_BOOT_CONFIG_WDOG_EN_SHFT 0x0 #define HWIO_BOOT_CONFIG_WDOG_EN_GPIO_CONTROLLED_FVAL 0x0 #define HWIO_BOOT_CONFIG_WDOG_EN_ENABLE_WDOG_FVAL 0x1 #define HWIO_SECURE_BOOTn_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x00006078 + 0x4 * (n)) #define HWIO_SECURE_BOOTn_PHYS(n) (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006078 + 0x4 * (n)) #define HWIO_SECURE_BOOTn_OFFS(n) (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006078 + 0x4 * (n)) #define HWIO_SECURE_BOOTn_RMSK 0x1ff #define HWIO_SECURE_BOOTn_MAXn 14 #define HWIO_SECURE_BOOTn_INI(n) \ in_dword_masked(HWIO_SECURE_BOOTn_ADDR(n), HWIO_SECURE_BOOTn_RMSK) #define HWIO_SECURE_BOOTn_INMI(n,mask) \ in_dword_masked(HWIO_SECURE_BOOTn_ADDR(n), mask) #define HWIO_SECURE_BOOTn_FUSE_SRC_BMSK 0x100 #define HWIO_SECURE_BOOTn_FUSE_SRC_SHFT 0x8 #define HWIO_SECURE_BOOTn_FUSE_SRC_QUALCOMM_FVAL 0x0 #define HWIO_SECURE_BOOTn_FUSE_SRC_OEM_FVAL 0x1 #define HWIO_SECURE_BOOTn_RSVD_7_BMSK 0x80 #define HWIO_SECURE_BOOTn_RSVD_7_SHFT 0x7 #define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_BMSK 0x40 #define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_SHFT 0x6 #define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_USE_OEM_ID_FVAL 0x0 #define HWIO_SECURE_BOOTn_USE_SERIAL_NUM_USE_SERIAL_NUM_FVAL 0x1 #define HWIO_SECURE_BOOTn_AUTH_EN_BMSK 0x20 #define HWIO_SECURE_BOOTn_AUTH_EN_SHFT 0x5 #define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_BMSK 0x10 #define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_SHFT 0x4 #define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_SHA_256_HASH_OF_ROOT_CERTIFICATE_IS_IN_ROM_FVAL 0x0 #define HWIO_SECURE_BOOTn_PK_HASH_IN_FUSE_SHA_256_HASH_OF_ROOT_CERTIFICATE_IS_IN_PK_HASH_FVAL 0x1 #define HWIO_SECURE_BOOTn_ROM_PK_HASH_INDEX_BMSK 0xf #define HWIO_SECURE_BOOTn_ROM_PK_HASH_INDEX_SHFT 0x0 #define HWIO_QSEE_INV_OVERRIDE_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000060c0) #define HWIO_QSEE_INV_OVERRIDE_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060c0) #define HWIO_QSEE_INV_OVERRIDE_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060c0) #define HWIO_QSEE_INV_OVERRIDE_RMSK 0xffffffff #define HWIO_QSEE_INV_OVERRIDE_IN \ in_dword(HWIO_QSEE_INV_OVERRIDE_ADDR) #define HWIO_QSEE_INV_OVERRIDE_INM(m) \ in_dword_masked(HWIO_QSEE_INV_OVERRIDE_ADDR, m) #define HWIO_QSEE_INV_OVERRIDE_OUT(v) \ out_dword(HWIO_QSEE_INV_OVERRIDE_ADDR,v) #define HWIO_QSEE_INV_OVERRIDE_OUTM(m,v) \ out_dword_masked_ns(HWIO_QSEE_INV_OVERRIDE_ADDR,m,v,HWIO_QSEE_INV_OVERRIDE_IN) #define HWIO_QSEE_INV_OVERRIDE_RSVD_31_1_BMSK 0xfffffffe #define HWIO_QSEE_INV_OVERRIDE_RSVD_31_1_SHFT 0x1 #define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_BMSK 0x1 #define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_SHFT 0x0 #define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_QSEE_INV_OVERRIDE_SHARED_QSEE_SPIDEN_DISABLE_QC_FUSE_VALUE_FVAL 0x1 #define HWIO_QSEE_NI_OVERRIDE_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000060c4) #define HWIO_QSEE_NI_OVERRIDE_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060c4) #define HWIO_QSEE_NI_OVERRIDE_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060c4) #define HWIO_QSEE_NI_OVERRIDE_RMSK 0xffffffff #define HWIO_QSEE_NI_OVERRIDE_IN \ in_dword(HWIO_QSEE_NI_OVERRIDE_ADDR) #define HWIO_QSEE_NI_OVERRIDE_INM(m) \ in_dword_masked(HWIO_QSEE_NI_OVERRIDE_ADDR, m) #define HWIO_QSEE_NI_OVERRIDE_OUT(v) \ out_dword(HWIO_QSEE_NI_OVERRIDE_ADDR,v) #define HWIO_QSEE_NI_OVERRIDE_OUTM(m,v) \ out_dword_masked_ns(HWIO_QSEE_NI_OVERRIDE_ADDR,m,v,HWIO_QSEE_NI_OVERRIDE_IN) #define HWIO_QSEE_NI_OVERRIDE_RSVD_31_1_BMSK 0xfffffffe #define HWIO_QSEE_NI_OVERRIDE_RSVD_31_1_SHFT 0x1 #define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_BMSK 0x1 #define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_SHFT 0x0 #define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_QSEE_NI_OVERRIDE_SHARED_QSEE_SPNIDEN_DISABLE_QC_FUSE_VALUE_FVAL 0x1 #define HWIO_MSS_INV_OVERRIDE_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000060c8) #define HWIO_MSS_INV_OVERRIDE_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060c8) #define HWIO_MSS_INV_OVERRIDE_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060c8) #define HWIO_MSS_INV_OVERRIDE_RMSK 0xffffffff #define HWIO_MSS_INV_OVERRIDE_IN \ in_dword(HWIO_MSS_INV_OVERRIDE_ADDR) #define HWIO_MSS_INV_OVERRIDE_INM(m) \ in_dword_masked(HWIO_MSS_INV_OVERRIDE_ADDR, m) #define HWIO_MSS_INV_OVERRIDE_OUT(v) \ out_dword(HWIO_MSS_INV_OVERRIDE_ADDR,v) #define HWIO_MSS_INV_OVERRIDE_OUTM(m,v) \ out_dword_masked_ns(HWIO_MSS_INV_OVERRIDE_ADDR,m,v,HWIO_MSS_INV_OVERRIDE_IN) #define HWIO_MSS_INV_OVERRIDE_RSVD_31_1_BMSK 0xfffffffe #define HWIO_MSS_INV_OVERRIDE_RSVD_31_1_SHFT 0x1 #define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_BMSK 0x1 #define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_SHFT 0x0 #define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_MSS_INV_OVERRIDE_SHARED_MSS_DBGEN_DISABLE_QC_FUSE_VALUE_FVAL 0x1 #define HWIO_MSS_NI_OVERRIDE_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000060cc) #define HWIO_MSS_NI_OVERRIDE_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060cc) #define HWIO_MSS_NI_OVERRIDE_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060cc) #define HWIO_MSS_NI_OVERRIDE_RMSK 0xffffffff #define HWIO_MSS_NI_OVERRIDE_IN \ in_dword(HWIO_MSS_NI_OVERRIDE_ADDR) #define HWIO_MSS_NI_OVERRIDE_INM(m) \ in_dword_masked(HWIO_MSS_NI_OVERRIDE_ADDR, m) #define HWIO_MSS_NI_OVERRIDE_OUT(v) \ out_dword(HWIO_MSS_NI_OVERRIDE_ADDR,v) #define HWIO_MSS_NI_OVERRIDE_OUTM(m,v) \ out_dword_masked_ns(HWIO_MSS_NI_OVERRIDE_ADDR,m,v,HWIO_MSS_NI_OVERRIDE_IN) #define HWIO_MSS_NI_OVERRIDE_RSVD_31_1_BMSK 0xfffffffe #define HWIO_MSS_NI_OVERRIDE_RSVD_31_1_SHFT 0x1 #define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_BMSK 0x1 #define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_SHFT 0x0 #define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_MSS_NI_OVERRIDE_SHARED_MSS_NIDEN_DISABLE_QC_FUSE_VALUE_FVAL 0x1 #define HWIO_CP_INV_OVERRIDE_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000060d0) #define HWIO_CP_INV_OVERRIDE_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060d0) #define HWIO_CP_INV_OVERRIDE_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060d0) #define HWIO_CP_INV_OVERRIDE_RMSK 0xffffffff #define HWIO_CP_INV_OVERRIDE_IN \ in_dword(HWIO_CP_INV_OVERRIDE_ADDR) #define HWIO_CP_INV_OVERRIDE_INM(m) \ in_dword_masked(HWIO_CP_INV_OVERRIDE_ADDR, m) #define HWIO_CP_INV_OVERRIDE_OUT(v) \ out_dword(HWIO_CP_INV_OVERRIDE_ADDR,v) #define HWIO_CP_INV_OVERRIDE_OUTM(m,v) \ out_dword_masked_ns(HWIO_CP_INV_OVERRIDE_ADDR,m,v,HWIO_CP_INV_OVERRIDE_IN) #define HWIO_CP_INV_OVERRIDE_RSVD_31_1_BMSK 0xfffffffe #define HWIO_CP_INV_OVERRIDE_RSVD_31_1_SHFT 0x1 #define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_BMSK 0x1 #define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_SHFT 0x0 #define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_CP_INV_OVERRIDE_SHARED_CP_DBGEN_DISABLE_QC_FUSE_VALUE_FVAL 0x1 #define HWIO_CP_NI_OVERRIDE_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000060d4) #define HWIO_CP_NI_OVERRIDE_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060d4) #define HWIO_CP_NI_OVERRIDE_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060d4) #define HWIO_CP_NI_OVERRIDE_RMSK 0xffffffff #define HWIO_CP_NI_OVERRIDE_IN \ in_dword(HWIO_CP_NI_OVERRIDE_ADDR) #define HWIO_CP_NI_OVERRIDE_INM(m) \ in_dword_masked(HWIO_CP_NI_OVERRIDE_ADDR, m) #define HWIO_CP_NI_OVERRIDE_OUT(v) \ out_dword(HWIO_CP_NI_OVERRIDE_ADDR,v) #define HWIO_CP_NI_OVERRIDE_OUTM(m,v) \ out_dword_masked_ns(HWIO_CP_NI_OVERRIDE_ADDR,m,v,HWIO_CP_NI_OVERRIDE_IN) #define HWIO_CP_NI_OVERRIDE_RSVD_31_1_BMSK 0xfffffffe #define HWIO_CP_NI_OVERRIDE_RSVD_31_1_SHFT 0x1 #define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_BMSK 0x1 #define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_SHFT 0x0 #define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_CP_NI_OVERRIDE_SHARED_CP_NIDEN_DISABLE_QC_FUSE_VALUE_FVAL 0x1 #define HWIO_NS_INV_OVERRIDE_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000060d8) #define HWIO_NS_INV_OVERRIDE_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060d8) #define HWIO_NS_INV_OVERRIDE_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060d8) #define HWIO_NS_INV_OVERRIDE_RMSK 0xffffffff #define HWIO_NS_INV_OVERRIDE_IN \ in_dword(HWIO_NS_INV_OVERRIDE_ADDR) #define HWIO_NS_INV_OVERRIDE_INM(m) \ in_dword_masked(HWIO_NS_INV_OVERRIDE_ADDR, m) #define HWIO_NS_INV_OVERRIDE_OUT(v) \ out_dword(HWIO_NS_INV_OVERRIDE_ADDR,v) #define HWIO_NS_INV_OVERRIDE_OUTM(m,v) \ out_dword_masked_ns(HWIO_NS_INV_OVERRIDE_ADDR,m,v,HWIO_NS_INV_OVERRIDE_IN) #define HWIO_NS_INV_OVERRIDE_RSVD_31_5_BMSK 0xffffffe0 #define HWIO_NS_INV_OVERRIDE_RSVD_31_5_SHFT 0x5 #define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_BMSK 0x10 #define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_SHFT 0x4 #define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_NS_INV_OVERRIDE_APPS_DBGEN_DISABLE_QC_FUSE_VALUE_FVAL 0x1 #define HWIO_NS_INV_OVERRIDE_RSVD_3_1_BMSK 0xe #define HWIO_NS_INV_OVERRIDE_RSVD_3_1_SHFT 0x1 #define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_BMSK 0x1 #define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_SHFT 0x0 #define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_NS_INV_OVERRIDE_SHARED_NS_DBGEN_DISABLE_QC_FUSE_VALUE_FVAL 0x1 #define HWIO_NS_NI_OVERRIDE_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000060dc) #define HWIO_NS_NI_OVERRIDE_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060dc) #define HWIO_NS_NI_OVERRIDE_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060dc) #define HWIO_NS_NI_OVERRIDE_RMSK 0xffffffff #define HWIO_NS_NI_OVERRIDE_IN \ in_dword(HWIO_NS_NI_OVERRIDE_ADDR) #define HWIO_NS_NI_OVERRIDE_INM(m) \ in_dword_masked(HWIO_NS_NI_OVERRIDE_ADDR, m) #define HWIO_NS_NI_OVERRIDE_OUT(v) \ out_dword(HWIO_NS_NI_OVERRIDE_ADDR,v) #define HWIO_NS_NI_OVERRIDE_OUTM(m,v) \ out_dword_masked_ns(HWIO_NS_NI_OVERRIDE_ADDR,m,v,HWIO_NS_NI_OVERRIDE_IN) #define HWIO_NS_NI_OVERRIDE_RSVD_31_5_BMSK 0xffffffe0 #define HWIO_NS_NI_OVERRIDE_RSVD_31_5_SHFT 0x5 #define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_BMSK 0x10 #define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_SHFT 0x4 #define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_NS_NI_OVERRIDE_APPS_NIDEN_DISABLE_QC_FUSE_VALUE_FVAL 0x1 #define HWIO_NS_NI_OVERRIDE_RSVD_3_1_BMSK 0xe #define HWIO_NS_NI_OVERRIDE_RSVD_3_1_SHFT 0x1 #define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_BMSK 0x1 #define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_SHFT 0x0 #define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_NS_NI_OVERRIDE_SHARED_NS_NIDEN_DISABLE_QC_FUSE_VALUE_FVAL 0x1 #define HWIO_MISC_DEBUG_OVERRIDE_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000060e0) #define HWIO_MISC_DEBUG_OVERRIDE_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000060e0) #define HWIO_MISC_DEBUG_OVERRIDE_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000060e0) #define HWIO_MISC_DEBUG_OVERRIDE_RMSK 0xffffffff #define HWIO_MISC_DEBUG_OVERRIDE_IN \ in_dword(HWIO_MISC_DEBUG_OVERRIDE_ADDR) #define HWIO_MISC_DEBUG_OVERRIDE_INM(m) \ in_dword_masked(HWIO_MISC_DEBUG_OVERRIDE_ADDR, m) #define HWIO_MISC_DEBUG_OVERRIDE_OUT(v) \ out_dword(HWIO_MISC_DEBUG_OVERRIDE_ADDR,v) #define HWIO_MISC_DEBUG_OVERRIDE_OUTM(m,v) \ out_dword_masked_ns(HWIO_MISC_DEBUG_OVERRIDE_ADDR,m,v,HWIO_MISC_DEBUG_OVERRIDE_IN) #define HWIO_MISC_DEBUG_OVERRIDE_RSVD_31_6_BMSK 0xffffffc0 #define HWIO_MISC_DEBUG_OVERRIDE_RSVD_31_6_SHFT 0x6 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC5_DEBUG_DISABLE_BMSK 0x20 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC5_DEBUG_DISABLE_SHFT 0x5 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC5_DEBUG_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC5_DEBUG_DISABLE_ZERO_FVAL 0x1 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC4_DEBUG_DISABLE_BMSK 0x10 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC4_DEBUG_DISABLE_SHFT 0x4 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC4_DEBUG_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC4_DEBUG_DISABLE_ZERO_FVAL 0x1 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC3_DEBUG_DISABLE_BMSK 0x8 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC3_DEBUG_DISABLE_SHFT 0x3 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC3_DEBUG_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC3_DEBUG_DISABLE_ZERO_FVAL 0x1 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC2_DEBUG_DISABLE_BMSK 0x4 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC2_DEBUG_DISABLE_SHFT 0x2 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC2_DEBUG_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC2_DEBUG_DISABLE_ZERO_FVAL 0x1 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC1_DEBUG_DISABLE_BMSK 0x2 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC1_DEBUG_DISABLE_SHFT 0x1 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC1_DEBUG_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC1_DEBUG_DISABLE_ZERO_FVAL 0x1 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC_DEBUG_DISABLE_BMSK 0x1 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC_DEBUG_DISABLE_SHFT 0x0 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC_DEBUG_DISABLE_FUSE_VALUE_FVAL 0x0 #define HWIO_MISC_DEBUG_OVERRIDE_SHARED_MISC_DEBUG_DISABLE_QC_FUSE_VALUE_FVAL 0x1 #define HWIO_CAPT_SEC_GPIO_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006100) #define HWIO_CAPT_SEC_GPIO_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006100) #define HWIO_CAPT_SEC_GPIO_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006100) #define HWIO_CAPT_SEC_GPIO_RMSK 0x1fff #define HWIO_CAPT_SEC_GPIO_IN \ in_dword(HWIO_CAPT_SEC_GPIO_ADDR) #define HWIO_CAPT_SEC_GPIO_INM(m) \ in_dword_masked(HWIO_CAPT_SEC_GPIO_ADDR, m) #define HWIO_CAPT_SEC_GPIO_OUT(v) \ out_dword(HWIO_CAPT_SEC_GPIO_ADDR,v) #define HWIO_CAPT_SEC_GPIO_OUTM(m,v) \ out_dword_masked_ns(HWIO_CAPT_SEC_GPIO_ADDR,m,v,HWIO_CAPT_SEC_GPIO_IN) #define HWIO_CAPT_SEC_GPIO_FORCE_USB_BOOT_GPIO_BMSK 0x1000 #define HWIO_CAPT_SEC_GPIO_FORCE_USB_BOOT_GPIO_SHFT 0xc #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_AUTH_EN_BMSK 0x800 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_AUTH_EN_SHFT 0xb #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_PK_HASH_IN_FUSE_BMSK 0x400 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_AP_PK_HASH_IN_FUSE_SHFT 0xa #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_ALL_USE_SERIAL_NUM_BMSK 0x200 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_ALL_USE_SERIAL_NUM_SHFT 0x9 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_PK_HASH_INDEX_SRC_BMSK 0x100 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_PK_HASH_INDEX_SRC_SHFT 0x8 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_PBL_BOOT_SPEED_BMSK 0xc0 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_PBL_BOOT_SPEED_SHFT 0x6 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_BOOT_FROM_ROM_BMSK 0x20 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_APPS_BOOT_FROM_ROM_SHFT 0x5 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_FAST_BOOT_BMSK 0x1e #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_FAST_BOOT_SHFT 0x1 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_WDOG_DISABLE_BMSK 0x1 #define HWIO_CAPT_SEC_GPIO_BOOT_CONFIG_GPIO_WDOG_DISABLE_SHFT 0x0 #define HWIO_APP_PROC_CFG_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006110) #define HWIO_APP_PROC_CFG_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006110) #define HWIO_APP_PROC_CFG_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006110) #define HWIO_APP_PROC_CFG_RMSK 0xfffff #define HWIO_APP_PROC_CFG_IN \ in_dword(HWIO_APP_PROC_CFG_ADDR) #define HWIO_APP_PROC_CFG_INM(m) \ in_dword_masked(HWIO_APP_PROC_CFG_ADDR, m) #define HWIO_APP_PROC_CFG_OUT(v) \ out_dword(HWIO_APP_PROC_CFG_ADDR,v) #define HWIO_APP_PROC_CFG_OUTM(m,v) \ out_dword_masked_ns(HWIO_APP_PROC_CFG_ADDR,m,v,HWIO_APP_PROC_CFG_IN) #define HWIO_APP_PROC_CFG_SPARE0_BMSK 0xc0000 #define HWIO_APP_PROC_CFG_SPARE0_SHFT 0x12 #define HWIO_APP_PROC_CFG_SPARE1_BMSK 0x30000 #define HWIO_APP_PROC_CFG_SPARE1_SHFT 0x10 #define HWIO_APP_PROC_CFG_APPS_CFG_MISC2_BMSK 0xf000 #define HWIO_APP_PROC_CFG_APPS_CFG_MISC2_SHFT 0xc #define HWIO_APP_PROC_CFG_APPS_CFG_MISC1_BMSK 0xf00 #define HWIO_APP_PROC_CFG_APPS_CFG_MISC1_SHFT 0x8 #define HWIO_APP_PROC_CFG_APPS_CFG_MISC0_BMSK 0xc0 #define HWIO_APP_PROC_CFG_APPS_CFG_MISC0_SHFT 0x6 #define HWIO_APP_PROC_CFG_APPS_CP15_DISABLE_BMSK 0x20 #define HWIO_APP_PROC_CFG_APPS_CP15_DISABLE_SHFT 0x5 #define HWIO_APP_PROC_CFG_APPS_CFG_NMFI_BMSK 0x10 #define HWIO_APP_PROC_CFG_APPS_CFG_NMFI_SHFT 0x4 #define HWIO_APP_PROC_CFG_APPS_CFG_NMFI_NORMAL_FVAL 0x0 #define HWIO_APP_PROC_CFG_APPS_CFG_NMFI_DISABLE_FVAL 0x1 #define HWIO_APP_PROC_CFG_SHARED_QSEE_SPNIDEN_BMSK 0x8 #define HWIO_APP_PROC_CFG_SHARED_QSEE_SPNIDEN_SHFT 0x3 #define HWIO_APP_PROC_CFG_SHARED_CP_NIDEN_BMSK 0x4 #define HWIO_APP_PROC_CFG_SHARED_CP_NIDEN_SHFT 0x2 #define HWIO_APP_PROC_CFG_SHARED_NS_NIDEN_BMSK 0x2 #define HWIO_APP_PROC_CFG_SHARED_NS_NIDEN_SHFT 0x1 #define HWIO_APP_PROC_CFG_APPS_NIDEN_BMSK 0x1 #define HWIO_APP_PROC_CFG_APPS_NIDEN_SHFT 0x0 #define HWIO_MSS_PROC_CFG_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006114) #define HWIO_MSS_PROC_CFG_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006114) #define HWIO_MSS_PROC_CFG_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006114) #define HWIO_MSS_PROC_CFG_RMSK 0x1 #define HWIO_MSS_PROC_CFG_IN \ in_dword(HWIO_MSS_PROC_CFG_ADDR) #define HWIO_MSS_PROC_CFG_INM(m) \ in_dword_masked(HWIO_MSS_PROC_CFG_ADDR, m) #define HWIO_MSS_PROC_CFG_OUT(v) \ out_dword(HWIO_MSS_PROC_CFG_ADDR,v) #define HWIO_MSS_PROC_CFG_OUTM(m,v) \ out_dword_masked_ns(HWIO_MSS_PROC_CFG_ADDR,m,v,HWIO_MSS_PROC_CFG_IN) #define HWIO_MSS_PROC_CFG_SHARED_MSS_NIDEN_BMSK 0x1 #define HWIO_MSS_PROC_CFG_SHARED_MSS_NIDEN_SHFT 0x0 #define HWIO_QFPROM_CLK_CTL_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006118) #define HWIO_QFPROM_CLK_CTL_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006118) #define HWIO_QFPROM_CLK_CTL_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006118) #define HWIO_QFPROM_CLK_CTL_RMSK 0x1 #define HWIO_QFPROM_CLK_CTL_IN \ in_dword(HWIO_QFPROM_CLK_CTL_ADDR) #define HWIO_QFPROM_CLK_CTL_INM(m) \ in_dword_masked(HWIO_QFPROM_CLK_CTL_ADDR, m) #define HWIO_QFPROM_CLK_CTL_OUT(v) \ out_dword(HWIO_QFPROM_CLK_CTL_ADDR,v) #define HWIO_QFPROM_CLK_CTL_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_CLK_CTL_ADDR,m,v,HWIO_QFPROM_CLK_CTL_IN) #define HWIO_QFPROM_CLK_CTL_CLK_HALT_BMSK 0x1 #define HWIO_QFPROM_CLK_CTL_CLK_HALT_SHFT 0x0 #define HWIO_QFPROM_CLK_CTL_CLK_HALT_CLK_ENABLED_FVAL 0x0 #define HWIO_QFPROM_CLK_CTL_CLK_HALT_CLK_DISABLED_FVAL 0x1 #define HWIO_JTAG_ID_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006130) #define HWIO_JTAG_ID_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006130) #define HWIO_JTAG_ID_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006130) #define HWIO_JTAG_ID_RMSK 0xffffffff #define HWIO_JTAG_ID_IN \ in_dword(HWIO_JTAG_ID_ADDR) #define HWIO_JTAG_ID_INM(m) \ in_dword_masked(HWIO_JTAG_ID_ADDR, m) #define HWIO_JTAG_ID_JTAG_ID_BMSK 0xffffffff #define HWIO_JTAG_ID_JTAG_ID_SHFT 0x0 #define HWIO_SERIAL_NUM_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006134) #define HWIO_SERIAL_NUM_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006134) #define HWIO_SERIAL_NUM_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006134) #define HWIO_SERIAL_NUM_RMSK 0xffffffff #define HWIO_SERIAL_NUM_IN \ in_dword(HWIO_SERIAL_NUM_ADDR) #define HWIO_SERIAL_NUM_INM(m) \ in_dword_masked(HWIO_SERIAL_NUM_ADDR, m) #define HWIO_SERIAL_NUM_SERIAL_NUM_BMSK 0xffffffff #define HWIO_SERIAL_NUM_SERIAL_NUM_SHFT 0x0 #define HWIO_OEM_ID_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006138) #define HWIO_OEM_ID_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006138) #define HWIO_OEM_ID_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006138) #define HWIO_OEM_ID_RMSK 0xffffffff #define HWIO_OEM_ID_IN \ in_dword(HWIO_OEM_ID_ADDR) #define HWIO_OEM_ID_INM(m) \ in_dword_masked(HWIO_OEM_ID_ADDR, m) #define HWIO_OEM_ID_OEM_ID_BMSK 0xffff0000 #define HWIO_OEM_ID_OEM_ID_SHFT 0x10 #define HWIO_OEM_ID_OEM_PRODUCT_ID_BMSK 0xffff #define HWIO_OEM_ID_OEM_PRODUCT_ID_SHFT 0x0 #define HWIO_TEST_BUS_SEL_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000613c) #define HWIO_TEST_BUS_SEL_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000613c) #define HWIO_TEST_BUS_SEL_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000613c) #define HWIO_TEST_BUS_SEL_RMSK 0x7 #define HWIO_TEST_BUS_SEL_IN \ in_dword(HWIO_TEST_BUS_SEL_ADDR) #define HWIO_TEST_BUS_SEL_INM(m) \ in_dword_masked(HWIO_TEST_BUS_SEL_ADDR, m) #define HWIO_TEST_BUS_SEL_OUT(v) \ out_dword(HWIO_TEST_BUS_SEL_ADDR,v) #define HWIO_TEST_BUS_SEL_OUTM(m,v) \ out_dword_masked_ns(HWIO_TEST_BUS_SEL_ADDR,m,v,HWIO_TEST_BUS_SEL_IN) #define HWIO_TEST_BUS_SEL_TEST_EN_BMSK 0x4 #define HWIO_TEST_BUS_SEL_TEST_EN_SHFT 0x2 #define HWIO_TEST_BUS_SEL_TEST_EN_DEBUG_DISABLED_FVAL 0x0 #define HWIO_TEST_BUS_SEL_TEST_EN_DEBUG_ENABLED_FVAL 0x1 #define HWIO_TEST_BUS_SEL_TEST_SELECT_BMSK 0x3 #define HWIO_TEST_BUS_SEL_TEST_SELECT_SHFT 0x0 #define HWIO_TEST_BUS_SEL_TEST_SELECT_FUSE_SENSE_FVAL 0x0 #define HWIO_TEST_BUS_SEL_TEST_SELECT_QFPROM_ARBITER_FVAL 0x1 #define HWIO_TEST_BUS_SEL_TEST_SELECT_SW_FVAL 0x2 #define HWIO_TEST_BUS_SEL_TEST_SELECT_ACC_FVAL 0x3 #define HWIO_SPDM_DYN_SECURE_MODE_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006140) #define HWIO_SPDM_DYN_SECURE_MODE_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006140) #define HWIO_SPDM_DYN_SECURE_MODE_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006140) #define HWIO_SPDM_DYN_SECURE_MODE_RMSK 0x1 #define HWIO_SPDM_DYN_SECURE_MODE_IN \ in_dword(HWIO_SPDM_DYN_SECURE_MODE_ADDR) #define HWIO_SPDM_DYN_SECURE_MODE_INM(m) \ in_dword_masked(HWIO_SPDM_DYN_SECURE_MODE_ADDR, m) #define HWIO_SPDM_DYN_SECURE_MODE_OUT(v) \ out_dword(HWIO_SPDM_DYN_SECURE_MODE_ADDR,v) #define HWIO_SPDM_DYN_SECURE_MODE_OUTM(m,v) \ out_dword_masked_ns(HWIO_SPDM_DYN_SECURE_MODE_ADDR,m,v,HWIO_SPDM_DYN_SECURE_MODE_IN) #define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_BMSK 0x1 #define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_SHFT 0x0 #define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_DISABLE_FVAL 0x0 #define HWIO_SPDM_DYN_SECURE_MODE_SECURE_MODE_ENABLE_FVAL 0x1 #define HWIO_CHIP_ID_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006144) #define HWIO_CHIP_ID_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006144) #define HWIO_CHIP_ID_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006144) #define HWIO_CHIP_ID_RMSK 0xffff #define HWIO_CHIP_ID_IN \ in_dword(HWIO_CHIP_ID_ADDR) #define HWIO_CHIP_ID_INM(m) \ in_dword_masked(HWIO_CHIP_ID_ADDR, m) #define HWIO_CHIP_ID_CHIP_ID_BMSK 0xffff #define HWIO_CHIP_ID_CHIP_ID_SHFT 0x0 #define HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x00006150 + 0x4 * (n)) #define HWIO_OEM_IMAGE_ENCR_KEYn_PHYS(n) (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006150 + 0x4 * (n)) #define HWIO_OEM_IMAGE_ENCR_KEYn_OFFS(n) (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006150 + 0x4 * (n)) #define HWIO_OEM_IMAGE_ENCR_KEYn_RMSK 0xffffffff #define HWIO_OEM_IMAGE_ENCR_KEYn_MAXn 3 #define HWIO_OEM_IMAGE_ENCR_KEYn_INI(n) \ in_dword_masked(HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n), HWIO_OEM_IMAGE_ENCR_KEYn_RMSK) #define HWIO_OEM_IMAGE_ENCR_KEYn_INMI(n,mask) \ in_dword_masked(HWIO_OEM_IMAGE_ENCR_KEYn_ADDR(n), mask) #define HWIO_OEM_IMAGE_ENCR_KEYn_KEY_DATA0_BMSK 0xffffffff #define HWIO_OEM_IMAGE_ENCR_KEYn_KEY_DATA0_SHFT 0x0 #define HWIO_IMAGE_ENCR_KEY1_0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006160) #define HWIO_IMAGE_ENCR_KEY1_0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006160) #define HWIO_IMAGE_ENCR_KEY1_0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006160) #define HWIO_IMAGE_ENCR_KEY1_0_RMSK 0xffffffff #define HWIO_IMAGE_ENCR_KEY1_0_IN \ in_dword(HWIO_IMAGE_ENCR_KEY1_0_ADDR) #define HWIO_IMAGE_ENCR_KEY1_0_INM(m) \ in_dword_masked(HWIO_IMAGE_ENCR_KEY1_0_ADDR, m) #define HWIO_IMAGE_ENCR_KEY1_0_KEY_DATA0_BMSK 0xffffffff #define HWIO_IMAGE_ENCR_KEY1_0_KEY_DATA0_SHFT 0x0 #define HWIO_IMAGE_ENCR_KEY1_1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006164) #define HWIO_IMAGE_ENCR_KEY1_1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006164) #define HWIO_IMAGE_ENCR_KEY1_1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006164) #define HWIO_IMAGE_ENCR_KEY1_1_RMSK 0xffffffff #define HWIO_IMAGE_ENCR_KEY1_1_IN \ in_dword(HWIO_IMAGE_ENCR_KEY1_1_ADDR) #define HWIO_IMAGE_ENCR_KEY1_1_INM(m) \ in_dword_masked(HWIO_IMAGE_ENCR_KEY1_1_ADDR, m) #define HWIO_IMAGE_ENCR_KEY1_1_KEY_DATA0_BMSK 0xffffffff #define HWIO_IMAGE_ENCR_KEY1_1_KEY_DATA0_SHFT 0x0 #define HWIO_IMAGE_ENCR_KEY1_2_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006168) #define HWIO_IMAGE_ENCR_KEY1_2_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006168) #define HWIO_IMAGE_ENCR_KEY1_2_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006168) #define HWIO_IMAGE_ENCR_KEY1_2_RMSK 0xffffffff #define HWIO_IMAGE_ENCR_KEY1_2_IN \ in_dword(HWIO_IMAGE_ENCR_KEY1_2_ADDR) #define HWIO_IMAGE_ENCR_KEY1_2_INM(m) \ in_dword_masked(HWIO_IMAGE_ENCR_KEY1_2_ADDR, m) #define HWIO_IMAGE_ENCR_KEY1_2_KEY_DATA0_BMSK 0xffffffff #define HWIO_IMAGE_ENCR_KEY1_2_KEY_DATA0_SHFT 0x0 #define HWIO_IMAGE_ENCR_KEY1_3_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000616c) #define HWIO_IMAGE_ENCR_KEY1_3_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000616c) #define HWIO_IMAGE_ENCR_KEY1_3_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000616c) #define HWIO_IMAGE_ENCR_KEY1_3_RMSK 0xffffffff #define HWIO_IMAGE_ENCR_KEY1_3_IN \ in_dword(HWIO_IMAGE_ENCR_KEY1_3_ADDR) #define HWIO_IMAGE_ENCR_KEY1_3_INM(m) \ in_dword_masked(HWIO_IMAGE_ENCR_KEY1_3_ADDR, m) #define HWIO_IMAGE_ENCR_KEY1_3_KEY_DATA0_BMSK 0xffffffff #define HWIO_IMAGE_ENCR_KEY1_3_KEY_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006190) #define HWIO_PK_HASH0_0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006190) #define HWIO_PK_HASH0_0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006190) #define HWIO_PK_HASH0_0_RMSK 0xffffffff #define HWIO_PK_HASH0_0_IN \ in_dword(HWIO_PK_HASH0_0_ADDR) #define HWIO_PK_HASH0_0_INM(m) \ in_dword_masked(HWIO_PK_HASH0_0_ADDR, m) #define HWIO_PK_HASH0_0_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_0_HASH_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006194) #define HWIO_PK_HASH0_1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006194) #define HWIO_PK_HASH0_1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006194) #define HWIO_PK_HASH0_1_RMSK 0xffffffff #define HWIO_PK_HASH0_1_IN \ in_dword(HWIO_PK_HASH0_1_ADDR) #define HWIO_PK_HASH0_1_INM(m) \ in_dword_masked(HWIO_PK_HASH0_1_ADDR, m) #define HWIO_PK_HASH0_1_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_1_HASH_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_2_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006198) #define HWIO_PK_HASH0_2_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006198) #define HWIO_PK_HASH0_2_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006198) #define HWIO_PK_HASH0_2_RMSK 0xffffffff #define HWIO_PK_HASH0_2_IN \ in_dword(HWIO_PK_HASH0_2_ADDR) #define HWIO_PK_HASH0_2_INM(m) \ in_dword_masked(HWIO_PK_HASH0_2_ADDR, m) #define HWIO_PK_HASH0_2_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_2_HASH_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_3_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000619c) #define HWIO_PK_HASH0_3_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000619c) #define HWIO_PK_HASH0_3_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000619c) #define HWIO_PK_HASH0_3_RMSK 0xffffffff #define HWIO_PK_HASH0_3_IN \ in_dword(HWIO_PK_HASH0_3_ADDR) #define HWIO_PK_HASH0_3_INM(m) \ in_dword_masked(HWIO_PK_HASH0_3_ADDR, m) #define HWIO_PK_HASH0_3_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_3_HASH_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_4_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000061a0) #define HWIO_PK_HASH0_4_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061a0) #define HWIO_PK_HASH0_4_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061a0) #define HWIO_PK_HASH0_4_RMSK 0xffffffff #define HWIO_PK_HASH0_4_IN \ in_dword(HWIO_PK_HASH0_4_ADDR) #define HWIO_PK_HASH0_4_INM(m) \ in_dword_masked(HWIO_PK_HASH0_4_ADDR, m) #define HWIO_PK_HASH0_4_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_4_HASH_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_5_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000061a4) #define HWIO_PK_HASH0_5_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061a4) #define HWIO_PK_HASH0_5_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061a4) #define HWIO_PK_HASH0_5_RMSK 0xffffffff #define HWIO_PK_HASH0_5_IN \ in_dword(HWIO_PK_HASH0_5_ADDR) #define HWIO_PK_HASH0_5_INM(m) \ in_dword_masked(HWIO_PK_HASH0_5_ADDR, m) #define HWIO_PK_HASH0_5_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_5_HASH_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_6_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000061a8) #define HWIO_PK_HASH0_6_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061a8) #define HWIO_PK_HASH0_6_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061a8) #define HWIO_PK_HASH0_6_RMSK 0xffffffff #define HWIO_PK_HASH0_6_IN \ in_dword(HWIO_PK_HASH0_6_ADDR) #define HWIO_PK_HASH0_6_INM(m) \ in_dword_masked(HWIO_PK_HASH0_6_ADDR, m) #define HWIO_PK_HASH0_6_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_6_HASH_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_7_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000061ac) #define HWIO_PK_HASH0_7_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061ac) #define HWIO_PK_HASH0_7_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061ac) #define HWIO_PK_HASH0_7_RMSK 0xffffffff #define HWIO_PK_HASH0_7_IN \ in_dword(HWIO_PK_HASH0_7_ADDR) #define HWIO_PK_HASH0_7_INM(m) \ in_dword_masked(HWIO_PK_HASH0_7_ADDR, m) #define HWIO_PK_HASH0_7_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_7_HASH_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_8_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000061b0) #define HWIO_PK_HASH0_8_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061b0) #define HWIO_PK_HASH0_8_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061b0) #define HWIO_PK_HASH0_8_RMSK 0xffffffff #define HWIO_PK_HASH0_8_IN \ in_dword(HWIO_PK_HASH0_8_ADDR) #define HWIO_PK_HASH0_8_INM(m) \ in_dword_masked(HWIO_PK_HASH0_8_ADDR, m) #define HWIO_PK_HASH0_8_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_8_HASH_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_9_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000061b4) #define HWIO_PK_HASH0_9_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061b4) #define HWIO_PK_HASH0_9_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061b4) #define HWIO_PK_HASH0_9_RMSK 0xffffffff #define HWIO_PK_HASH0_9_IN \ in_dword(HWIO_PK_HASH0_9_ADDR) #define HWIO_PK_HASH0_9_INM(m) \ in_dword_masked(HWIO_PK_HASH0_9_ADDR, m) #define HWIO_PK_HASH0_9_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_9_HASH_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_10_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000061b8) #define HWIO_PK_HASH0_10_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061b8) #define HWIO_PK_HASH0_10_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061b8) #define HWIO_PK_HASH0_10_RMSK 0xffffffff #define HWIO_PK_HASH0_10_IN \ in_dword(HWIO_PK_HASH0_10_ADDR) #define HWIO_PK_HASH0_10_INM(m) \ in_dword_masked(HWIO_PK_HASH0_10_ADDR, m) #define HWIO_PK_HASH0_10_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_10_HASH_DATA0_SHFT 0x0 #define HWIO_PK_HASH0_11_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000061bc) #define HWIO_PK_HASH0_11_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061bc) #define HWIO_PK_HASH0_11_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061bc) #define HWIO_PK_HASH0_11_RMSK 0xffffffff #define HWIO_PK_HASH0_11_IN \ in_dword(HWIO_PK_HASH0_11_ADDR) #define HWIO_PK_HASH0_11_INM(m) \ in_dword_masked(HWIO_PK_HASH0_11_ADDR, m) #define HWIO_PK_HASH0_11_HASH_DATA0_BMSK 0xffffffff #define HWIO_PK_HASH0_11_HASH_DATA0_SHFT 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000061f0) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061f0) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061f0) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_RMSK 0xffffffff #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_IN \ in_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_INM(m) \ in_dword_masked(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR, m) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_OUT(v) \ out_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR,v) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_ADDR,m,v,HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_IN) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION31_STICKY_BIT_BMSK 0x80000000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION31_STICKY_BIT_SHFT 0x1f #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION31_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION31_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_BMSK 0x40000000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_SHFT 0x1e #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION30_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_BMSK 0x20000000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_SHFT 0x1d #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION29_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_BMSK 0x10000000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_SHFT 0x1c #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION28_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_BMSK 0x8000000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_SHFT 0x1b #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION27_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_BMSK 0x4000000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_SHFT 0x1a #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION26_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_BMSK 0x2000000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_SHFT 0x19 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION25_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_BMSK 0x1000000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_SHFT 0x18 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION24_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_BMSK 0x800000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_SHFT 0x17 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION23_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_BMSK 0x400000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_SHFT 0x16 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION22_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_BMSK 0x200000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_SHFT 0x15 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION21_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_BMSK 0x100000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_SHFT 0x14 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION20_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_BMSK 0x80000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_SHFT 0x13 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION19_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_BMSK 0x40000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_SHFT 0x12 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION18_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_BMSK 0x20000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_SHFT 0x11 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION17_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_BMSK 0x10000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_SHFT 0x10 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION16_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_BMSK 0x8000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_SHFT 0xf #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION15_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_BMSK 0x4000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_SHFT 0xe #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION14_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_BMSK 0x2000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_SHFT 0xd #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION13_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_BMSK 0x1000 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_SHFT 0xc #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION12_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_BMSK 0x800 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_SHFT 0xb #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION11_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_BMSK 0x400 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_SHFT 0xa #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION10_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_BMSK 0x200 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_SHFT 0x9 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION9_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_BMSK 0x100 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_SHFT 0x8 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION8_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_BMSK 0x80 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_SHFT 0x7 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION7_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_BMSK 0x40 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_SHFT 0x6 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION6_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_BMSK 0x20 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_SHFT 0x5 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION5_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_BMSK 0x10 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_SHFT 0x4 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION4_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_BMSK 0x8 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_SHFT 0x3 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION3_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_BMSK 0x4 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_SHFT 0x2 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION2_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_BMSK 0x2 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_SHFT 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION1_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_BMSK 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_SHFT 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_ALLOW_WRITE_FVAL 0x0 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT0_REGION0_STICKY_BIT_DISABLE_WRITE_FVAL 0x1 #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000061f4) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x000061f4) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x000061f4) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RMSK 0xffffffff #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_IN \ in_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_INM(m) \ in_dword_masked(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR, m) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_OUT(v) \ out_dword(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR,v) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_OUTM(m,v) \ out_dword_masked_ns(HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_ADDR,m,v,HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_IN) #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RSVD0_BMSK 0xffffffff #define HWIO_QFPROM_WRITE_DISABLE_STICKY_BIT1_RSVD0_SHFT 0x0 #define HWIO_ANTI_ROLLBACK_1_0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006200) #define HWIO_ANTI_ROLLBACK_1_0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006200) #define HWIO_ANTI_ROLLBACK_1_0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006200) #define HWIO_ANTI_ROLLBACK_1_0_RMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_1_0_IN \ in_dword(HWIO_ANTI_ROLLBACK_1_0_ADDR) #define HWIO_ANTI_ROLLBACK_1_0_INM(m) \ in_dword_masked(HWIO_ANTI_ROLLBACK_1_0_ADDR, m) #define HWIO_ANTI_ROLLBACK_1_0_XBL0_BMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_1_0_XBL0_SHFT 0x0 #define HWIO_ANTI_ROLLBACK_1_1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006204) #define HWIO_ANTI_ROLLBACK_1_1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006204) #define HWIO_ANTI_ROLLBACK_1_1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006204) #define HWIO_ANTI_ROLLBACK_1_1_RMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_1_1_IN \ in_dword(HWIO_ANTI_ROLLBACK_1_1_ADDR) #define HWIO_ANTI_ROLLBACK_1_1_INM(m) \ in_dword_masked(HWIO_ANTI_ROLLBACK_1_1_ADDR, m) #define HWIO_ANTI_ROLLBACK_1_1_XBL1_BMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_1_1_XBL1_SHFT 0x0 #define HWIO_ANTI_ROLLBACK_2_0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006208) #define HWIO_ANTI_ROLLBACK_2_0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006208) #define HWIO_ANTI_ROLLBACK_2_0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006208) #define HWIO_ANTI_ROLLBACK_2_0_RMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_2_0_IN \ in_dword(HWIO_ANTI_ROLLBACK_2_0_ADDR) #define HWIO_ANTI_ROLLBACK_2_0_INM(m) \ in_dword_masked(HWIO_ANTI_ROLLBACK_2_0_ADDR, m) #define HWIO_ANTI_ROLLBACK_2_0_PIL_SUBSYSTEM_31_0_BMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_2_0_PIL_SUBSYSTEM_31_0_SHFT 0x0 #define HWIO_ANTI_ROLLBACK_2_1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000620c) #define HWIO_ANTI_ROLLBACK_2_1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000620c) #define HWIO_ANTI_ROLLBACK_2_1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000620c) #define HWIO_ANTI_ROLLBACK_2_1_RMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_2_1_IN \ in_dword(HWIO_ANTI_ROLLBACK_2_1_ADDR) #define HWIO_ANTI_ROLLBACK_2_1_INM(m) \ in_dword_masked(HWIO_ANTI_ROLLBACK_2_1_ADDR, m) #define HWIO_ANTI_ROLLBACK_2_1_XBL_SEC_BMSK 0xfe000000 #define HWIO_ANTI_ROLLBACK_2_1_XBL_SEC_SHFT 0x19 #define HWIO_ANTI_ROLLBACK_2_1_SPARE_66_56_BMSK 0x1000000 #define HWIO_ANTI_ROLLBACK_2_1_SPARE_66_56_SHFT 0x18 #define HWIO_ANTI_ROLLBACK_2_1_RPM_BMSK 0xfe0000 #define HWIO_ANTI_ROLLBACK_2_1_RPM_SHFT 0x11 #define HWIO_ANTI_ROLLBACK_2_1_TZ_BMSK 0x1ffff #define HWIO_ANTI_ROLLBACK_2_1_TZ_SHFT 0x0 #define HWIO_ANTI_ROLLBACK_3_0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006210) #define HWIO_ANTI_ROLLBACK_3_0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006210) #define HWIO_ANTI_ROLLBACK_3_0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006210) #define HWIO_ANTI_ROLLBACK_3_0_RMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_3_0_IN \ in_dword(HWIO_ANTI_ROLLBACK_3_0_ADDR) #define HWIO_ANTI_ROLLBACK_3_0_INM(m) \ in_dword_masked(HWIO_ANTI_ROLLBACK_3_0_ADDR, m) #define HWIO_ANTI_ROLLBACK_3_0_RSVD1_BMSK 0xc0000000 #define HWIO_ANTI_ROLLBACK_3_0_RSVD1_SHFT 0x1e #define HWIO_ANTI_ROLLBACK_3_0_TQS_HASH_ACTIVE_BMSK 0x3e000000 #define HWIO_ANTI_ROLLBACK_3_0_TQS_HASH_ACTIVE_SHFT 0x19 #define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_BMSK 0x1000000 #define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_SHFT 0x18 #define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_RPMB_KEY_NOT_PROVISIONED_FVAL 0x0 #define HWIO_ANTI_ROLLBACK_3_0_RPMB_KEY_PROVISIONED_RPMB_KEY_PROVISIONED_FVAL 0x1 #define HWIO_ANTI_ROLLBACK_3_0_PIL_SUBSYSTEM_47_32_BMSK 0xffff00 #define HWIO_ANTI_ROLLBACK_3_0_PIL_SUBSYSTEM_47_32_SHFT 0x8 #define HWIO_ANTI_ROLLBACK_3_0_SAFESWITCH_BMSK 0xff #define HWIO_ANTI_ROLLBACK_3_0_SAFESWITCH_SHFT 0x0 #define HWIO_ANTI_ROLLBACK_3_1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006214) #define HWIO_ANTI_ROLLBACK_3_1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006214) #define HWIO_ANTI_ROLLBACK_3_1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006214) #define HWIO_ANTI_ROLLBACK_3_1_RMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_3_1_IN \ in_dword(HWIO_ANTI_ROLLBACK_3_1_ADDR) #define HWIO_ANTI_ROLLBACK_3_1_INM(m) \ in_dword_masked(HWIO_ANTI_ROLLBACK_3_1_ADDR, m) #define HWIO_ANTI_ROLLBACK_3_1_RSVD1_BMSK 0xf0000000 #define HWIO_ANTI_ROLLBACK_3_1_RSVD1_SHFT 0x1c #define HWIO_ANTI_ROLLBACK_3_1_DEVICE_CFG_BMSK 0xffe0000 #define HWIO_ANTI_ROLLBACK_3_1_DEVICE_CFG_SHFT 0x11 #define HWIO_ANTI_ROLLBACK_3_1_DEBUG_POLICY_BMSK 0x1f000 #define HWIO_ANTI_ROLLBACK_3_1_DEBUG_POLICY_SHFT 0xc #define HWIO_ANTI_ROLLBACK_3_1_HYPERVISOR_BMSK 0xfff #define HWIO_ANTI_ROLLBACK_3_1_HYPERVISOR_SHFT 0x0 #define HWIO_ANTI_ROLLBACK_4_0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006218) #define HWIO_ANTI_ROLLBACK_4_0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006218) #define HWIO_ANTI_ROLLBACK_4_0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006218) #define HWIO_ANTI_ROLLBACK_4_0_RMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_4_0_IN \ in_dword(HWIO_ANTI_ROLLBACK_4_0_ADDR) #define HWIO_ANTI_ROLLBACK_4_0_INM(m) \ in_dword_masked(HWIO_ANTI_ROLLBACK_4_0_ADDR, m) #define HWIO_ANTI_ROLLBACK_4_0_MSS_BMSK 0xffff0000 #define HWIO_ANTI_ROLLBACK_4_0_MSS_SHFT 0x10 #define HWIO_ANTI_ROLLBACK_4_0_MISC_BMSK 0xffff #define HWIO_ANTI_ROLLBACK_4_0_MISC_SHFT 0x0 #define HWIO_ANTI_ROLLBACK_4_1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000621c) #define HWIO_ANTI_ROLLBACK_4_1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000621c) #define HWIO_ANTI_ROLLBACK_4_1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000621c) #define HWIO_ANTI_ROLLBACK_4_1_RMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_4_1_IN \ in_dword(HWIO_ANTI_ROLLBACK_4_1_ADDR) #define HWIO_ANTI_ROLLBACK_4_1_INM(m) \ in_dword_masked(HWIO_ANTI_ROLLBACK_4_1_ADDR, m) #define HWIO_ANTI_ROLLBACK_4_1_SIMLOCK_BMSK 0x80000000 #define HWIO_ANTI_ROLLBACK_4_1_SIMLOCK_SHFT 0x1f #define HWIO_ANTI_ROLLBACK_4_1_RSVD0_BMSK 0x7ffffff0 #define HWIO_ANTI_ROLLBACK_4_1_RSVD0_SHFT 0x4 #define HWIO_ANTI_ROLLBACK_4_1_ROOT_CERT_PK_HASH_INDEX_BMSK 0xf #define HWIO_ANTI_ROLLBACK_4_1_ROOT_CERT_PK_HASH_INDEX_SHFT 0x0 #define HWIO_ANTI_ROLLBACK_5_0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006220) #define HWIO_ANTI_ROLLBACK_5_0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006220) #define HWIO_ANTI_ROLLBACK_5_0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006220) #define HWIO_ANTI_ROLLBACK_5_0_RMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_5_0_IN \ in_dword(HWIO_ANTI_ROLLBACK_5_0_ADDR) #define HWIO_ANTI_ROLLBACK_5_0_INM(m) \ in_dword_masked(HWIO_ANTI_ROLLBACK_5_0_ADDR, m) #define HWIO_ANTI_ROLLBACK_5_0_ANTI_ROLLBACK_5_31_13_BMSK 0xffffe000 #define HWIO_ANTI_ROLLBACK_5_0_ANTI_ROLLBACK_5_31_13_SHFT 0xd #define HWIO_ANTI_ROLLBACK_5_0_SHRM_BMSK 0x1f00 #define HWIO_ANTI_ROLLBACK_5_0_SHRM_SHFT 0x8 #define HWIO_ANTI_ROLLBACK_5_0_CPUCP_FW_BMSK 0xff #define HWIO_ANTI_ROLLBACK_5_0_CPUCP_FW_SHFT 0x0 #define HWIO_ANTI_ROLLBACK_5_1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006224) #define HWIO_ANTI_ROLLBACK_5_1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006224) #define HWIO_ANTI_ROLLBACK_5_1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006224) #define HWIO_ANTI_ROLLBACK_5_1_RMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_5_1_IN \ in_dword(HWIO_ANTI_ROLLBACK_5_1_ADDR) #define HWIO_ANTI_ROLLBACK_5_1_INM(m) \ in_dword_masked(HWIO_ANTI_ROLLBACK_5_1_ADDR, m) #define HWIO_ANTI_ROLLBACK_5_1_MISC_BMSK 0xffffffff #define HWIO_ANTI_ROLLBACK_5_1_MISC_SHFT 0x0 #define HWIO_MRC_2_0_0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006250) #define HWIO_MRC_2_0_0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006250) #define HWIO_MRC_2_0_0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006250) #define HWIO_MRC_2_0_0_RMSK 0xffffffff #define HWIO_MRC_2_0_0_IN \ in_dword(HWIO_MRC_2_0_0_ADDR) #define HWIO_MRC_2_0_0_INM(m) \ in_dword_masked(HWIO_MRC_2_0_0_ADDR, m) #define HWIO_MRC_2_0_0_RSVD0_BMSK 0xfffffff0 #define HWIO_MRC_2_0_0_RSVD0_SHFT 0x4 #define HWIO_MRC_2_0_0_ROOT_CERT_ACTIVATION_LIST_BMSK 0xf #define HWIO_MRC_2_0_0_ROOT_CERT_ACTIVATION_LIST_SHFT 0x0 #define HWIO_MRC_2_0_1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006254) #define HWIO_MRC_2_0_1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006254) #define HWIO_MRC_2_0_1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006254) #define HWIO_MRC_2_0_1_RMSK 0xffffffff #define HWIO_MRC_2_0_1_IN \ in_dword(HWIO_MRC_2_0_1_ADDR) #define HWIO_MRC_2_0_1_INM(m) \ in_dword_masked(HWIO_MRC_2_0_1_ADDR, m) #define HWIO_MRC_2_0_1_RSVD1_BMSK 0xfffffffe #define HWIO_MRC_2_0_1_RSVD1_SHFT 0x1 #define HWIO_MRC_2_0_1_CURRENT_UIE_KEY_SEL_BMSK 0x1 #define HWIO_MRC_2_0_1_CURRENT_UIE_KEY_SEL_SHFT 0x0 #define HWIO_MRC_2_0_2_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006258) #define HWIO_MRC_2_0_2_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006258) #define HWIO_MRC_2_0_2_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006258) #define HWIO_MRC_2_0_2_RMSK 0xffffffff #define HWIO_MRC_2_0_2_IN \ in_dword(HWIO_MRC_2_0_2_ADDR) #define HWIO_MRC_2_0_2_INM(m) \ in_dword_masked(HWIO_MRC_2_0_2_ADDR, m) #define HWIO_MRC_2_0_2_RSVD0_BMSK 0xfffffff0 #define HWIO_MRC_2_0_2_RSVD0_SHFT 0x4 #define HWIO_MRC_2_0_2_ROOT_CERT_REVOCATION_LIST_BMSK 0xf #define HWIO_MRC_2_0_2_ROOT_CERT_REVOCATION_LIST_SHFT 0x0 #define HWIO_MRC_2_0_3_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x0000625c) #define HWIO_MRC_2_0_3_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x0000625c) #define HWIO_MRC_2_0_3_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x0000625c) #define HWIO_MRC_2_0_3_RMSK 0xffffffff #define HWIO_MRC_2_0_3_IN \ in_dword(HWIO_MRC_2_0_3_ADDR) #define HWIO_MRC_2_0_3_INM(m) \ in_dword_masked(HWIO_MRC_2_0_3_ADDR, m) #define HWIO_MRC_2_0_3_RSVD0_BMSK 0xffffffff #define HWIO_MRC_2_0_3_RSVD0_SHFT 0x0 #define HWIO_CRYPTO_LIB_VERSION_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006300) #define HWIO_CRYPTO_LIB_VERSION_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006300) #define HWIO_CRYPTO_LIB_VERSION_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006300) #define HWIO_CRYPTO_LIB_VERSION_RMSK 0xffffffff #define HWIO_CRYPTO_LIB_VERSION_IN \ in_dword(HWIO_CRYPTO_LIB_VERSION_ADDR) #define HWIO_CRYPTO_LIB_VERSION_INM(m) \ in_dword_masked(HWIO_CRYPTO_LIB_VERSION_ADDR, m) #define HWIO_CRYPTO_LIB_VERSION_VERSION_BMSK 0xffffffff #define HWIO_CRYPTO_LIB_VERSION_VERSION_SHFT 0x0 #define HWIO_LCM_0_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006304) #define HWIO_LCM_0_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006304) #define HWIO_LCM_0_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006304) #define HWIO_LCM_0_RMSK 0xffffffff #define HWIO_LCM_0_IN \ in_dword(HWIO_LCM_0_ADDR) #define HWIO_LCM_0_INM(m) \ in_dword_masked(HWIO_LCM_0_ADDR, m) #define HWIO_LCM_0_DISABLE_LCM_BMSK 0x80000000 #define HWIO_LCM_0_DISABLE_LCM_SHFT 0x1f #define HWIO_LCM_0_DISABLE_LCM_STATE_TRANSITION_BMSK 0x40000000 #define HWIO_LCM_0_DISABLE_LCM_STATE_TRANSITION_SHFT 0x1e #define HWIO_LCM_0_DISABLE_SECURE_PHK_BMSK 0x20000000 #define HWIO_LCM_0_DISABLE_SECURE_PHK_SHFT 0x1d #define HWIO_LCM_0_RSVD_BMSK 0x1fffff00 #define HWIO_LCM_0_RSVD_SHFT 0x8 #define HWIO_LCM_0_DEBUG_STATE_BMSK 0x80 #define HWIO_LCM_0_DEBUG_STATE_SHFT 0x7 #define HWIO_LCM_0_ILLEGAL_STATE_BMSK 0x40 #define HWIO_LCM_0_ILLEGAL_STATE_SHFT 0x6 #define HWIO_LCM_0_QC_EXTERNAL_BMSK 0x20 #define HWIO_LCM_0_QC_EXTERNAL_SHFT 0x5 #define HWIO_LCM_0_QC_INTERNAL_BMSK 0x10 #define HWIO_LCM_0_QC_INTERNAL_SHFT 0x4 #define HWIO_LCM_0_QC_FEAT_CONFIG_BMSK 0x8 #define HWIO_LCM_0_QC_FEAT_CONFIG_SHFT 0x3 #define HWIO_LCM_0_HW_TEST_BMSK 0x4 #define HWIO_LCM_0_HW_TEST_SHFT 0x2 #define HWIO_LCM_0_SOC_PERSO_BMSK 0x2 #define HWIO_LCM_0_SOC_PERSO_SHFT 0x1 #define HWIO_LCM_0_BLANK_BMSK 0x1 #define HWIO_LCM_0_BLANK_SHFT 0x0 #define HWIO_LCM_1_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006308) #define HWIO_LCM_1_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006308) #define HWIO_LCM_1_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006308) #define HWIO_LCM_1_RMSK 0xffffffff #define HWIO_LCM_1_IN \ in_dword(HWIO_LCM_1_ADDR) #define HWIO_LCM_1_INM(m) \ in_dword_masked(HWIO_LCM_1_ADDR, m) #define HWIO_LCM_1_LCM_DATA1_BMSK 0xffffffff #define HWIO_LCM_1_LCM_DATA1_SHFT 0x0 #define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00006400) #define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_PHYS (SECURITY_CONTROL_CORE_REG_BASE_PHYS + 0x00006400) #define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_OFFS (SECURITY_CONTROL_CORE_REG_BASE_OFFS + 0x00006400) #define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_RMSK 0xffffffff #define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_IN \ in_dword(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR) #define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_INM(m) \ in_dword_masked(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR, m) #define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_OUT(v) \ out_dword(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR,v) #define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_OUTM(m,v) \ out_dword_masked_ns(HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDR,m,v,HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_IN) #define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDRESS_BMSK 0xffffffff #define HWIO_VIRTUAL_SEC_CTRL_BASE_ADDR_ADDRESS_SHFT 0x0 #endif /* __CPR_FUSES_HWIO_H__ */