/*
 *
 * Copyright (C) 2012-2019, Samsung Electronics Co., Ltd.
 *
 * Board base registers and structures
 */

#ifndef __BOARD_H__
#define __BOARD_H__

#include "base.h"

#define USE_TOUCH_INTERRUPT

/* Display constants */
#define BOARD_GRAYSCALE_DEPTH              8
#define BOARD_REDBITDEPTH                  8
#define BOARD_GREENBITDEPTH                8
#define BOARD_BLUEBITDEPTH                 8
#define BOARD_ALPHABITDEPTH                8
#define BOARD_BITSPERPIXEL                 32 /* RGBA */

#define BOARD_WDENSITY                     368
#define BOARD_HDENSITY                     368

#define FB_ALIGN                           SIZE_4KB

/* Define for specific values which are dependent by model */
#define SENSOR_MAX_X_DEFAULT               4096
#define SENSOR_MAX_Y_DEFAULT               4096

/* =============================================== */
/* Board memory map */
/* Display controller(DECON) */
#define DISP_DECON_MAIN_BASE    0x19F00000 /* Display controller(DECON) */
#define DISP_DECON_WIN_BASE     0x19F10000 /* Display controller(DECON) */
#define DISP_DECON_WINCON_BASE  0x19F30000 /* Display controller(DECON) */
#define DISP_DPP_SEC_BASE       0x19CD0000 /* Display controller(DECON) */
#define DISP_IDMA_SEC_BASE      0x19CB0000 /* Display controller(DECON) */
#define DISP_MIPI_BASE          0x16080000 /* Display controller(DECON) */
#define DISP_IDMA_COMMON_BASE   0x19CB0000 /* Display controller(DECON) */

#define SMMUDECON0_BASE         0x19D00000 /* Display system MMU */
#define SMMUDECON1_BASE         0x19D10000 /* Display system MMU */

/* I2C driver name for touch interface */
#define TOUCH_I2C_DRVNAME                  "/dev/hsi2c/hsi2c0"

/* Touch IC Address */
#define SEC_I2C_ADDR                       0x48
#define TOUCH_IC_SLAVE_ADDR                SEC_I2C_ADDR

/* Interrupt IDs */
#define NUM_SGI                            16
#define NUM_PPI                            16
#define SPI_IRQ(x)                         (NUM_SGI + NUM_PPI + x)

/* EXT_INTA1_OUT0, SPI[57] */
#define TOUCH_INT_NUM                      SPI_IRQ(57)

/* GPIO registers and bits */
#define GPIO_PA_BASE                       0x14EC0000

/* GPA1[0] , XEINT_8/WAKE_EXT_INTA1[0] */
#define GPA1_CON_OFFSET                    0x0020
#define GPA1_0_CONF_MASK                   (0xFu << 0)
#define GPA1_0_CONF_EINT                   (0xFu << 0)

#define WEINT_GPA1_CON_OFFSET              0x0704
#define GPA1_EINT0_MASK                    (0x7u << 0)
#define GPA1_EINT0_LOW                     (0x0u << 0)
#define GPA1_EINT0_HIGH                    (0x1u << 0)
#define GPA1_EINT0_FALL                    (0x2u << 0)
#define GPA1_EINT0_RISE                    (0x3u << 0)

#define WEINT_GPA1_MASK_OFFSET             0x0904

#define WEINT_GPA1_PEND_OFFSET             0x0A04
#define WEINT_MASK_BIT(x)                  (0x1 << (x))
#define WEINT_GPA1_0                       0
#define WEINT_GPA1_0_PEND                  WEINT_MASK_BIT(WEINT_GPA1_0)

#endif /* __BOARD_H__ */