/* * * dpu30/cal_1000/regs-decon.h * * Copyright (c) 2019 Samsung Electronics Co., Ltd. * http://www.samsung.com * * Jaehoe Yang * Jiun Yu * * Register definition file for Samsung DECON driver * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef _REGS_DISP_SS_H #define _REGS_DISP_SS_H #define DISP_DPU_MIPI_PHY_CON 0x0008 /* _v : [0,1] */ #define SEL_RESET_DPHY_MASK(_v) (0x1 << (4 + (_v))) #define M_RESETN_M4S4_MODULE_MASK (0x1 << 1) #define M_RESETN_M4S4_TOP_MASK (0x1 << 0) #define DISP_DPU_TE_QACTIVE_PLL_EN 0x0010 #define TE_QACTIVE_PLL_EN (0x1 << 0) #endif /* _REGS_DISP_SS_H */ #ifndef _REGS_DECON_H #define _REGS_DECON_H /* * [ DISP BASE ADDRESS ] * * - CMU_DISP 0x1C20_0000 * - D_TZPC_DISP 0x1C21_0000 * - SYSREG_DISP 0x1C22_0000 : DPU_MIPI_PHY_CON (0x1008) * - GPC_DISP 0x1C23_0000 * - MIPI_DSIM0 0x1C2C_0000 * - MIPI_DSIM1 0x1C2D_0000 * - MIPI_DCPHY 0x1C2E_0000 * - DECON_MAIN 0x1C30_0000 * - DECON_WIN 0x1C31_0000 * - DECON_SUB 0x1C32_0000 * - DECON0_WINCON 0x1C33_0000 * - DECON1_WINCON 0x1C34_0000 * - DECON2_WINCON 0x1C35_0000 * - DQE0 0x1C36_0000 * * [ DPU BASE ADDRESS ] * * - CMU_DPU 0x1C00_0000 * - D_TZPC_DPU 0x1C01_0000 * - SYSREG_DPU 0x1C02_0000 : DRCG (0x0104) * - GPC_DPU 0x1C03_0000 * - DPU_DMA 0x1C0B_0000 * - DPU_DMA_VGEN 0x1C0C_0000 * - DPP_COMMON 0x1C0D_0000 * - DPP_HDR_LSI 0x1C0E_0000 * - SYSMMU_DPU0_S1_NS 0x1C10_0000 * - SYSMMU_DPU1_S1_NS 0x1C11_0000 * - SYSMMU_DPU2_S1_NS 0x1C12_0000 * - SYSMMU_DPU0_S1_S 0x1C13_0000 * - SYSMMU_DPU1_S1_S 0x1C14_0000 * - SYSMMU_DPU2_S1_S 0x1C15_0000 * - SYSMMU_DPU0_S2 0x1C16_0000 * - SYSMMU_DPU1_S2 0x1C17_0000 * - SYSMMU_DPU2_S2 0x1C18_0000 * - PPMU_DPUD0 0x1C19_0000 * - PPMU_DPUD1 0x1C1A_0000 * - PPMU_DPUD2 0x1C1B_0000 * - SSMT_DPU0 0x1C1C_0000 * - SSMT_DPU1 0x1C1D_0000 * - SSMT_DPU2 0x1C1E_0000 */ //------------------------------------------------------------------- // DECON_MAIN //------------------------------------------------------------------- #define DECON_OFFSET(_id) (0x0000 + 0x1000 * (_id)) #define DECON0_OFFSET (0x0000) #define DECON1_OFFSET (0x1000) #define DECON2_OFFSET (0x2000) #define SHADOW_OFFSET (0x0800) #define DECON_VERSION (0x0000) #define DECON_VERSION_GET(_v) (((_v) >> 0) & 0xffffffff) #define FRAME_COUNT (0x0004) #define FRAME_COUNT_GET(_v) (((_v) >> 0) & 0xffffffff) #define GLOBAL_CON (0x0020) #define GLOBAL_CON_SRESET (1 << 28) #define GLOBAL_CON_TEN_BPC_MODE_F (1 << 20) #define GLOBAL_CON_TEN_BPC_MODE_MASK (1 << 20) #define GLOBAL_CON_MASTER_MODE_F(_v) ((_v) << 12) #define GLOBAL_CON_MASTER_MODE_MASK (0xF << 12) #define GLOBAL_CON_OPERATION_MODE_F (1 << 8) #define GLOBAL_CON_OPERATION_MODE_VIDEO_F (0 << 8) #define GLOBAL_CON_OPERATION_MODE_CMD_F (1 << 8) #define GLOBAL_CON_IDLE_STATUS (1 << 5) #define GLOBAL_CON_RUN_STATUS (1 << 4) #define GLOBAL_CON_DECON_EN (1 << 1) #define GLOBAL_CON_DECON_EN_F (1 << 0) #define TRIG_CON (0x0030) #define HW_SW_TRIG_HS_STATUS (1 << 28) #define HW_TRIG_SEL(_v) ((_v) << 24) #define HW_TRIG_SEL_MASK (0x3 << 24) #define HW_TRIG_SEL_FROM_DDI2 (2 << 24) #define HW_TRIG_SEL_FROM_DDI1 (1 << 24) #define HW_TRIG_SEL_FROM_DDI0 (0 << 24) #define HW_TRIG_SKIP(_v) ((_v) << 16) #define HW_TRIG_SKIP_MASK (0xff << 16) #define HW_TRIG_ACTIVE_VALUE (1 << 13) #define HW_TRIG_EDGE_POLARITY (1 << 12) #define SW_TRIG_EN (1 << 8) #define HW_TRIG_MASK_SLAVE1 (1 << 6) #define HW_TRIG_MASK_SLAVE0 (1 << 5) #define HW_TRIG_MASK_DECON (1 << 4) #define HW_SW_TRIG_TIMER_CLEAR (1 << 3) #define HW_SW_TRIG_TIMER_EN (1 << 2) #define SW_TRIG_DET_EN (1 << 1) //new #define HW_TRIG_EN (1 << 0) #define TRIG_TIMER (0x0034) #define HW_TE_CNT (0x0038) #define HW_TRIG_CNT_B_GET(_v) (((_v) >> 16) & 0xffff) #define HW_TRIG_CNT_A_GET(_v) (((_v) >> 0) & 0xffff) #define DBG_INFO_OF_CNT0(_id) (0x0560 + (_id * 0x8)) #define DBG_INFO_OF_CNT1(_id) (0x0564 + (_id * 0x8)) #define DBG_INFO_OF_XCNT(_v) (((_v) >> 16) & 0x3fff) #define DBG_INFO_OF_YCNT(_v) (((_v) >> 0) & 0x3fff) #define TRIG_CON_SECURE (0x003C) #define HW_TRIG_MASK_SECURE_SLAVE1 (1 << 6) #define HW_TRIG_MASK_SECURE_SLAVE0 (1 << 5) #define HW_TRIG_MASK_SECURE (1 << 4) #define OPMODE_OPTION (0x0040) #define VIDEO_FRAME_CON_F(_v) ((_v) << 0) #define VIDEO_FRAME_CON_F_MASK (0x7 << 0) #define PIXELSYNC (0x0044) #define DESYNC_TRIG (1 << 4) #define NULL2C_EN (1 << 1) #define LEVELSTART_EN (1 << 0) #define SHD_REG_UP_REQ (0x0050) #define SHD_REG_UP_REQ_GLOBAL (1U << 31) #define SHD_REG_UP_REQ_DQE_ROI (1 << 29) #define SHD_REG_UP_REQ_DQE (1 << 28) #define SHD_REG_UP_REQ_CMP (1 << 20) #define SHD_REG_UP_REQ_WIN(_win) (1 << (_win)) #define SHD_REG_UP_REQ_FOR_DECON (0xFFFF) #define DECON_INT_EN (0x0060) #define INT_EN_DQE_DIMMING_END (1 << 21) #define INT_EN_DQE_DIMMING_START (1 << 20) #define INT_EN_FRAME_DONE (1 << 13) #define INT_EN_FRAME_START (1 << 12) #define INT_EN_EXTRA (1 << 4) #define INT_EN (1 << 0) #define INT_EN_MASK (0x3011) #define DECON_INT_EN_EXTRA (0x0064) #define INT_EN_UNMASK_START (1 << 24) #define INT_EN_TE_FALL (1 << 20) #define INT_EN_TE_RISE (1 << 16) #define INT_EN_DSIM_LATE_START_ALARM (1 << 12) #define INT_EN_CWB_INST_OFF (1 << 8) #define INT_EN_RESOURCE_CONFLICT (1 << 4) #define INT_EN_TIME_OUT (1 << 0) #define INT_TIMEOUT_VAL (0x0068) #define DECON_INT_PEND (0x0070) #define INT_PEND_DQE_DIMMING_END (1 << 21) #define INT_PEND_DQE_DIMMING_START (1 << 20) #define INT_PEND_FRAME_DONE (1 << 13) #define INT_PEND_FRAME_START (1 << 12) #define INT_PEND_EXTRA (1 << 4) /* defined for common part of driver only */ #define DPU_FRAME_DONE_INT_PEND INT_PEND_FRAME_DONE #define DPU_FRAME_START_INT_PEND INT_PEND_FRAME_START #define DECON_INT_PEND_EXTRA (0x0074) #define INT_PEND_UNMASK_START (1 << 24) #define INT_PEND_TE_FALL (1 << 20) #define INT_PEND_TE_RISE (1 << 16) #define INT_PEND_DSIM_LATE_START_ALARM (1 << 12) #define INT_PEND_CWB_INST_OFF (1 << 8) #define INT_PEND_RESOURCE_CONFLICT (1 << 4) #define INT_PEND_TIME_OUT (1 << 0) #define EWR_CON (0x0300) #define EWR_EN_F (1 << 0) #define EWR_TIMER (0x0304) #define TIMER_VALUE(_v) ((_v) << 0) #define TIMER_VALUE_GET(_v) (((_v) >> 0) & 0xffffffff) #define PLL_SLEEP_CON (0x0310) #define SLEEP_CTRL_MODE_F (1 << 8) #define PLL_SLEEP_MASK_OUTIF1 (1 << 5) #define PLL_SLEEP_MASK_OUTIF0 (1 << 4) #define PLL_SLEEP_EN_OUTIF1_F (1 << 1) #define PLL_SLEEP_EN_OUTIF0_F (1 << 0) #define WAIT_CYCLE_AFTER_SFR_UPDATE (0x0340) #define WAIT_CYCLE_AFTER_SFR_UPDATE_V(_v) ((_v) << 0) #define WAIT_CYCLE_AFTER_SFR_UPDATE_MASK (0x3f << 0) #define DATA_PATH_CON (0x0200) #define ENHANCE_PATH_F(_v) ((_v) << 12) #define ENHANCE_PATH_MASK (0x7 << 12) #define ENHANCE_PATH_GET(_v) (((_v) >> 12) & 0x7) #define COMP_OUTIF_PATH_F(_v) ((_v) << 0) #define COMP_OUTIF_PATH_MASK (0xff << 0) #define COMP_OUTIF_PATH_GET(_v) (((_v) >> 0) & 0xff) #define CWB_PATH_EN (1 << 2) #define CLOCK_CON (0x5000) /* * [28] QACTIVE_PLL_VALUE = 0 * [24] QACTIVE_VALUE = 0 * 0: QACTIVE is dynamically changed by DECON h/w, * 1: QACTIVE is stuck to 1'b1 * [16] AUTO_CG_EN_CTRL (1=en / 0=dis) * [12] AUTO_CG_EN_OUTIF * [ 8] AUTO_CG_EN_COMP * [ 4] AUTO_CG_EN_ENH * [ 0] AUTO_CG_EN_BLD */ /* clock gating is disabled during initial bringup */ #define CLOCK_CON_AUTO_CG_MASK (0x11111 << 0) #define CLOCK_CON_QACTIVE_MASK ((0x1 << 24) | (0x1 << 28)) #define CLOCK_CON_QACTIVE_PLL_ON (0x1 << 28) #define SECURE_CON (0x5010) #define PSLVERR_EN (1 << 0) //------------------------------------------------------------------- // DECON_WIN //------------------------------------------------------------------- /* WIN index offset increment : 0x1000 */ #define WIN_OFFSET(_id) (0x0000 + 0x1000 * (_id)) #define WIN0_FUNC_CON_0 (0x0004) #define WIN0_FUNC_CON_1 (0x0008) #define WIN0_START_POSITION (0x000C) #define WIN0_END_POSITION (0x0010) #define WIN0_COLORMAP_0 (0x0014) #define WIN0_COLORMAP_1 (0x0018) #define WIN0_START_TIME_CON (0x001C) /* this can be handled by Secure OS */ #define WIN_SECURE_CON(_id) (WIN_OFFSET(_id) + 0x0) #define TZPC_FLAG_WIN_F (1 << 0) #define TZPC_WIN_SECURE (0 << 0) #define TZPC_WIN_NONSECURE (1 << 0) /* BLENDER */ #define WIN_FUNC_CON_0(_id) (WIN_OFFSET(_id) + 0x4) #define WIN_ALPHA1_F(_v) (((_v) & 0xFF) << 24) #define WIN_ALPHA1_MASK (0xFFU << 24) #define WIN_ALPHA0_F(_v) (((_v) & 0xFF) << 16) #define WIN_ALPHA0_MASK (0xFF << 16) #define WIN_ALPHA_GET(_v, _n) (((_v) >> (16 + 8 * (_n))) & 0xFF) #define WIN_FUNC_F(_v) (((_v) & 0xF) << 8) #define WIN_FUNC_MASK (0xF << 8) #define WIN_FUNC_GET(_v) (((_v) >> 8) & 0xf) #define WIN_SRESET (1 << 4) #define WIN_ALPHA_MULT_SRC_SEL_F(_v) (((_v) & 0x3) << 0) #define WIN_ALPHA_MULT_SRC_SEL_MASK (0x3 << 0) #define WIN_FUNC_CON_1(_id) (WIN_OFFSET(_id) + 0x8) #define WIN_FG_ALPHA_D_SEL_F(_v) (((_v) & 0xF) << 24) #define WIN_FG_ALPHA_D_SEL_MASK (0xF << 24) #define WIN_BG_ALPHA_D_SEL_F(_v) (((_v) & 0xF) << 16) #define WIN_BG_ALPHA_D_SEL_MASK (0xF << 16) #define WIN_FG_ALPHA_A_SEL_F(_v) (((_v) & 0xF) << 8) #define WIN_FG_ALPHA_A_SEL_MASK (0xF << 8) #define WIN_BG_ALPHA_A_SEL_F(_v) (((_v) & 0xF) << 0) #define WIN_BG_ALPHA_A_SEL_MASK (0xF << 0) #define WIN_START_POSITION(_id) (WIN_OFFSET(_id) + 0xC) #define WIN_STRPTR_Y_F(_v) (((_v) & 0x3FFF) << 16) #define WIN_STRPTR_X_F(_v) (((_v) & 0x3FFF) << 0) #define WIN_END_POSITION(_id) (WIN_OFFSET(_id) + 0x10) #define WIN_ENDPTR_Y_F(_v) (((_v) & 0x3FFF) << 16) #define WIN_ENDPTR_X_F(_v) (((_v) & 0x3FFF) << 0) #define WIN_COLORMAP_0(_id) (WIN_OFFSET(_id) + 0x14) #define WIN_MAPCOLOR_A_F(_v) ((_v) << 16) #define WIN_MAPCOLOR_A_MASK (0xff << 16) #define WIN_MAPCOLOR_R_F(_v) ((_v) << 0) #define WIN_MAPCOLOR_R_MASK (0x3ff << 0) #define WIN_COLORMAP_1(_id) (WIN_OFFSET(_id) + 0x18) #define WIN_MAPCOLOR_G_F(_v) ((_v) << 16) #define WIN_MAPCOLOR_G_MASK (0x3ff << 16) #define WIN_MAPCOLOR_B_F(_v) ((_v) << 0) #define WIN_MAPCOLOR_B_MASK (0x3ff << 0) #define WIN_START_TIME_CON(_id) (WIN_OFFSET(_id) + 0x1C) #define WIN_START_TIME_CONTROL_F(_v) ((_v) << 0) #define WIN_START_TIME_CONTROL_MASK (0x3fff << 0) //------------------------------------------------------------------- // DECON_WINCON //------------------------------------------------------------------- /* WIN index offset increment : 0x1000 */ #define DECON_CON_WIN(_id) (WIN_OFFSET(_id) + 0x0) #define WIN_CHMAP_F(_ch) (((_ch) & 0xF) << 4) #define WIN_CHMAP_MASK (0xF << 4) #define WIN_MAPCOLOR_EN_F (1 << 1) #define _WIN_EN_F (1 << 0) #define WIN_EN_F(_win) _WIN_EN_F #endif /* _REGS_DECON_H */