/* * * Copyright (c) 2012-2019, Samsung Electronics Co., Ltd. * http://www.samsung.com * * Jaehoe Yang * Jiun Yu * * Register definition file for Samsung Display Pre-Processor driver * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __DPP_REGS_H__ #define __DPP_REGS_H__ /* *------------------------------------------------------------------- * RDMA(L0~L5) SFR list * base address : 0x1C0B_0000 * < Layer.offset > * L0 L1 L2 L3 L4 L5 * 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 *------------------------------------------------------------------- */ /* SHADOW: 0x400 ~ 0x800 */ #define DMA_SHD_OFFSET 0x0400 #define RDMA_ENABLE 0x0000 #define IDMA_ASSIGNED_MO(_v) ((_v) << 24) #define IDMA_ASSIGNED_MO_MASK (0xffu << 24) #define IDMA_SRESET (1 << 8) #define IDMA_SFR_UPDATE_FORCE (1 << 4) #define IDMA_OP_STATUS (1 << 2) #define OP_STATUS_IDLE (0) #define OP_STATUS_BUSY (1) #define IDMA_INST_OFF_PEND (1 << 1) #define INST_OFF_PEND (1) #define INST_OFF_NOT_PEND (0) #define RDMA_IRQ 0x0004 #define IDMA_AXI_ADDR_ERR_IRQ (1 << 26) #define IDMA_LB_CONFLICT_IRQ (1 << 25) #define IDMA_MO_CONFLICT_IRQ (1 << 24) #define IDMA_FBC_ERR_IRQ (1 << 23) #define IDMA_RECOVERY_TRG_IRQ (1 << 22) #define IDMA_CONFIG_ERR_IRQ (1 << 21) #define IDMA_INST_OFF_DONE (1 << 20) #define IDMA_READ_SLAVE_ERR_IRQ (1 << 19) #define IDMA_DEADLOCK_IRQ (1 << 17) #define IDMA_FRAME_DONE_IRQ (1 << 16) #define IDMA_ALL_IRQ_CLEAR (0x7FB << 16) #define IDMA_AXI_ADDR_ERR_IRQ_MASK (1 << 11) #define IDMA_LB_CONFLICT_MASK (1 << 10) #define IDMA_MO_CONFLICT_MASK (1 << 9) #define IDMA_FBC_ERR_MASK (1 << 8) #define IDMA_RECOVERY_TRG_MASK (1 << 7) #define IDMA_CONFIG_ERR_MASK (1 << 6) #define IDMA_INST_OFF_DONE_MASK (1 << 5) #define IDMA_READ_SLAVE_ERR_MASK (1 << 4) #define IDMA_DEADLOCK_MASK (1 << 2) #define IDMA_FRAME_DONE_MASK (1 << 1) #define IDMA_ALL_IRQ_MASK (0x7FB << 1) #define IDMA_IRQ_ENABLE (1 << 0) /* defined for common part of driver only */ #define IDMA_RECOVERY_START_IRQ IDMA_RECOVERY_TRG_IRQ #define IDMA_READ_SLAVE_ERROR IDMA_READ_SLAVE_ERR_IRQ #define IDMA_STATUS_DEADLOCK_IRQ IDMA_DEADLOCK_IRQ #define IDMA_STATUS_FRAMEDONE_IRQ IDMA_FRAME_DONE_IRQ #define IDMA_AFBC_CONFLICT_IRQ IDMA_LB_CONFLICT_IRQ #define RDMA_IN_CTRL_0 0x0008 #define IDMA_ALPHA(_v) ((_v) << 24) #define IDMA_ALPHA_MASK (0xffu << 24) #define IDMA_IC_MAX(_v) ((_v) << 16) #define IDMA_IC_MAX_MASK (0xff << 16) #define IDMA_SBWC_LOSSY (1 << 14) #define IDMA_IMG_FORMAT(_v) ((_v) << 8) #define IDMA_IMG_FORMAT_MASK (0x3f << 8) #define IDMA_IMG_FORMAT_ARGB8888 (0) #define IDMA_IMG_FORMAT_ABGR8888 (1) #define IDMA_IMG_FORMAT_RGBA8888 (2) #define IDMA_IMG_FORMAT_BGRA8888 (3) #define IDMA_IMG_FORMAT_XRGB8888 (4) #define IDMA_IMG_FORMAT_XBGR8888 (5) #define IDMA_IMG_FORMAT_RGBX8888 (6) #define IDMA_IMG_FORMAT_BGRX8888 (7) #define IDMA_IMG_FORMAT_RGB565 (8) #define IDMA_IMG_FORMAT_BGR565 (9) #define IDMA_IMG_FORMAT_ARGB1555 (12) #define IDMA_IMG_FORMAT_ARGB4444 (13) #define IDMA_IMG_FORMAT_ABGR1555 (14) #define IDMA_IMG_FORMAT_ABGR4444 (15) #define IDMA_IMG_FORMAT_ARGB2101010 (16) #define IDMA_IMG_FORMAT_ABGR2101010 (17) #define IDMA_IMG_FORMAT_RGBA1010102 (18) #define IDMA_IMG_FORMAT_BGRA1010102 (19) #define IDMA_IMG_FORMAT_RGBA5551 (20) #define IDMA_IMG_FORMAT_RGBA4444 (21) #define IDMA_IMG_FORMAT_BGRA5551 (22) #define IDMA_IMG_FORMAT_BGRA4444 (23) #define IDMA_IMG_FORMAT_YUV420_2P (24) #define IDMA_IMG_FORMAT_YVU420_2P (25) #define IDMA_IMG_FORMAT_YUV420_8P2 (26) #define IDMA_IMG_FORMAT_YVU420_8P2 (27) #define IDMA_IMG_FORMAT_YUV420_P010 (29) #define IDMA_IMG_FORMAT_YVU420_P010 (28) #define IDMA_IMG_FORMAT_YVU422_2P (56) #define IDMA_IMG_FORMAT_YUV422_2P (57) #define IDMA_IMG_FORMAT_YVU422_8P2 (58) #define IDMA_IMG_FORMAT_YUV422_8P2 (59) #define IDMA_IMG_FORMAT_YVU422_P210 (60) #define IDMA_IMG_FORMAT_YUV422_P210 (61) #define IDMA_ROT(_v) ((_v) << 4) #define IDMA_ROT_MASK (0x7 << 4) #define IDMA_ROT_X_FLIP (1 << 4) #define IDMA_ROT_Y_FLIP (2 << 4) #define IDMA_ROT_180 (3 << 4) #define IDMA_ROT_90 (4 << 4) #define IDMA_ROT_90_X_FLIP (5 << 4) #define IDMA_ROT_90_Y_FLIP (6 << 4) #define IDMA_ROT_270 (7 << 4) #define IDMA_FLIP(_v) ((_v) << 4) #define IDMA_FLIP_MASK (0x3 << 4) #define IDMA_CSET_EN (1 << 3) // must keep as '0' #define IDMA_SBWC_EN (1 << 2) #define IDMA_AFBC_EN (1 << 1) #define IDMA_BLOCK_EN (1 << 0) #define RDMA_IN_CTRL_1 0x000C #define IDMA_SPLIT_8K_LR (1 << 1) #define IDMA_SPLIT_8K_EN (1 << 0) #define RDMA_SRC_SIZE 0x0010 #define IDMA_SRC_HEIGHT(_v) ((_v) << 16) #define IDMA_SRC_HEIGHT_MASK (0xFFFF << 16) #define IDMA_SRC_WIDTH(_v) ((_v) << 0) #define IDMA_SRC_WIDTH_MASK (0xFFFF << 0) #define RDMA_SRC_OFFSET 0x0014 #define IDMA_SRC_OFFSET_Y(_v) ((_v) << 16) #define IDMA_SRC_OFFSET_Y_MASK (0x3FFF << 16) #define IDMA_SRC_OFFSET_X(_v) ((_v) << 0) #define IDMA_SRC_OFFSET_X_MASK (0x3FFF << 0) #define RDMA_IMG_SIZE 0x0018 #define IDMA_IMG_HEIGHT(_v) ((_v) << 16) #define IDMA_IMG_HEIGHT_MASK (0x3FFF << 16) #define IDMA_IMG_WIDTH(_v) ((_v) << 0) #define IDMA_IMG_WIDTH_MASK (0x3FFF << 0) #define RDMA_BLOCK_OFFSET 0x0020 #define IDMA_BLK_OFFSET_Y(_v) ((_v) << 16) #define IDMA_BLK_OFFSET_Y_MASK (0x3FFF << 16) #define IDMA_BLK_OFFSET_X(_v) ((_v) << 0) #define IDMA_BLK_OFFSET_X_MASK (0x3FFF << 0) #define RDMA_BLOCK_SIZE 0x0024 #define IDMA_BLK_HEIGHT(_v) ((_v) << 16) #define IDMA_BLK_HEIGHT_MASK (0x3FFF << 16) #define IDMA_BLK_WIDTH(_v) ((_v) << 0) #define IDMA_BLK_WIDTH_MASK (0x3FFF << 0) #define RDMA_BASEADDR_Y8 0x0040 #define RDMA_BASEADDR_C8 0x0044 #define RDMA_BASEADDR_Y2 0x0048 #define RDMA_BASEADDR_C2 0x004C #define RDMA_SRC_STRIDE_0 0x0050 #define IDMA_STRIDE_3_SEL (1 << 23) #define IDMA_STRIDE_2_SEL (1 << 22) #define IDMA_STRIDE_1_SEL (1 << 21) #define IDMA_STRIDE_0_SEL (1 << 20) #define IDMA_STRIDE_SEL(_v) ((_v) << 20) #define IDMA_STRIDE_SEL_MASK (0xF << 20) #define IDMA_CHROM_STRIDE_SEL (1 << 16) #define IDMA_CHROM_STRIDE(_v) ((_v) << 0) #define IDMA_CHROM_STRIDE_MASK (0xFFFF << 0) #define RDMA_SRC_STRIDE_1 0x0054 #define IDMA_STRIDE_1(_v) ((_v) << 16) #define IDMA_STRIDE_1_MASK (0xffff << 16) #define IDMA_STRIDE_0(_v) ((_v) << 0) #define IDMA_STRIDE_0_MASK (0xffff << 0) #define RDMA_SRC_STRIDE_2 0x0058 #define IDMA_STRIDE_3(_v) ((_v) << 16) #define IDMA_STRIDE_3_MASK (0xffff << 16) #define IDMA_STRIDE_2(_v) ((_v) << 0) #define IDMA_STRIDE_2_MASK (0xffff << 0) #define RDMA_AFBC_PARAM 0x0060 /* [128 x n] 3: 384 byte */ #define IDMA_AFBC_BLK_BYTENUM(_v) ((_v) << 4) #define IDMA_AFBC_BLK_BYTENUM_MASK (0xf << 4) #define IDMA_AFBC_BLK_SIZE(_v) ((_v) << 0) #define IDMA_AFBC_BLK_SIZE_MASK (0x3 << 0) #define IDMA_AFBC_BLK_SIZE_16_16 (0) #define IDMA_AFBC_BLK_SIZE_32_8 (1) #define IDMA_AFBC_BLK_SIZE_64_4 (2) #define RDMA_SBWC_PARAM 0x0064 #define IDMA_SBWC_CRC_EN (1 << 16) #define IDMA_CHM_BLK_BYTENUM(_v) ((_v) << 8) #define IDMA_CHM_BLK_BYTENUM_MASK (0xf << 8) #define IDMA_LUM_BLK_BYTENUM(_v) ((_v) << 4) #define IDMA_LUM_BLK_BYTENUM_MASK (0xf << 4) /* only valid 32x4 */ #define IDMA_CHM_BLK_SIZE(_v) ((_v) << 2) #define IDMA_CHM_BLK_SIZE_MASK (0x3 << 2) #define IDMA_LUM_BLK_SIZE(_v) ((_v) << 0) #define IDMA_LUM_BLK_SIZE_MASK (0x3 << 0) #define RDMA_CSET_PARAM 0x0068 #define IDMA_GB_BASE(_v) ((_v) << 0) #define IDMA_GB_BASE_MASK (0x1f << 0) #define RDMA_RECOVERY_CTRL 0x0070 #define IDMA_RECOVERY_NUM(_v) ((_v) << 1) #define IDMA_RECOVERY_NUM_MASK (0x7fffffff << 1) #define IDMA_RECOVERY_EN (1 << 0) #define RDMA_DEADLOCK_CTRL 0x0100 #define IDMA_DEADLOCK_NUM(_v) ((_v) << 1) #define IDMA_DEADLOCK_NUM_MASK (0x7fffffffu << 1) #define IDMA_DEADLOCK_NUM_EN (1 << 0) #define RDMA_BUS_CTRL 0x0110 #define IDMA_ARCACHE_P3 ((_v) << 12) #define IDMA_ARCACHE_P3_MASK (0xf << 12) #define IDMA_ARCACHE_P2 ((_v) << 8) #define IDMA_ARCACHE_P2_MASK (0xf << 8) #define IDMA_ARCACHE_P1 ((_v) << 4) #define IDMA_ARCACHE_P1_MASK (0xf << 4) #define IDMA_ARCACHE_P0 ((_v) << 0) #define IDMA_ARCACHE_P0_MASK (0xf << 0) #define RDMA_LLC_CTRL 0x0114 #define IDMA_DATA_SAHRE_TYPE_P3(_v) ((_v) << 28) #define IDMA_DATA_SAHRE_TYPE_P3_MASK (0x3 << 28) #define IDMA_LLC_HINT_P3(_v) ((_v) << 24) #define IDMA_LLC_HINT_P3_MASK (0x7 << 24) #define IDMA_DATA_SAHRE_TYPE_P2(_v) ((_v) << 20) #define IDMA_DATA_SAHRE_TYPE_P2_MASK (0x3 << 20) #define IDMA_LLC_HINT_P2(_v) ((_v) << 16) #define IDMA_LLC_HINT_P2_MASK (0x7 << 16) #define IDMA_DATA_SAHRE_TYPE_P1(_v) ((_v) << 12) #define IDMA_DATA_SAHRE_TYPE_P1_MASK (0x3 << 12) #define IDMA_LLC_HINT_P1(_v) ((_v) << 8) #define IDMA_LLC_HINT_P1_MASK (0x7 << 8) #define IDMA_DATA_SAHRE_TYPE_P0(_v) ((_v) << 4) #define IDMA_DATA_SAHRE_TYPE_P0_MASK (0x3 << 4) #define IDMA_LLC_HINT_P0(_v) ((_v) << 0) #define IDMA_LLC_HINT_P0_MASK (0x7 << 0) #define RDMA_PERF_CTRL 0x0120 #define IDMA_DEGRADATION_TIME(_v) ((_v) << 16) #define IDMA_DEGRADATION_TIME_MASK (0xFFFF << 16) #define IDMA_IC_MAX_DEG(_v) ((_v) << 4) #define IDMA_IC_MAX_DEG_MASK (0xFF << 4) #define IDMA_DEGRADATION_EN (1 << 0) /* _n: [0,7], _v: [0x0, 0xF] */ #define RDMA_QOS_LUT_LOW 0x0130 #define RDMA_QOS_LUT_HIGH 0x0134 #define IDMA_QOS_LUT(_n, _v) ((_v) << (4*(_n))) #define IDMA_QOS_LUT_MASK(_n) (0xF << (4*(_n))) #define RDMA_DYNAMIC_GATING_EN 0x0140 #define IDMA_SRAM_CG_EN (1U << 31) #define IDMA_DG_EN(_n, _v) ((_v) << (_n)) #define IDMA_DG_EN_MASK(_n) (1 << (_n)) #define IDMA_DG_EN_ALL (0x7FFFFFFF << 0) #define RDMA_MST_SECURITY 0x200 #define RDMA_SLV_SECURITY 0x204 #define RDMA_SECURE_MASK (1 << 0) /* *------------------------------------------------------------------- * DPP(L0~L5, L12) SFR list * base address : 0x1C0D_0000 * < Layer.offset > * L0 L1 L2 L3 L4 L5 L12 * 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0xC000 *------------------------------------------------------------------- */ #define DPP_COM_SHD_OFFSET 0x0100 #define DPP_SCL_SHD_OFFSET 0x0400 #define DPP_COM_VERSION 0x0000 #define DPP_VERSION 0x06010000 #define DPP_COM_SWRST_CON 0x0004 #define DPP_SRESET (1 << 0) #define DPP_COM_QCH_CON 0x0008 #define DPP_QACTIVE (1 << 0) #define DPP_COM_PSLVERR_CON 0x000c #define DPP_PSLVERR_EN (1 << 0) #define DPP_COM_IRQ_CON 0x0010 #define DPP_IRQ_EN (1 << 0) #define DPP_COM_IRQ_MASK 0x0014 #define DPP_CFG_ERROR_MASK (1 << 1) #define DPP_FRM_DONE_MASK (1 << 0) #define DPP_ALL_IRQ_MASK (0x3 << 0) #define DPP_COM_IRQ_STATUS 0x0018 #define DPP_CFG_ERROR_IRQ (1 << 1) #define DPP_FRM_DONE_IRQ (1 << 0) #define DPP_ALL_IRQ_CLEAR (0x3 << 0) #define DPP_COM_CFG_ERROR_STATUS 0x001c #define DPP_CFG_ERR_SCL_POS (1 << 4) #define DPP_CFG_ERR_SCL_RATIO (1 << 3) #define DPP_CFG_ERR_ODD_SIZE (1 << 2) #define DPP_CFG_ERR_MAX_SIZE (1 << 1) #define DPP_CFG_ERR_MIN_SIZE (1 << 0) #define DPP_COM_LC_CON 0x0020 #define DPP_LC_CAPTURE_MASK (1 << 2) #define DPP_LC_MODE(_V) ((_V) << 1) #define DPP_LC_MODE_MASK (1 << 1) #define DPP_LC_EN(_v) ((_v) << 0) #define DPP_LC_EN_MASK (1 << 0) #define DPP_COM_LC_STATUS 0x0024 #define DPP_LC_COUNTER_GET(_v) (((_v) >> 0) & 0xFFFFFFFF) #define DPP_COM_DBG_CON 0x0028 #define DPP_DBG_SEL(_v) ((_v) << 16) #define DPP_DBG_EN (1 << 0) #define DPP_COM_DBG_STATUS 0x002c #define DPP_COM_OP_STATUS 0x0030 #define DPP_OP_STATUS (1 << 0) #define DPP_COM_TZPC 0x0034 #define DPP_TZPC (1 << 0) #define DPP_COM_IO_CON 0x0038 #define DPP_ALPHA_SEL(_v) ((_v) << 7) #define DPP_ALPHA_SEL_MASK (1 << 7) #define DPP_BPC_MODE(_v) ((_v) << 6) #define DPP_BPC_MODE_MASK (1 << 6) #define DPP_IMG_FORMAT(_v) ((_v) << 0) #define DPP_IMG_FORMAT_MASK (0x7 << 0) #define DPP_IMG_FORMAT_ARGB8888 (0 << 0) #define DPP_IMG_FORMAT_ARGB8101010 (1 << 0) #define DPP_IMG_FORMAT_YUV420_8P (2 << 0) #define DPP_IMG_FORMAT_YUV420_P010 (3 << 0) #define DPP_IMG_FORMAT_YUV420_8P2 (4 << 0) #define DPP_IMG_FORMAT_YUV422_8P (5 << 0) #define DPP_IMG_FORMAT_YUV422_P210 (6 << 0) #define DPP_IMG_FORMAT_YUV422_8P2 (7 << 0) #define DPP_COM_IMG_SIZE 0x003c #define DPP_IMG_HEIGHT(_v) ((_v) << 16) #define DPP_IMG_HEIGHT_MASK (0x3FFF << 16) #define DPP_IMG_WIDTH(_v) ((_v) << 0) #define DPP_IMG_WIDTH_MASK (0x3FFF << 0) #define DPP_COM_CSC_CON 0x0040 #define DPP_CSC_TYPE(_v) ((_v) << 2) #define DPP_CSC_TYPE_MASK (3 << 2) #define DPP_CSC_RANGE(_v) ((_v) << 1) #define DPP_CSC_RANGE_MASK (1 << 1) #define DPP_CSC_MODE(_v) ((_v) << 0) #define DPP_CSC_MODE_MASK (1 << 0) #endif /* __DPP_REGS_H__ */