/*
 *
 * Copyright (C) 2012-2020, Samsung Electronics Co., Ltd.
 *
 * Board base registers and structures
 */

#pragma once

#include "base.h"

#define USE_TOUCH_INTERRUPT

/* Display constants */
#define BOARD_GRAYSCALE_DEPTH              8
#define BOARD_REDBITDEPTH                  8
#define BOARD_GREENBITDEPTH                8
#define BOARD_BLUEBITDEPTH                 8
#define BOARD_ALPHABITDEPTH                8
#define BOARD_BITSPERPIXEL                 32 /* RGBA */

#define BOARD_WDENSITY                     368
#define BOARD_HDENSITY                     368

#define FB_ALIGN                           SIZE_4KB

/* Define for specific values which are dependent by model */
#define SENSOR_MAX_X_DEFAULT               4095
#define SENSOR_MAX_Y_DEFAULT               4095

/* =============================================== */
/* Board memory map */
/* Display controller(DECON) */
#define DISP_DECON_BASE                    0x13060000 /* Display controller(DECON) */
#define DISP_DECON_SEC_BASE                0x13040000 /* Display controller(DECON) */
#define DISP_DPP_SEC_BASE                  0x13050000 /* L0 */
#define DISP_IDMA_SEC_BASE                 0x130A0000 /* L0 */
#define DISP_IDMA_COMMON_BASE              0x130B0000 /* Display controller(DECON) */
#define DISP_MIPI_BASE                     0x13070000 /* Display controller(DECON) */

#define SMMUDECON0_BASE                    0x130C0000 /* Display system MMU : DPU0_S1_NS for L0_NS */
#define SMMUDECON1_BASE                    0x130D0000 /* Display system MMU : DPU0_S1_S  for L0_S */

/* Interrupt IDs */
#define NUM_SGI                            16
#define NUM_PPI                            16
#define SPI_IRQ(x)                         (NUM_SGI + NUM_PPI + x)

#define TOUCH_INT_NUM                      SPI_IRQ(1)

/* I2C driver name for touch interface */
#define TOUCH_I2C_DRVNAME                  "/dev/hsi2c/hsi2c0"

/* GPIO registers and bits */
#define GPIO_PA_BASE                       0x11850000

#define GPA0_CON_OFFSET                    0x0000
#define GPA0_0_CONF_MASK                   (0xFu << 0)
#define GPA0_0_CONF_EINT                   (0xFu << 0)

#define WEINT_GPA0_CON_OFFSET              0x0700
#define GPA0_EINT0_MASK                    (0x7u << 0)
#define GPA0_EINT0_LOW                     (0x0u << 0)
#define GPA0_EINT0_HIGH                    (0x1u << 0)
#define GPA0_EINT0_FALL                    (0x2u << 0)
#define GPA0_EINT0_RISE                    (0x3u << 0)

#define WEINT_GPA0_MASK_OFFSET             0x0900

#define WEINT_GPA0_PEND_OFFSET             0x0A00
#define WEINT_MASK_BIT(x)                  (0x1u << (x))
#define WEINT_GPA0_0                       0
#define WEINT_GPA0_0_PEND                  WEINT_MASK_BIT(WEINT_GPA0_0)