/* * Copyright 2012-2019, Samsung Electronics Co. Ltd * This software is proprietary of Samsung Electronics. * No part of this software, either material or conceptual may be copied or * distributed, transmitted, * transcribed, stored in a retrieval system or translated into any human * or computer language in any form by any means, * electronic, mechanical, manual or otherwise, or disclosed * to third parties without the express written permission of Samsung * Electronics. */ #ifndef __DPP_REGS_H__ #define __DPP_REGS_H__ #define IDMA_ENABLE 0x0000 #define IDMA_SRSET (1 << 24) #define IDMA_SFR_CLOCK_GATE_EN (1 << 10) #define IDMA_SRAM_CLOCK_GATE_EN (1 << 9) #define IDMA_ALL_CLOCK_GATE_EN_MASK (0x3 << 9) #define IDMA_FRAME_START_FORCE (1 << 5) #define IDMA_SFR_UPDATE_FORCE (1 << 4) #define IDMA_OP_STATUS (1 << 2) #define OP_STATUS_IDLE (0) #define OP_STATUS_BUSY (1) #define IDMA_SECURE_MODE (1 << 0) #define SECURE_MODE_DISABLE (0) #define SECURE_MODE_ENABLE (1) #define IDMA_IRQ 0x0004 #define IDMA_AFBC_TIMEOUT_IRQ (1 << 23) #define IDMA_RECOVERY_START_IRQ (1 << 22) #define IDMA_CONFIG_ERROR (1 << 21) #define IDMA_LOCAL_HW_RESET_DONE (1 << 20) #define IDMA_READ_SLAVE_ERROR (1 << 19) #define IDMA_STATUS_DEADLOCK_IRQ (1 << 17) #define IDMA_STATUS_FRAMEDONE_IRQ (1 << 16) #define IDMA_ALL_IRQ_CLEAR (0xfb << 16) #define IDMA_AFBC_TIMEOUT_MASK (1 << 8) #define IDMA_RECOVERY_START_MASK (1 << 7) #define IDMA_CONFIG_ERROR_MASK (1 << 6) #define IDMA_LOCAL_HW_RESET_DONE_MASK (1 << 5) #define IDMA_READ_SLAVE_ERROR_MASK (1 << 4) #define IDMA_IRQ_DEADLOCK_MASK (1 << 2) #define IDMA_IRQ_FRAMEDONE_MASK (1 << 1) #define IDMA_ALL_IRQ_MASK (0xfb << 1) #define IDMA_IRQ_ENABLE (1 << 0) #define IDMA_IN_CON 0x0008 #define IDMA_IN_IC_MAX(_v) ((_v) << 19) #define IDMA_IN_IC_MAX_MASK (0x7f << 19) #define IDMA_IMG_FORMAT(_v) ((_v) << 11) #define IDMA_IMG_FORMAT_MASK (0x1f << 11) #define IDMA_IMG_FORMAT_ARGB8888 (0) #define IDMA_IMG_FORMAT_ABGR8888 (1) #define IDMA_IMG_FORMAT_RGBA8888 (2) #define IDMA_IMG_FORMAT_BGRA8888 (3) #define IDMA_IMG_FORMAT_XRGB8888 (4) #define IDMA_IMG_FORMAT_XBGR8888 (5) #define IDMA_IMG_FORMAT_RGBX8888 (6) #define IDMA_IMG_FORMAT_BGRX8888 (7) #define IDMA_IMG_FORMAT_RGB565 (8) #define IDMA_IMG_FORMAT_ARGB1555 (12) #define IDMA_IMG_FORMAT_ARGB4444 (13) #define IDMA_IMG_FORMAT_YUV420_2P (24) #define IDMA_IMG_FORMAT_YVU420_2P (25) #define IDMA_IN_FLIP(_v) ((_v) << 8) #define IDMA_IN_FLIP_MASK (0x3 << 8) #define IDMA_AFBC_EN (1 << 7) #define IDMA_AFBC_TO_EN (1 << 6) #define IDMA_IN_CHROMINANCE_STRIDE_SEL (1 << 4) #define IDMA_BLOCK_EN (1 << 3) #define IDMA_OUT_CON 0x000C #define IDMA_OUT_FRAME_ALPHA(_v) ((_v) << 24) #define IDMA_OUT_FRAME_ALPHA_MASK (0xffu << 24) #define IDMA_SRC_SIZE 0x0010 #define IDMA_SRC_HEIGHT(_v) ((_v) << 16) #define IDMA_SRC_HEIGHT_MASK (0x3FFF << 16) #define IDMA_SRC_WIDTH(_v) ((_v) << 0) #define IDMA_SRC_WIDTH_MASK (0xFFFF << 0) #define IDMA_SRC_OFFSET 0x0014 #define IDMA_SRC_OFFSET_Y(_v) ((_v) << 16) #define IDMA_SRC_OFFSET_Y_MASK (0x1FFF << 16) #define IDMA_SRC_OFFSET_X(_v) ((_v) << 0) #define IDMA_SRC_OFFSET_X_MASK (0x1FFF << 0) #define IDMA_IMG_SIZE 0x0018 #define IDMA_IMG_HEIGHT(_v) ((_v) << 16) #define IDMA_IMG_HEIGHT_MASK (0x1FFF << 16) #define IDMA_IMG_WIDTH(_v) ((_v) << 0) #define IDMA_IMG_WIDTH_MASK (0x1FFF << 0) #define IDMA_IN_QOS_LUT07_00 0x0034 #define IDMA_IN_QOS_LUT15_08 0x0038 #define IDMA_IN_QOS_LUT(_n, _v) ((_v) << (4 * (_n))) #define IDMA_IN_QOS_LUT_MASK(_n) (0xF << (4 * (_n))) #define IDMA_IN_BASE_ADDR_Y 0x0040 #define IDMA_IN_BASE_ADDR_C 0x0044 #define IDMA_DYNAMIC_GATING_EN 0x0058 #define IDMA_DG_EN(_n, _v) ((_v) << (_n)) #define IDMA_DG_EN_MASK(_n) (1 << (_n)) #define IDMA_DG_EN_ALL (0xFF << 0) #define DPP_ENABLE 0x0000 #define DPP_SRSET (1 << 24) #define DPP_SFR_CLOCK_GATE_EN (1 << 10) #define DPP_SRAM_CLOCK_GATE_EN (1 << 9) #define DPP_INT_CLOCK_GATE_EN (1 << 8) #define DPP_ALL_CLOCK_GATE_EN_MASK (0x7 << 8) #define DPP_SFR_UPDATE_FORCE (1 << 4) #define DPP_QCHANNEL_EN (1 << 3) #define DPP_OP_STATUS (1 << 2) #define DPP_SECURE_MODE (1 << 0) #define DPP_IRQ 0x0004 #define DPP_CONFIG_ERROR (1 << 21) #define DPP_STATUS_FRAMEDONE_IRQ (1 << 16) #define DPP_ALL_IRQ_CLEAR (0x21 << 16) #define DPP_CONFIG_ERROR_MASK (1 << 6) #define DPP_IRQ_FRAMEDONE_MASK (1 << 1) #define DPP_ALL_IRQ_MASK (0x21 << 1) #define DPP_IRQ_ENABLE (1 << 0) #define DPP_IN_CON 0x0008 #define DPP_CSC_TYPE(_v) ((_v) << 18) #define DPP_CSC_TYPE_MASK (1 << 18) #define DPP_CSC_RANGE(_v) ((_v) << 17) #define DPP_CSC_RANGE_MASK (1 << 17) #define DPP_CSC_MODE(_v) ((_v) << 16) #define DPP_CSC_MODE_MASK (1 << 16) #define DPP_IMG_FORMAT(_v) ((_v) << 11) #define DPP_IMG_FORMAT_MASK (1 << 11) #define DPP_ALPHA_SEL(_v) ((_v) << 10) #define DPP_ALPHA_SEL_MASK (1 << 10) #define DPP_IMG_SIZE 0x0018 #define DPP_IMG_HEIGHT(_v) ((_v) << 16) #define DPP_IMG_HEIGHT_MASK (0x1FFF << 16) #define DPP_IMG_WIDTH(_v) ((_v) << 0) #define DPP_IMG_WIDTH_MASK (0x1FFF << 0) #define DPP_MAIN_H_RATIO 0x0044 #define DPP_H_RATIO(_v) ((_v) << 0) #define DPP_H_RATIO_MASK (0xFFFFFF << 0) #define DPP_MAIN_V_RATIO 0x0048 #define DPP_V_RATIO(_v) ((_v) << 0) #define DPP_V_RATIO_MASK (0xFFFFFF << 0) #define DPP_H_COEF(n, s, x) (0x290 + (n) * 0x4 + (s) * 0x24 + (x) * 0x200) #define DPP_V_COEF(n, s, x) (0x200 + (n) * 0x4 + (s) * 0x24 + (x) * 0x200) #define DPP_DYNAMIC_GATING_EN 0x0A54 #define DPP_DG_EN(_n, _v) ((_v) << (_n)) #define DPP_DG_EN_MASK(_n) (1 << (_n)) #define DPP_DG_EN_ALL (0x5F << 0) #endif /* __DPP_REGS_H__ */