#ifndef __PANEL_H__
#define __PANEL_H__

#include "cal_common/cal_config.h"

//#define CONFIG_PANEL_S6E3FAB
#define CONFIG_PANEL_S6E8FC1
//#define CONFIG_PANEL_S6E3FAC
//#define CONFIG_PANEL_S6E3HAE

#ifdef CONFIG_PANEL_S6E3FAB
#define VACTIVE 2400
#define HACTIVE	1080
#define VFP	8
#define VSA	1
#define VBP	15
#define HFP	2
#define DPHY_RSEL	0x0
#define DPHY_DITHER_EN	0

#define DATA_LANE_CNT		4
#define OP_MODE			1 /* 0: video, 1: command */
#define CMD_UNDERRUN_CNT	7397
#endif

#ifdef CONFIG_PANEL_S6E8FC1
#define VACTIVE 1600
#define HACTIVE	720
#define VFP	5
#define VSA	2
#define VBP	9
#define HFP	24
#define HSA	4
#define HBP	48
#define FPS	60

#define DSC_EN			0
#define DSC_CNT			0
#define DSC_SLICE_CNT		0
#define DSC_SLICE_HEIGHT	0

#define HS_CLK		511
#define ESC_CLK		20

#define DPHY_P		0x3
#define DPHY_M		0xEC
#define DPHY_S		0x3
#define DPHY_K		0x0
#define DPHY_MFR	0x0
#define DPHY_MRR	0x0
#define DPHY_SEL_PF	0x0
#define DPHY_ICP	0x0
#define DPHY_AFC_ENB	0x0
#define DPHY_EXTAFC	0x0
#define DPHY_FEED_EN	0x0
#define DPHY_FSEL	0x0
#define DPHY_FOUT_MASK	0x0
#define DPHY_RSEL	0x0
#define DPHY_DITHER_EN	0

#define DATA_LANE_CNT		4
#define OP_MODE			0 /* 0: video, 1: command */
#define CMD_UNDERRUN_CNT	4357
#endif

#ifdef CONFIG_PANEL_S6E3FAC
#define VACTIVE 2340
#define HACTIVE 1080
#define VFP     15
#define VSA     1
#define VBP     1
#define HFP     1
#define HSA     1
#define HBP     1
#define FPS     60

#define DSC_EN                  1
#define DSC_CNT                 2
#define DSC_SLICE_CNT           2
#define DSC_SLICE_HEIGHT        117

#define HS_CLK          1362
#define ESC_CLK         20

#define DPHY_P          0x5
#define DPHY_M          0x59
#define DPHY_S          0x0
#define DPHY_K          0xAC00
#define DPHY_MFR        0x0
#define DPHY_MRR        0x0
#define DPHY_SEL_PF     0x0
#define DPHY_ICP        0x0
#define DPHY_AFC_ENB    0x0
#define DPHY_EXTAFC     0x0
#define DPHY_FEED_EN    0x0
#define DPHY_FSEL       0x0
#define DPHY_FOUT_MASK  0x0
#define DPHY_RSEL       0x0
#define DPHY_DITHER_EN  0

#define DATA_LANE_CNT           4
#define OP_MODE                 1 /* 0: video, 1: command */
#define CMD_UNDERRUN_CNT        10442
#endif

enum dsim_panel_mode {
	DSIM_VIDEO_MODE = 0,
	DSIM_COMMAND_MODE,
};

struct panel_information {
	unsigned int vactive;
	unsigned int vfp;
	unsigned int vsa;
	unsigned int vbp;
	unsigned int hactive;
	unsigned int hfp;
	unsigned int hsa;
	unsigned int hbp;
	unsigned int vrefresh;

	bool enabled;
	u32 dsc_count;
	u32 slice_count;
	u32 slice_height;

	u32 hs_clk;
	u32 esc_clk;

	unsigned int p;
	unsigned int m;
	unsigned int s;
	unsigned int k;
	unsigned int mfr;
	unsigned int mrr;
	unsigned int sel_pf;
	unsigned int icp;
	unsigned int afc_enb;
	unsigned int extafc;
	unsigned int feed_en;
	unsigned int fsel;
	unsigned int fout_mask;
	unsigned int rsel;
	bool dither_en;

	unsigned int data_lane_cnt;
	enum dsim_panel_mode mode;
	unsigned int cmd_underrun_cnt;
};

enum type_of_ddi {
	TYPE_OF_SM_DDI = 0,
	TYPE_OF_MAGNA_DDI,
	TYPE_OF_NORMAL_DDI,
};

struct dpu_panel_timing {
	unsigned int vactive;
	unsigned int vfp;
	unsigned int vsa;
	unsigned int vbp;

	unsigned int hactive;
	unsigned int hfp;
	unsigned int hsa;
	unsigned int hbp;

	unsigned int vrefresh;
};

struct exynos_dsc {
	bool enabled;
	u32 dsc_count;
	u32 slice_count;
	u32 slice_width;
	u32 slice_height;
};

/* return compressed DSC slice width */
static inline u32 get_comp_dsc_width(const struct exynos_dsc *dsc, u32 bpc)
{
	unsigned int slice_width_pixels =
				DIV_ROUND_UP(dsc->slice_width * bpc, 8);

	return ALIGN(DIV_ROUND_UP(slice_width_pixels, 3), 4);
}
#endif /* __PANEL_H__ */