#ifndef __SOC_H__
#define __SOC_H__

/* DECON */
#define SEC_DECON_ID			0 

#define DECON_MAIN_BASE 		0x14940000
#define DECON_WIN_BASE 			0x14950000
#define DECON_SUB_BASE 			0x14960000
#define DECON_WINCON_BASE 		0x14970000

#define DECON_MAIN_SIZE 		0xFFFF
#define DECON_WIN_SIZE 			0xFFFF
#define DECON_SUB_SIZE 			0xFFFF
#define DECON_WINCON_SIZE 		0xFFFF

/* DSIM */
#define SEC_DSIM_ID			0

#define MIPI_DSIM0_BASE 		0x148C0000
#define MIPI_DCPHY_M4M4_BASE 		0x148E0100
#define MIPI_DCPHY_M4M4_BIAS_BASE 	0x148E0000
#define SYSREG_DPU_BASE 		0x14821000

#define PMU_ALIVE_BASE 			0x11860000
#define PHY_CTRL_MIPI_DCPHY_M4M4	0x0714
#define PHY_ISO_BIT_POS			0x0

#define DSIM_BASE 			MIPI_DSIM0_BASE
#define DPHY_BASE 			MIPI_DCPHY_M4M4_BASE
#define DPHY_EXTRA_BASE 		MIPI_DCPHY_M4M4_BIAS_BASE
#define DPHY_ISO_CONTROL 		(PMU_ALIVE_BASE + PHY_CTRL_MIPI_DCPHY_M4M4)

#define DSIM_SIZE 			0x300
#define DPHY_SIZE 			0x700
#define DPHY_EXTRA_SIZE 		0x100
#define SYSREG_SIZE 			0x10
#define DPHY_ISO_SIZE			0x10

/* DPP */
#define SEC_DPP_ID			0

#define IDMA_L0_BASE 			0x14890000
#define DPP_L0_BASE 			0x14840000

#define IDMA_SIZE 			0x1000
#define DPP_SIZE 			0x1000

#define IDMA_BASE(id) 			(IDMA_L0_BASE + (id) * IDMA_SIZE)
#define DPP_BASE(id) 			(DPP_L0_BASE + (id) * DPP_SIZE)

#define DPP0_ATTR 			0x50004
#define DPP1_ATTR 			0x5043D
#define DPP2_ATTR 			0x50005
#define DPP3_ATTR 			0x50434
#define DPP4_ATTR 			0x50005
#define DPP5_ATTR 			0x50014
#define DPP6_ATTR 			0x50004
#define DPP7_ATTR 			0x50435
#define DPP_ATTR			DPP0_ATTR

/* DQE */
#define SEC_DQE_ID 			0

#define DQE_BASE 			0x149B0000
//#define EDMA_BASE

#define DQE_SIZE 			0xFFFF
//#define EDMA_SIZE

#endif /* __SOC_H__ */