/**
 * @brief  Header file for Exynos DECON driver for exynos9630.
 *
 * Copyright (c) 2012-2019, Samsung Electronics Co., Ltd.
 * MinHo Kim <m8891.kim@samsung.com>
 *
 * This software is proprietary of Samsung Electronics.
 * No part of this software, either material or conceptual may be copied
 * or distributed, transmitted, transcribed, stored in a retrieval system
 * or translated into any human or computer language in any form by any means,
 * electronic, mechanical, manual or otherwise, or disclosed to third parties
 * without the express written permission of Samsung Electronics.
 *
 */

#ifndef __DECON_H__
#define __DECON_H__

enum decon_trig_mode {
    DECON_HW_TRIG = 0,
    DECON_SW_TRIG
};

enum decon_psr_mode {
    DECON_VIDEO_MODE = 0,
    DECON_DP_PSR_MODE = 1,
    DECON_MIPI_COMMAND_MODE = 2,
};

enum decon_set_trig {
    DECON_TRIG_DISABLE = 0,
    DECON_TRIG_ENABLE
};

struct decon_mode_info {
    enum decon_psr_mode psr_mode;
    enum decon_trig_mode trig_mode;
};

/* Porter Duff Compositing Operators */
enum decon_win_func {
    PD_FUNC_CLEAR = 0x0,
    PD_FUNC_COPY = 0x1,
    PD_FUNC_DESTINATION = 0x2,
    PD_FUNC_SOURCE_OVER = 0x3,
    PD_FUNC_DESTINATION_OVER = 0x4,
    PD_FUNC_SOURCE_IN = 0x5,
    PD_FUNC_DESTINATION_IN = 0x6,
    PD_FUNC_SOURCE_OUT = 0x7,
    PD_FUNC_DESTINATION_OUT = 0x8,
    PD_FUNC_SOURCE_A_TOP = 0x9,
    PD_FUNC_DESTINATION_A_TOP = 0xa,
    PD_FUNC_XOR = 0xb,
    PD_FUNC_PLUS = 0xc,
    PD_FUNC_USER_DEFINED = 0xd,
};

enum decon_pixel_format {
    /* RGB 8bit display */
    /* 4byte */
    DECON_PIXEL_FORMAT_ARGB_8888 = 0,
    DECON_PIXEL_FORMAT_ABGR_8888,
    DECON_PIXEL_FORMAT_RGBA_8888,
    DECON_PIXEL_FORMAT_BGRA_8888,
    DECON_PIXEL_FORMAT_XRGB_8888,
    DECON_PIXEL_FORMAT_XBGR_8888,
    DECON_PIXEL_FORMAT_RGBX_8888,
    DECON_PIXEL_FORMAT_BGRX_8888,
    /* 2byte */
    DECON_PIXEL_FORMAT_RGBA_5551,
    DECON_PIXEL_FORMAT_BGRA_5551,
    DECON_PIXEL_FORMAT_ABGR_4444,
    DECON_PIXEL_FORMAT_RGBA_4444,
    DECON_PIXEL_FORMAT_BGRA_4444,
    DECON_PIXEL_FORMAT_RGB_565,
    DECON_PIXEL_FORMAT_BGR_565,

    /* RGB 10bit display */
    /* 4byte */
    DECON_PIXEL_FORMAT_ARGB_2101010,
    DECON_PIXEL_FORMAT_ABGR_2101010,
    DECON_PIXEL_FORMAT_RGBA_1010102,
    DECON_PIXEL_FORMAT_BGRA_1010102,

    /* YUV 8bit display */
    /* YUV422 2P */
    DECON_PIXEL_FORMAT_NV16,
    DECON_PIXEL_FORMAT_NV61,
    /* YUV422 3P */
    DECON_PIXEL_FORMAT_YVU422_3P,
    /* YUV420 2P */
    DECON_PIXEL_FORMAT_NV12,
    DECON_PIXEL_FORMAT_NV21,
    DECON_PIXEL_FORMAT_NV12M,
    DECON_PIXEL_FORMAT_NV21M,
    /* YUV420 3P */
    DECON_PIXEL_FORMAT_YUV420,
    DECON_PIXEL_FORMAT_YVU420,
    DECON_PIXEL_FORMAT_YUV420M,
    DECON_PIXEL_FORMAT_YVU420M,
    /* YUV - 2 planes but 1 buffer */
    DECON_PIXEL_FORMAT_NV12N,
    DECON_PIXEL_FORMAT_NV12N_10B,

    /* YUV 10bit display */
    /* YUV420 2P */
    DECON_PIXEL_FORMAT_NV12M_P010,
    DECON_PIXEL_FORMAT_NV21M_P010,

    /* YUV420(P8+2) 4P */
    DECON_PIXEL_FORMAT_NV12M_S10B,
    DECON_PIXEL_FORMAT_NV21M_S10B,

    /* YUV422 2P */
    DECON_PIXEL_FORMAT_NV16M_P210,
    DECON_PIXEL_FORMAT_NV61M_P210,

    /* YUV422(P8+2) 4P */
    DECON_PIXEL_FORMAT_NV16M_S10B,
    DECON_PIXEL_FORMAT_NV61M_S10B,

    DECON_PIXEL_FORMAT_NV12_P010,

    /* formats for lossless SBWC case */
    DECON_PIXEL_FORMAT_NV12M_SBWC_8B,
    DECON_PIXEL_FORMAT_NV12M_SBWC_10B,
    DECON_PIXEL_FORMAT_NV21M_SBWC_8B,
    DECON_PIXEL_FORMAT_NV21M_SBWC_10B,
    DECON_PIXEL_FORMAT_NV12N_SBWC_8B,
    DECON_PIXEL_FORMAT_NV12N_SBWC_10B,
    DECON_PIXEL_FORMAT_MAX,
};

enum decon_win_alpha_coef {
    BND_COEF_ZERO = 0x0,
    BND_COEF_ONE = 0x1,
    BND_COEF_AF = 0x2,
    BND_COEF_1_M_AF = 0x3,
    BND_COEF_AB = 0x4,
    BND_COEF_1_M_AB = 0x5,
    BND_COEF_PLNAE_ALPHA0 = 0x6,
    BND_COEF_1_M_PLNAE_ALPHA0 = 0x7,
    BND_COEF_PLNAE_ALPHA1 = 0x8,
    BND_COEF_1_M_PLNAE_ALPHA1 = 0x9,
    BND_COEF_ALPHA_MULT = 0xA,
    BND_COEF_1_M_ALPHA_MULT = 0xB,
};

enum decon_win_alpha_sel {
    ALPHA_MULT_SRC_SEL_ALPHA0 = 0,
    ALPHA_MULT_SRC_SEL_ALPHA1 = 1,
    ALPHA_MULT_SRC_SEL_AF = 2,
    ALPHA_MULT_SRC_SEL_AB = 3,
};

enum decon_blending {
    DECON_BLENDING_NONE = 0,
    DECON_BLENDING_PREMULT = 1,
    DECON_BLENDING_COVERAGE = 2,
    DECON_BLENDING_MAX = 3,
};

enum decon_idma_type {
    IDMA_G0 = 0,
    IDMA_G1,
    IDMA_VG0,
    IDMA_VG1,
    IDMA_VGF0,
    IDMA_VGF1, /* VGRF in case of Exynos9810 */
    MAX_DECON_DMA_TYPE,
};

#define IDMA_GF0    IDMA_G0
#define IDMA_GF1    IDMA_G1
#define IDMA_VG     IDMA_VG0
#define IDMA_VGF    IDMA_VG1
#define IDMA_VGS    IDMA_VGF0
#define IDMA_VGRFS  IDMA_VGF1

struct decon_window_regs {
    uint32_t wincon;
    uint32_t start_pos;
    uint32_t end_pos;
    uint32_t colormap;
    uint32_t start_time;
    uint32_t pixel_count;
    uint32_t whole_w;
    uint32_t whole_h;
    uint32_t offset_x;
    uint32_t offset_y;
    uint32_t winmap_state;
    uint32_t type;
    int plane_alpha;
    uint32_t format;
    uint32_t blend;
};

/********** EXTERNAL FUNCTION: H/W access API **********/
void tui_decon_init(uint32_t width, uint32_t height);
int tui_decon_ready(uint32_t fb_addr);
int tui_decon_oneshot(void);
void tui_decon_deinit(void);

#endif /* __DECON_H__ */