/* * * Copyright (c) 2012-2019, Samsung Electronics Co., Ltd. * http://www.samsung.com * * Register definition file for Samsung dpp driver * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __DPP_REGS_H__ #define __DPP_REGS_H__ /* * DPU_DMA SFR base address : 0x14890000 * - GLOBAL : 0x14890000 * - IDMA GF0(L0) : 0x14891000 * - IDMA GF1(L1) : 0x14892000 * - IDMA VG(L2) : 0x14893000 * - IDMA VGS(L3) : 0x14894000 */ #define DPU_DMA_VERSION 0x0000 #define DPU_DMA_VER 0x05000000 #define DPU_DMA_QCH_EN 0x000C #define DMA_QCH_EN (1 << 0) #define DPU_DMA_SWRST 0x0010 #define DMA_CH2_SWRST (1 << 3) #define DMA_CH1_SWRST (1 << 2) #define DMA_CH0_SWRST (1 << 1) #define DMA_ALL_SWRST (1 << 0) #define DMA_CH_SWRST(_ch) (1 << ((_ch))) #define DPU_DMA_TEST_PATTERN0_3 0x0020 #define DPU_DMA_TEST_PATTERN0_2 0x0024 #define DPU_DMA_TEST_PATTERN0_1 0x0028 #define DPU_DMA_TEST_PATTERN0_0 0x002C #define DPU_DMA_TEST_PATTERN1_3 0x0030 #define DPU_DMA_TEST_PATTERN1_2 0x0034 #define DPU_DMA_TEST_PATTERN1_1 0x0038 #define DPU_DMA_TEST_PATTERN1_0 0x003C #define DPU_DMA_GLB_CGEN_CH0 0x0040 #define DMA_SFR_CGEN(_v) ((_v) << 31) #define DMA_SFR_CGEN_MASK (1U << 31) #define DMA_INT_CGEN(_v) ((_v) << 0) #define DMA_INT_CGEN_MASK (0x7FFFFFFF << 0) #define DPU_DMA_GLB_CGEN_CH1 0x0044 #define DMA_INT_CGEN(_v) ((_v) << 0) #define DMA_INT_CGEN_MASK (0x7FFFFFFF << 0) #define DPU_DMA_GLB_CGEN_CH2 0x0048 #define DMA_INT_CGEN(_v) ((_v) << 0) #define DMA_INT_CGEN_MASK (0x7FFFFFFF << 0) #define DPU_DMA_DEBUG_CONTROL 0x0100 #define DPU_DMA_DEBUG_CONTROL_SEL(_v) ((_v) << 16) #define DPU_DMA_DEBUG_CONTROL_EN (0x1 << 0) #define DPU_DMA_DEBUG_DATA 0x0104 /* * 1.1 - IDMA Register * < DMA.offset > * G0 G1 VG VGS VGF VGRFS * 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 */ #define IDMA_ENABLE 0x0000 #define IDMA_ASSIGNED_MO(_v) ((_v) << 24) #define IDMA_ASSIGNED_MO_MASK (0xffu << 24) #define IDMA_SRESET (1 << 8) #define IDMA_SFR_UPDATE_FORCE (1 << 4) #define IDMA_OP_STATUS (1 << 2) #define OP_STATUS_IDLE (0) #define OP_STATUS_BUSY (1) #define IDMA_INSTANT_OFF_PENDING (1 << 1) #define INSTANT_OFF_PENDING (1) #define INSTANT_OFF_NOT_PENDING (0) #define IDMA_IRQ 0x0004 /* [9630] AXI_ADDR_ERR_IRQ is added */ #define IDMA_AXI_ADDR_ERR_IRQ (1 << 26) #define IDMA_AFBC_CONFLICT_IRQ (1 << 25) #define IDMA_VR_CONFLICT_IRQ (1 << 24) #define IDMA_SBWC_ERR_IRQ (1 << 23) #define IDMA_RECOVERY_TRG_IRQ (1 << 22) #define IDMA_CONFIG_ERROR (1 << 21) #define IDMA_LOCAL_HW_RESET_DONE (1 << 20) #define IDMA_READ_SLAVE_ERROR (1 << 19) #define IDMA_STATUS_DEADLOCK_IRQ (1 << 17) #define IDMA_STATUS_FRAMEDONE_IRQ (1 << 16) #define IDMA_ALL_IRQ_CLEAR (0x7FB << 16) /* [9630] AXI_ADDR_ERR_IRQ_MASK is added */ #define IDMA_AXI_ADDR_ERR_IRQ_MASK (1 << 11) #define IDMA_AFBC_CONFLICT_MASK (1 << 10) #define IDMA_VR_CONFLICT_MASK (1 << 9) #define IDMA_SBWC_ERR_MASK (1 << 8) #define IDMA_RECOVERY_TRG_MASK (1 << 7) #define IDMA_CONFIG_ERROR_MASK (1 << 6) #define IDMA_LOCAL_HW_RESET_DONE_MASK (1 << 5) #define IDMA_READ_SLAVE_ERROR_MASK (1 << 4) #define IDMA_IRQ_DEADLOCK_MASK (1 << 2) #define IDMA_IRQ_FRAMEDONE_MASK (1 << 1) #define IDMA_ALL_IRQ_MASK (0x7FB << 1) #define IDMA_IRQ_ENABLE (1 << 0) #define IDMA_IN_CON 0x0008 #define IDMA_PIXEL_ALPHA(_v) ((_v) << 24) #define IDMA_PIXEL_ALPHA_MASK (0xffu << 24) #define IDMA_IN_IC_MAX(_v) ((_v) << 16) #define IDMA_IN_IC_MAX_MASK (0xff << 16) #define IDMA_SBWC_LOSSY_EN (1 << 14) #define IDMA_IMG_FORMAT(_v) ((_v) << 8) #define IDMA_IMG_FORMAT_MASK (0x3f << 8) #define IDMA_IMG_FORMAT_ARGB8888 (0) #define IDMA_IMG_FORMAT_ABGR8888 (1) #define IDMA_IMG_FORMAT_RGBA8888 (2) #define IDMA_IMG_FORMAT_BGRA8888 (3) #define IDMA_IMG_FORMAT_XRGB8888 (4) #define IDMA_IMG_FORMAT_XBGR8888 (5) #define IDMA_IMG_FORMAT_RGBX8888 (6) #define IDMA_IMG_FORMAT_BGRX8888 (7) #define IDMA_IMG_FORMAT_RGB565 (8) #define IDMA_IMG_FORMAT_BGR565 (9) #define IDMA_IMG_FORMAT_ARGB1555 (12) #define IDMA_IMG_FORMAT_ARGB4444 (13) #define IDMA_IMG_FORMAT_ABGR1555 (14) #define IDMA_IMG_FORMAT_ABGR4444 (15) #define IDMA_IMG_FORMAT_ARGB2101010 (16) #define IDMA_IMG_FORMAT_ABGR2101010 (17) #define IDMA_IMG_FORMAT_RGBA1010102 (18) #define IDMA_IMG_FORMAT_BGRA1010102 (19) #define IDMA_IMG_FORMAT_RGBA5551 (20) #define IDMA_IMG_FORMAT_RGBA4444 (21) #define IDMA_IMG_FORMAT_BGRA5551 (22) #define IDMA_IMG_FORMAT_BGRA4444 (23) #define IDMA_IMG_FORMAT_YUV420_2P (24) #define IDMA_IMG_FORMAT_YVU420_2P (25) #define IDMA_IMG_FORMAT_YUV420_8P2 (26) #define IDMA_IMG_FORMAT_YVU420_8P2 (27) #define IDMA_IMG_FORMAT_YUV420_P010 (29) #define IDMA_IMG_FORMAT_YVU420_P010 (28) #define IDMA_IMG_FORMAT_YVU422_2P (56) #define IDMA_IMG_FORMAT_YUV422_2P (57) #define IDMA_IMG_FORMAT_YVU422_8P2 (58) #define IDMA_IMG_FORMAT_YUV422_8P2 (59) #define IDMA_IMG_FORMAT_YVU422_P210 (60) #define IDMA_IMG_FORMAT_YUV422_P210 (61) #define IDMA_ROTATION(_v) ((_v) << 4) #define IDMA_ROTATION_MASK (0x7 << 4) #define IDMA_ROTATION_X_FLIP (1 << 4) #define IDMA_ROTATION_Y_FLIP (2 << 4) #define IDMA_ROTATION_180 (3 << 4) #define IDMA_ROTATION_90 (4 << 4) #define IDMA_ROTATION_90_X_FLIP (5 << 4) #define IDMA_ROTATION_90_Y_FLIP (6 << 4) #define IDMA_ROTATION_270 (7 << 4) #define IDMA_IN_FLIP(_v) ((_v) << 4) #define IDMA_IN_FLIP_MASK (0x3 << 4) /* #define IDMA_CSET_EN (1 << 3) */ #define IDMA_SBWC_EN (1 << 2) #define IDMA_AFBC_EN (1 << 1) #define IDMA_BLOCK_EN (1 << 0) #define IDMA_SRC_SIZE 0x0010 #define IDMA_SRC_HEIGHT(_v) ((_v) << 16) #define IDMA_SRC_HEIGHT_MASK (0xFFFF << 16) #define IDMA_SRC_WIDTH(_v) ((_v) << 0) #define IDMA_SRC_WIDTH_MASK (0xFFFF << 0) #define IDMA_SRC_OFFSET 0x0014 #define IDMA_SRC_OFFSET_Y(_v) ((_v) << 16) #define IDMA_SRC_OFFSET_Y_MASK (0x3FFF << 16) #define IDMA_SRC_OFFSET_X(_v) ((_v) << 0) #define IDMA_SRC_OFFSET_X_MASK (0x3FFF << 0) #define IDMA_IMG_SIZE 0x0018 #define IDMA_IMG_HEIGHT(_v) ((_v) << 16) #define IDMA_IMG_HEIGHT_MASK (0x3FFF << 16) #define IDMA_IMG_WIDTH(_v) ((_v) << 0) #define IDMA_IMG_WIDTH_MASK (0x3FFF << 0) #define IDMA_BLOCK_OFFSET 0x0020 #define IDMA_BLK_OFFSET_Y(_v) ((_v) << 16) #define IDMA_BLK_OFFSET_Y_MASK (0x3FFF << 16) #define IDMA_BLK_OFFSET_X(_v) ((_v) << 0) #define IDMA_BLK_OFFSET_X_MASK (0x3FFF << 0) #define IDMA_BLOCK_SIZE 0x0024 #define IDMA_BLK_HEIGHT(_v) ((_v) << 16) #define IDMA_BLK_HEIGHT_MASK (0x3FFF << 16) #define IDMA_BLK_WIDTH(_v) ((_v) << 0) #define IDMA_BLK_WIDTH_MASK (0x3FFF << 0) #define IDMA_IN_BASE_ADDR_Y8 0x0040 #define IDMA_IN_BASE_ADDR_C8 0x0044 #define IDMA_IN_BASE_ADDR_Y2 0x0048 #define IDMA_IN_BASE_ADDR_C2 0x004C #define IDMA_SRC_STRIDE_0 0x0050 #define IDMA_PLANE_3_STRIDE_SEL (1 << 23) #define IDMA_PLANE_2_STRIDE_SEL (1 << 22) #define IDMA_PLANE_1_STRIDE_SEL (1 << 21) #define IDMA_PLANE_0_STRIDE_SEL (1 << 20) #define IDMA_PLANE_STRIDE_SEL(_v) ((_v) << 20) #define IDMA_PLANE_STRIDE_SEL_MASK (0xF << 20) #define IDMA_CHROM_STRIDE_SEL (1 << 16) #define IDMA_CHROM_STRIDE(_v) ((_v) << 0) #define IDMA_CHROM_STRIDE_MASK (0xFFFF << 0) #define IDMA_SRC_STRIDE_1 0x0054 #define IDMA_PLANE_1_STRIDE(_v) ((_v) << 16) #define IDMA_PLANE_1_STRIDE_MASK (0xffff << 16) #define IDMA_PLANE_0_STRIDE(_v) ((_v) << 0) #define IDMA_PLANE_0_STRIDE_MASK (0xffff << 0) #define IDMA_SRC_STRIDE_2 0x0058 #define IDMA_PLANE_3_STRIDE(_v) ((_v) << 16) #define IDMA_PLANE_3_STRIDE_MASK (0xffff << 16) #define IDMA_PLANE_2_STRIDE(_v) ((_v) << 0) #define IDMA_PLANE_2_STRIDE_MASK (0xffff << 0) /* [9630] SWBC_PARAM is added */ #define IDMA_SBWC_PARAM 0x0064 #define IDMA_SBWC_CRC_EN (1 << 16) #define IDMA_CHM_LOSSY_BYTENUM(_v) ((_v) << 8) #define IDMA_CHM_LOSSY_BYTENUM_MASK (0xf << 8) #define IDMA_LUM_LOSSY_BYTENUM(_v) ((_v) << 4) #define IDMA_LUM_LOSSY_BYTENUM_MASK (0xf << 4) #define IDMA_CHM_BLK_SIZE(_v) ((_v) << 2) #define IDMA_CHM_BLK_SIZE_MASK (0x3 << 2) #define IDMA_CHM_BLK_SIZE_32_4 (0) #define IDMA_CHM_BLK_SIZE_16_8 (1) #define IDMA_CHM_BLK_SIZE_64_4 (2) #define IDMA_LUM_BLK_SIZE(_v) ((_v) << 0) #define IDMA_LUM_BLK_SIZE_MASK (0x3 << 0) #define IDMA_LUM_BLK_SIZE_16_16 (0) #define IDMA_LUM_BLK_SIZE_32_8 (1) #define IDMA_LUM_BLK_SIZE_64_4 (2) #define IDMA_RECOVERY_CTRL 0x0070 #define IDMA_RECOVERY_NUM(_v) ((_v) << 1) #define IDMA_RECOVERY_NUM_MASK (0x7fffffff << 1) #define IDMA_RECOVERY_EN (1 << 0) /* [9630] IDMA_DEADLOCK_NUM -> IDMA_DEADLOCK_EN */ #define IDMA_DEADLOCK_EN 0x0100 #define IDMA_DEADLOCK_TIMER(_v) ((_v) << 1) #define IDMA_DEADLOCK_TIMER_MASK (0x7fffffff << 1) #define IDMA_DEADLOCK_TIMER_EN (1 << 0) #define IDMA_BUS_CON 0x0110 /* [9630] IDMA_CACHE_CON is added */ #define IDMA_CACHE_CON 0x0114 #define IDMA_DATA_SAHRE_TYPE_P3(_v) ((_v) << 28) #define IDMA_DATA_SAHRE_TYPE_P3_MASK (0x3 << 28) #define IDMA_LLC_HINT_P3(_v) ((_v) << 24) #define IDMA_LLC_HINT_P3_MASK (0x7 << 24) #define IDMA_DATA_SAHRE_TYPE_P2(_v) ((_v) << 20) #define IDMA_DATA_SAHRE_TYPE_P2_MASK (0x3 << 20) #define IDMA_LLC_HINT_P2(_v) ((_v) << 16) #define IDMA_LLC_HINT_P2_MASK (0x7 << 16) #define IDMA_DATA_SAHRE_TYPE_P1(_v) ((_v) << 12) #define IDMA_DATA_SAHRE_TYPE_P1_MASK (0x3 << 12) #define IDMA_LLC_HINT_P1(_v) ((_v) << 8) #define IDMA_LLC_HINT_P1_MASK (0x7 << 8) #define IDMA_DATA_SAHRE_TYPE_P0(_v) ((_v) << 4) #define IDMA_DATA_SAHRE_TYPE_P0_MASK (0x3 << 4) #define IDMA_LLC_HINT_P0(_v) ((_v) << 0) #define IDMA_LLC_HINT_P0_MASK (0x7 << 0) /* [9630] IDMA_PERFORMANCE_CON is added at each layer */ #define IDMA_PERFORMANCE_CON 0x0120 #define IDMA_DEGRADATION_TIME(_v) ((_v) << 16) #define IDMA_DEGRADATION_TIME_MASK (0xFFFF << 16) #define IDMA_IN_IC_MAX_DEG(_v) ((_v) << 4) #define IDMA_IN_IC_MAX_DEG_MASK (0xFF << 4) #define IDMA_DEGRADATION_EN (1 << 0) /* [9630] IDMA_QOS_LUT is added at each layer */ /* _n: [0,7], _v: [0x0, 0xF] */ #define IDMA_QOS_LUT07_00 0x0130 #define IDMA_QOS_LUT15_08 0x0134 #define IDMA_QOS_LUT(_n, _v) ((_v) << (4*(_n))) #define IDMA_QOS_LUT_MASK(_n) (0xF << (4*(_n))) #define IDMA_DYNAMIC_GATING_EN 0x0140 #define IDMA_SRAM_CG_EN (1U << 31) #define IDMA_DG_EN(_n, _v) ((_v) << (_n)) #define IDMA_DG_EN_MASK(_n) (1 << (_n)) #define IDMA_DG_EN_ALL (0x7FFFFFFF << 0) #define IDMA_MST_SECURITY 0x0200 #define IDMA_SLV_SECURITY 0x0204 #define IDMA_SECURE_MASK (0x1 << 0) #define IDMA_DEBUG_CONTROL 0x0300 #define IDMA_DEBUG_CONTROL_SEL(_v) ((_v) << 16) #define IDMA_DEBUG_CONTROL_EN (0x1 << 0) #define IDMA_DEBUG_DATA 0x0304 /* 0: AXI, 3: Pattern */ #define IDMA_IN_REQ_DEST 0x0308 #define IDMA_IN_REG_DEST_SEL(_v) ((_v) << 0) #define IDMA_IN_REG_DEST_SEL_MASK (0x3 << 0) /* [9630] IDMA_PSLV_ERR_CTRL is added */ #define IDMA_PSLV_ERR_CTRL 0x030c #define IDMA_PSLVERR_CTRL (1 << 0) /* [9630] IDMA_DEBUG_ADDR_Y/C is added */ #define IDMA_DEBUG_ADDR_Y8 0x0310 #define IDMA_DEBUG_ADDR_C8 0x0314 #define IDMA_DEBUG_ADDR_Y2 0x0318 #define IDMA_DEBUG_ADDR_C2 0x031C /* [9630] IDMA_DEBUG_ADDR_CTRL is added */ #define IDMA_DEBUG_ADDR_CTRL 0x0320 #define IDMA_DBG_EN_ADDR_C2 (1 << 3) #define IDMA_DBG_EN_ADDR_Y2 (1 << 2) #define IDMA_DBG_EN_ADDR_C8 (1 << 1) #define IDMA_DBG_EN_ADDR_Y8 (1 << 0) #define IDMA_CFG_ERR_STATE 0x0b30 #define IDMA_CFG_ERR_ROTATION (1 << 21) #define IDMA_CFG_ERR_IMG_HEIGHT_ROTATION (1 << 20) #define IDMA_CFG_ERR_AFBC (1 << 18) #define IDMA_CFG_ERR_SBWC (1 << 17) #define IDMA_CFG_ERR_BLOCK (1 << 16) #define IDMA_CFG_ERR_FORMAT (1 << 15) #define IDMA_CFG_ERR_STRIDE3 (1 << 14) #define IDMA_CFG_ERR_STRIDE2 (1 << 13) #define IDMA_CFG_ERR_STRIDE1 (1 << 12) #define IDMA_CFG_ERR_STRIDE0 (1 << 11) #define IDMA_CFG_ERR_CHROM_STRIDE (1 << 10) #define IDMA_CFG_ERR_BASE_ADDR_C2 (1 << 9) #define IDMA_CFG_ERR_BASE_ADDR_Y2 (1 << 8) #define IDMA_CFG_ERR_BASE_ADDR_C8 (1 << 7) #define IDMA_CFG_ERR_BASE_ADDR_Y8 (1 << 6) #define IDMA_CFG_ERR_SRC_OFFSET_Y (1 << 5) #define IDMA_CFG_ERR_SRC_OFFSET_X (1 << 4) #define IDMA_CFG_ERR_IMG_HEIGHT (1 << 3) #define IDMA_CFG_ERR_IMG_WIDTH (1 << 2) #define IDMA_CFG_ERR_SRC_HEIGHT (1 << 1) #define IDMA_CFG_ERR_SRC_WIDTH (1 << 0) #define IDMA_CFG_ERR_GET(_v) (((_v) >> 0) & 0x3FFFFF) /* * DPP SFR base address : 0x19040000 * - DPP GF0(L0) : 0x19041000 * - DPP GF1(L1) : 0x19042000 #define DMA_SHD_OFFSET 0x800 * - DPP VG(L2) : 0x19043000 * - DPP VGF(L3) : 0x19044000 * - DPP VGS(L4) : 0x19045000 * - DPP VGRFS(L5) : 0x19046000 */ #define DPP_ENABLE 0x0000 #define DPP_SRSET (1 << 24) #define DPP_HDR_SEL (0 << 11) #define DPP_SFR_CLOCK_GATE_EN (1 << 10) #define DPP_SRAM_CLOCK_GATE_EN (1 << 9) #define DPP_INT_CLOCK_GATE_EN (1 << 8) #define DPP_ALL_CLOCK_GATE_EN_MASK (0x7 << 8) #define DPP_PSLVERR_EN (1 << 5) #define DPP_SFR_UPDATE_FORCE (1 << 4) #define DPP_QCHANNEL_EN (1 << 3) #define DPP_OP_STATUS (1 << 2) #define DPP_TZPC_FLAG (1 << 0) #define DPP_IRQ 0x0004 #define DPP_CONFIG_ERROR (1 << 21) #define DPP_FRAMEDONE_IRQ (1 << 16) #define DPP_ALL_IRQ_CLEAR (0x21 << 16) #define DPP_CONFIG_ERROR_MASK (1 << 6) #define DPP_FRAMEDONE_IRQ_MASK (1 << 1) #define DPP_ALL_IRQ_MASK (0x21 << 1) #define DPP_IRQ_ENABLE (1 << 0) #define DPP_IN_CON 0x0008 #define DPP_CSC_TYPE(_v) ((_v) << 18) #define DPP_CSC_TYPE_MASK (3 << 18) #define DPP_CSC_RANGE(_v) ((_v) << 17) #define DPP_CSC_RANGE_MASK (1 << 17) #define DPP_CSC_MODE(_v) ((_v) << 16) #define DPP_CSC_MODE_MASK (1 << 16) #define DPP_DEPREMULTIPLY_EN (1 << 7) #define DPP_PREMULTIPLY_EN (1 << 6) #define DPP_DITH_MASK_SEL (1 << 5) #define DPP_DITH_MASK_SPIN (1 << 4) #define DPP_ALPHA_SEL(_v) ((_v) << 3) #define DPP_ALPHA_SEL_MASK (1 << 3) #define DPP_IMG_FORMAT(_v) ((_v) << 0) #define DPP_IMG_FORMAT_MASK (0x7 << 0) #define DPP_IMG_FORMAT_ARGB8888 (0 << 0) #define DPP_IMG_FORMAT_ARGB8101010 (1 << 0) #define DPP_IMG_FORMAT_YUV420_8P (2 << 0) #define DPP_IMG_FORMAT_YUV420_P010 (3 << 0) #define DPP_IMG_FORMAT_YUV420_8P2 (4 << 0) /* [9820] 3 kinds of YUV422 formats are added to DPP format */ #define DPP_IMG_FORMAT_YUV422_8P (5 << 0) #define DPP_IMG_FORMAT_YUV422_P210 (6 << 0) #define DPP_IMG_FORMAT_YUV422_8P2 (7 << 0) #define DPP_IMG_SIZE 0x0018 #define DPP_IMG_HEIGHT(_v) ((_v) << 16) #define DPP_IMG_HEIGHT_MASK (0x1FFF << 16) #define DPP_IMG_WIDTH(_v) ((_v) << 0) #define DPP_IMG_WIDTH_MASK (0x1FFF << 0) /* scaler configuration only */ #define DPP_SCALED_IMG_SIZE 0x002C #define DPP_SCALED_IMG_HEIGHT(_v) ((_v) << 16) #define DPP_SCALED_IMG_HEIGHT_MASK (0x1FFF << 16) #define DPP_SCALED_IMG_WIDTH(_v) ((_v) << 0) #define DPP_SCALED_IMG_WIDTH_MASK (0x1FFF << 0) /* * (00-01-02) : Reg0.L-Reg0.H-Reg1.L * (10-11-12) : Reg1.H-Reg2.L-Reg2.H * (20-21-22) : Reg3.L-Reg3.H-Reg4.L */ #define DPP_CSC_COEF0 0x0030 #define DPP_CSC_COEF1 0x0034 #define DPP_CSC_COEF2 0x0038 #define DPP_CSC_COEF3 0x003C #define DPP_CSC_COEF4 0x0040 #define DPP_CSC_COEF_H(_v) ((_v) << 16) #define DPP_CSC_COEF_H_MASK (0xFFFF << 16) #define DPP_CSC_COEF_L(_v) ((_v) << 0) #define DPP_CSC_COEF_L_MASK (0xFFFF << 0) #define DPP_CSC_COEF_XX(_n, _v) ((_v) << (0 + (16 * (_n)))) #define DPP_CSC_COEF_XX_MASK(_n) (0xFFF << (0 + (16 * (_n)))) #define DPP_MAIN_H_RATIO 0x0044 #define DPP_H_RATIO(_v) ((_v) << 0) #define DPP_H_RATIO_MASK (0xFFFFFF << 0) #define DPP_MAIN_V_RATIO 0x0048 #define DPP_V_RATIO(_v) ((_v) << 0) #define DPP_V_RATIO_MASK (0xFFFFFF << 0) #define DPP_Y_VCOEF_0A 0x0200 #define DPP_Y_HCOEF_0A 0x0290 #define DPP_C_VCOEF_0A 0x0400 #define DPP_C_HCOEF_0A 0x0490 #define DPP_SCL_COEF(_v) ((_v) << 0) #define DPP_SCL_COEF_MASK (0x7FF << 0) #define DPP_H_COEF(n, s, x) (0x290 + (n) * 0x4 + (s) * 0x24 + (x) * 0x200) #define DPP_V_COEF(n, s, x) (0x200 + (n) * 0x4 + (s) * 0x24 + (x) * 0x200) #define DPP_YHPOSITION 0x05B0 #define DPP_YVPOSITION 0x05B4 #define DPP_CHPOSITION 0x05B8 #define DPP_CVPOSITION 0x05BC #define DPP_POS_I(_v) ((_v) << 20) #define DPP_POS_I_MASK (0xFFF << 20) #define DPP_POS_I_GET(_v) (((_v) >> 20) & 0xFFF) #define DPP_POS_F(_v) ((_v) << 0) #define DPP_POS_F_MASK (0xFFFFF << 0) #define DPP_POS_F_GET(_v) (((_v) >> 0) & 0xFFFFF) /* 0x0A00 ~ 0x0A1C : ASHE */ #define DPP_DYNAMIC_GATING_EN 0x0A54 #define DPP_DG_EN(_n, _v) ((_v) << (_n)) #define DPP_DG_EN_MASK(_n) (1 << (_n)) #define DPP_DG_EN_ALL (0x5F << 0) #define DPP_LINECNT_CON 0x0D00 #define DPP_LC_CAPTURE(_v) ((_v) << 2) #define DPP_LC_CAPTURE_MASK (1 << 2) #define DPP_LC_MODE(_V) ((_V) << 1) #define DPP_LC_MODE_MASK (1 << 1) #define DPP_LC_ENABLE(_v) ((_v) << 0) #define DPP_LC_ENABLE_MASK (1 << 0) #define DPP_LINECNT_VAL 0x0D04 #define DPP_LC_COUNTER(_v) ((_v) << 0) #define DPP_LC_COUNTER_MASK (0x1FFF << 0) #define DPP_LC_COUNTER_GET(_v) (((_v) >> 0) & 0x1FFF) #define DPP_CFG_ERR_STATE 0x0D08 #define DPP_CFG_ERR_SCL_POS (1 << 4) #define DPP_CFG_ERR_SCALE_RATIO (1 << 3) #define DPP_CFG_ERR_ODD_SIZE (1 << 2) #define DPP_CFG_ERR_MAX_SIZE (1 << 1) #define DPP_CFG_ERR_MIN_SIZE (1 << 0) #define DPP_CFG_ERR_GET(_v) (((_v) >> 0) & 0x1F) #endif /* __DPP_REGS_H__ */