/* * * Register definition file for Samsung DECON driver * * Copyright (c) 2012-2019, Samsung Electronics * Sewoon Park * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef _REGS_DECON_H #define _REGS_DECON_H /* * [ BLK_DPU BASE ADDRESS ] * * - CMU_DPU 0x1600_0000 * - SYSREG_DPU 0x1601_0000 * - DPP 0x1602_0000 * - DECON0 0x1603_0000 * - DECON1 0x1604_0000 * - DECON2 0x1605_0000 * - DPU_DMA 0x1607_0000 * - MIPI_DSIM0 0x1608_0000 * - MIPI_DSIM1 0x1609_0000 * - BTM_DPUD0 0x1613_0000 * - BTM_DPUD1 0x1614_0000 * - BTM_DPUD2 0x1615_0000 * - SYSMMU_DPUD0 0x160A_0000 * - SYSMMU_DPUD1 0x160B_0000 * - SYSMMU_DPUD2 0x160C_0000 * - SYSMMU_DPUD0_S 0x160D_0000 * - SYSMMU_DPUD1_S 0x160E_0000 * - SYSMMU_DPUD2_S 0x160F_0000 * - PPMU_DPUD0 0x1610_0000 * - PPMU_DPUD1 0x1611_0000 * - PPMU_DPUD2 0x1612_0000 * - DCPHY_TOP_M4S4 0x1616_0000 * - DCPHY_MODULE_M4S4 0x1617_0000 */ /* * IP start_offset end_offset *================================================= * DECON 0x0000 0x0fff * BLENDER 0x1000 0x1fff *------------------------------------------------- * DSC0 0x4000 0x4fff * DSC1 0x5000 0x5fff * DSC2 0x6000 0x6fff *------------------------------------------------- * SHD_DECON 0x7000 0x7FFF *------------------------------------------------- * SHD_BLENDER 0x8000 0x8FFF *------------------------------------------------- * SHD_DSC0 0xB000 0xBFFF * SHD_DSC1 0xC000 0xCFFF * SHD_DSC2 0xD000 0xCFFF *------------------------------------------------- */ /* * DECON registers * -> * updated by SHADOW_REG_UPDATE_REQ[31] : SHADOW_REG_UPDATE_REQ * (0x0000~0x011C, 0x0230~0x209C ) */ #define GLOBAL_CONTROL 0x0000 #define GLOBAL_CONTROL_SRESET (1 << 28) #define GLOBAL_CONTROL_PSLVERR_EN (1 << 24) #define GLOBAL_CONTROL_TEN_BPC_MODE_F (1 << 20) #define GLOBAL_CONTROL_TEN_BPC_MODE_MASK (1 << 20) #define GLOBAL_CONTROL_MASTER_MODE_F(_v) ((_v) << 12) #define GLOBAL_CONTROL_MASTER_MODE_MASK (0xF << 12) #define GLOBAL_CONTROL_OPERATION_MODE_F (1 << 8) #define GLOBAL_CONTROL_OPERATION_MODE_VIDEO_F (0 << 8) #define GLOBAL_CONTROL_OPERATION_MODE_CMD_F (1 << 8) #define GLOBAL_CONTROL_IDLE_STATUS (1 << 5) #define GLOBAL_CONTROL_RUN_STATUS (1 << 4) #define GLOBAL_CONTROL_DECON_EN (1 << 1) #define GLOBAL_CONTROL_DECON_EN_F (1 << 0) #define INTERRUPT_ENABLE 0x0040 #define DPU_FRAME_DONE_INT_EN (1 << 13) #define DPU_FRAME_START_INT_EN (1 << 12) #define DPU_UNDER_FLOW_INT_EN (1 << 8) #define DPU_EXTRA_INT_EN (1 << 4) #define DPU_INT_EN (1 << 0) #define INTERRUPT_ENABLE_MASK 0x3111 #define EXTRA_INTERRUPT_ENABLE 0x0044 #define DPU_RESOURCE_CONFLICT_INT_EN (1 << 8) #define DPU_TIME_OUT_INT_EN (1 << 4) #define INTERRUPT_PENDING 0x004C #define DPU_FRAME_DONE_INT_PEND (1 << 13) #define DPU_FRAME_START_INT_PEND (1 << 12) #define DPU_EXTRA_INT_PEND (1 << 4) #define EXTRA_INTERRUPT_PENDING 0x0050 #define DPU_RESOURCE_CONFLICT_INT_PEND (1 << 8) #define DPU_TIME_OUT_INT_PEND (1 << 4) #define SHADOW_REG_UPDATE_REQ 0x0060 #define SHADOW_REG_UPDATE_REQ_GLOBAL (1U << 31) #define SHADOW_REG_UPDATE_REQ_WIN(_win) (1 << (_win)) #define SHADOW_REG_UPDATE_REQ_FOR_DECON (0x3f) #define HW_SW_TRIG_CONTROL 0x0070 #define HW_TRIG_SEL(_v) ((_v) << 24) #define HW_TRIG_SEL_MASK (0x3 << 24) #define HW_TRIG_SEL_FROM_DDI1 (1 << 24) #define HW_TRIG_SEL_FROM_DDI0 (0 << 24) #define HW_TRIG_SKIP(_v) ((_v) << 16) #define HW_TRIG_SKIP_MASK (0xff << 16) #define HW_TRIG_ACTIVE_VALUE (1 << 13) #define HW_TRIG_EDGE_POLARITY (1 << 12) #define SW_TRIG_EN (1 << 8) #define HW_TRIG_MASK_DECON (1 << 4) #define HW_SW_TRIG_TIMER_CLEAR (1 << 3) #define HW_SW_TRIG_TIMER_EN (1 << 2) #define HW_TRIG_EN (1 << 0) #define DATA_PATH_CONTROL_0 0x0214 #define WIN_MAPCOLOR_EN_F(_win) (1 << (4*_win + 1)) #define WIN_EN_F(_win) (1 << (4*_win + 0)) #define DATA_PATH_CONTROL_1 0x0218 #define WIN_CHMAP_F(_win, _ch) (((_ch) & 0x7) << (4*_win)) #define WIN_CHMAP_MASK(_win) (0x7 << (4*_win)) /* BLENDER */ #define WIN_CONTROL_0(_win) (0x1000 + ((_win) * 0x30)) #define WIN_ALPHA1_F(_v) (((_v) & 0xFF) << 24) #define WIN_ALPHA1_MASK (0xFFU << 24) #define WIN_ALPHA0_F(_v) (((_v) & 0xFF) << 16) #define WIN_ALPHA0_MASK (0xFF << 16) #define WIN_ALPHA_GET(_v, _n) (((_v) >> (16 + 8 * (_n))) & 0xFF) #define WIN_FUNC_F(_v) (((_v) & 0xF) << 8) #define WIN_FUNC_MASK (0xF << 8) #define WIN_FUNC_GET(_v) (((_v) >> 8) & 0xf) #define WIN_SRESET (1 << 4) #define WIN_ALPHA_MULT_SRC_SEL_F(_v) (((_v) & 0x3) << 0) #define WIN_ALPHA_MULT_SRC_SEL_MASK (0x3 << 0) #define WIN_CONTROL_1(_win) (0x1004 + ((_win) * 0x30)) #define WIN_FG_ALPHA_D_SEL_F(_v) (((_v) & 0xF) << 24) #define WIN_FG_ALPHA_D_SEL_MASK (0xF << 24) #define WIN_BG_ALPHA_D_SEL_F(_v) (((_v) & 0xF) << 16) #define WIN_BG_ALPHA_D_SEL_MASK (0xF << 16) #define WIN_FG_ALPHA_A_SEL_F(_v) (((_v) & 0xF) << 8) #define WIN_FG_ALPHA_A_SEL_MASK (0xF << 8) #define WIN_BG_ALPHA_A_SEL_F(_v) (((_v) & 0xF) << 0) #define WIN_BG_ALPHA_A_SEL_MASK (0xF << 0) #define WIN_START_POSITION(_win) (0x1008 + ((_win) * 0x30)) #define WIN_STRPTR_Y_F(_v) (((_v) & 0x3FFF) << 16) #define WIN_STRPTR_X_F(_v) (((_v) & 0x3FFF) << 0) #define WIN_END_POSITION(_win) (0x100C + ((_win) * 0x30)) #define WIN_ENDPTR_Y_F(_v) (((_v) & 0x3FFF) << 16) #define WIN_ENDPTR_X_F(_v) (((_v) & 0x3FFF) << 0) #define WIN_START_TIME_CONTROL(_win) (0x1018 + ((_win) * 0x30)) #define WIN_START_TIME_CONTROL_F(_v) ((_v) << 0) #define WIN_START_TIME_CONTROL_MASK (0x3fff << 0) #endif /* _REGS_DECON_H */