/* * * Copyright (c) 2012-2019, Samsung Electronics Co., Ltd. * http://www.samsung.com * * Register definition file for Samsung dpp driver * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __DPP_REGS_H__ #define __DPP_REGS_H__ /* * DPU_DMA SFR base address : 0x19070000 * - GLOBAL : 0x19070000 * - IDMA GF0 : 0x19071000 * - IDMA GF1 : 0x19072000 * - IDMA VG : 0x19073000 * - IDMA VGS : 0x19074000 * - IDMA VGF : 0x19075000 * - IDMA VGRFS : 0x19076000 * - ODMA : 0x19077000 */ #define DPU_DMA_SWRST 0x0010 #define DMA_CH2_SWRST (1 << 3) #define DMA_CH1_SWRST (1 << 2) #define DMA_CH0_SWRST (1 << 1) #define DMA_ALL_SWRST (1 << 0) #define DMA_CH_SWRST(_ch) (1 << ((_ch))) /* _n: [0,7], _v: [0x0, 0xF] */ #define DPU_DMA_QOS_LUT07_00 0x0070 #define DPU_DMA_QOS_LUT15_08 0x0074 #define DPU_DMA_QOS_LUT(_n, _v) ((_v) << (4*(_n))) #define DPU_DMA_QOS_LUT_MASK(_n) (0xF << (4*(_n))) /* * 1.1 - IDMA Register * < DMA.offset > * G0 G1 VG0 VG1 VGF0 VGRF * 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 */ #define IDMA_ENABLE 0x0000 #define IDMA_SRESET (1 << 24) #define IDMA_SRAM_CLOCK_GATE_EN (1 << 9) #define IDMA_ALL_CLOCK_GATE_EN_MASK (0x1 << 9) #define IDMA_SFR_UPDATE_FORCE (1 << 4) #define IDMA_OP_STATUS (1 << 2) #define OP_STATUS_IDLE (0) #define OP_STATUS_BUSY (1) #define IDMA_INSTANT_OFF_PENDING (1 << 1) #define INSTANT_OFF_PENDING (1) #define INSTANT_OFF_NOT_PENDING (0) #define IDMA_IRQ 0x0004 /* [9820] AFBC_CONFLICT_IRQ is added */ #define IDMA_AFBC_CONFLICT_IRQ (1 << 25) /* [9820] MO_CONFLICT_IRQ -> VR_CONFLICT_IRQ */ #define IDMA_VR_CONFLICT_IRQ (1 << 24) #define IDMA_AFBC_TIMEOUT_IRQ (1 << 23) #define IDMA_RECOVERY_START_IRQ (1 << 22) #define IDMA_CONFIG_ERROR (1 << 21) #define IDMA_LOCAL_HW_RESET_DONE (1 << 20) #define IDMA_READ_SLAVE_ERROR (1 << 19) #define IDMA_STATUS_DEADLOCK_IRQ (1 << 17) #define IDMA_STATUS_FRAMEDONE_IRQ (1 << 16) #define IDMA_ALL_IRQ_CLEAR (0x3FB << 16) /* [9820] AFBC_CONFLICT_IRQ_MASK is added */ #define IDMA_AFBC_CONFLICT_MASK (1 << 10) /* [9820] MO_CONFLICT_IRQ_MASK -> VR_CONFLICT_IRQ_MASK */ #define IDMA_VR_CONFLICT_MASK (1 << 9) #define IDMA_AFBC_TIMEOUT_MASK (1 << 8) #define IDMA_RECOVERY_START_MASK (1 << 7) #define IDMA_CONFIG_ERROR_MASK (1 << 6) #define IDMA_LOCAL_HW_RESET_DONE_MASK (1 << 5) #define IDMA_READ_SLAVE_ERROR_MASK (1 << 4) #define IDMA_IRQ_DEADLOCK_MASK (1 << 2) #define IDMA_IRQ_FRAMEDONE_MASK (1 << 1) #define IDMA_ALL_IRQ_MASK (0x3FB << 1) #define IDMA_IRQ_ENABLE (1 << 0) #define IDMA_IN_CON 0x0008 #define IDMA_VR_MODE_EN (1U << 31) #define IDMA_IN_IC_MAX(_v) ((_v) << 19) #define IDMA_IN_IC_MAX_MASK (0xff << 19) #define IDMA_IMG_FORMAT(_v) ((_v) << 11) #define IDMA_IMG_FORMAT_MASK (0x3f << 11) #define IDMA_IMG_FORMAT_ARGB8888 (0) #define IDMA_IMG_FORMAT_ABGR8888 (1) #define IDMA_IMG_FORMAT_RGBA8888 (2) #define IDMA_IMG_FORMAT_BGRA8888 (3) #define IDMA_IMG_FORMAT_XRGB8888 (4) #define IDMA_IMG_FORMAT_XBGR8888 (5) #define IDMA_IMG_FORMAT_RGBX8888 (6) #define IDMA_IMG_FORMAT_BGRX8888 (7) #define IDMA_IMG_FORMAT_RGB565 (8) #define IDMA_IMG_FORMAT_BGR565 (9) #define IDMA_IMG_FORMAT_ARGB1555 (12) #define IDMA_IMG_FORMAT_ARGB4444 (13) #define IDMA_IMG_FORMAT_ARGB2101010 (16) #define IDMA_IMG_FORMAT_ABGR2101010 (17) #define IDMA_IMG_FORMAT_RGBA2101010 (18) #define IDMA_IMG_FORMAT_BGRA2101010 (19) #define IDMA_IMG_FORMAT_YUV420_2P (24) #define IDMA_IMG_FORMAT_YVU420_2P (25) #define IDMA_IMG_FORMAT_YUV420_8P2 (26) #define IDMA_IMG_FORMAT_YVU420_8P2 (27) #define IDMA_IMG_FORMAT_YUV420_P010 (29) #define IDMA_IMG_FORMAT_YVU420_P010 (28) /* [9820] Below IDMA formats are added */ #define IDMA_IMG_FORMAT_YVU422_2P (56) #define IDMA_IMG_FORMAT_YUV422_2P (57) #define IDMA_IMG_FORMAT_YVU422_8P2 (58) #define IDMA_IMG_FORMAT_YUV422_8P2 (59) #define IDMA_IMG_FORMAT_YVU422_P210 (60) #define IDMA_IMG_FORMAT_YUV422_P210 (61) #define IDMA_ROTATION(_v) ((_v) << 8) #define IDMA_ROTATION_MASK (7 << 8) #define IDMA_ROTATION_X_FLIP (1 << 8) #define IDMA_ROTATION_Y_FLIP (2 << 8) #define IDMA_ROTATION_180 (3 << 8) #define IDMA_ROTATION_90 (4 << 8) #define IDMA_ROTATION_90_X_FLIP (5 << 8) #define IDMA_ROTATION_90_Y_FLIP (6 << 8) #define IDMA_ROTATION_270 (7 << 8) #define IDMA_IN_FLIP(_v) ((_v) << 8) #define IDMA_IN_FLIP_MASK (0x3 << 8) #define IDMA_AFBC_EN (1 << 7) #define IDMA_AFBC_TO_EN (1 << 6) #define IDMA_IN_CHROMINANCE_STRIDE_SEL (1 << 4) #define IDMA_BLOCK_EN (1 << 3) #define IDMA_OUT_CON 0x000C #define IDMA_OUT_FRAME_ALPHA(_v) ((_v) << 24) #define IDMA_OUT_FRAME_ALPHA_MASK (0xffu << 24) #define IDMA_SRC_SIZE 0x0010 #define IDMA_SRC_HEIGHT(_v) ((_v) << 16) #define IDMA_SRC_HEIGHT_MASK (0x3FFF << 16) #define IDMA_SRC_WIDTH(_v) ((_v) << 0) #define IDMA_SRC_WIDTH_MASK (0xFFFF << 0) #define IDMA_SRC_OFFSET 0x0014 #define IDMA_SRC_OFFSET_Y(_v) ((_v) << 16) #define IDMA_SRC_OFFSET_Y_MASK (0x1FFF << 16) #define IDMA_SRC_OFFSET_X(_v) ((_v) << 0) #define IDMA_SRC_OFFSET_X_MASK (0x1FFF << 0) #define IDMA_IMG_SIZE 0x0018 #define IDMA_IMG_HEIGHT(_v) ((_v) << 16) #define IDMA_IMG_HEIGHT_MASK (0x1FFF << 16) #define IDMA_IMG_WIDTH(_v) ((_v) << 0) #define IDMA_IMG_WIDTH_MASK (0x1FFF << 0) #define IDMA_IN_BASE_ADDR_Y 0x0040 #define IDMA_IN_BASE_ADDR_C 0x0044 #define IDMA_IN_BASE_ADDR_Y2 0x0048 #define IDMA_IN_BASE_ADDR_C2 0x004C #define IDMA_DYNAMIC_GATING_EN 0x0058 #define IDMA_DG_EN(_n, _v) ((_v) << (_n)) #define IDMA_DG_EN_MASK(_n) (1 << (_n)) #define IDMA_DG_EN_ALL (0x7FFFFFF << 0) /* * DPP SFR base address : 0x19020000 * - DPP GF0 : 0x19021000 * - DPP GF1 : 0x19022000 * - DPP VG : 0x19023000 * - DPP VGF : 0x19024000 * - DPP VGS : 0x19025000 * - DPP VGRFS : 0x19026000 */ #define DPP_ENABLE 0x0000 #define DPP_SRSET (1 << 24) #define DPP_HDR_SEL (1 << 11) #define DPP_SFR_CLOCK_GATE_EN (1 << 10) #define DPP_SRAM_CLOCK_GATE_EN (1 << 9) #define DPP_INT_CLOCK_GATE_EN (1 << 8) #define DPP_ALL_CLOCK_GATE_EN_MASK (0x7 << 8) #define DPP_PSLVERR_EN (1 << 5) #define DPP_SFR_UPDATE_FORCE (1 << 4) #define DPP_QCHANNEL_EN (1 << 3) #define DPP_OP_STATUS (1 << 2) #define DPP_TZPC_FLAG (1 << 0) #define DPP_IRQ 0x0004 #define DPP_CONFIG_ERROR (1 << 21) #define DPP_STATUS_FRAMEDONE_IRQ (1 << 16) #define DPP_ALL_IRQ_CLEAR (0x21 << 16) #define DPP_CONFIG_ERROR_MASK (1 << 6) #define DPP_IRQ_FRAMEDONE_MASK (1 << 1) #define DPP_ALL_IRQ_MASK (0x21 << 1) #define DPP_IRQ_ENABLE (1 << 0) #define DPP_IN_CON 0x0008 #define DPP_CSC_TYPE(_v) ((_v) << 18) #define DPP_CSC_TYPE_MASK (3 << 18) #define DPP_CSC_RANGE(_v) ((_v) << 17) #define DPP_CSC_RANGE_MASK (1 << 17) #define DPP_CSC_MODE(_v) ((_v) << 16) #define DPP_CSC_MODE_MASK (1 << 16) #define DPP_DITH_MASK_SEL (1 << 5) #define DPP_DITH_MASK_SPIN (1 << 4) #define DPP_ALPHA_SEL(_v) ((_v) << 3) #define DPP_ALPHA_SEL_MASK (1 << 3) #define DPP_IMG_FORMAT(_v) ((_v) << 0) #define DPP_IMG_FORMAT_MASK (0x7 << 0) #define DPP_IMG_FORMAT_ARGB8888 (0 << 0) #define DPP_IMG_FORMAT_ARGB8101010 (1 << 0) #define DPP_IMG_FORMAT_YUV420_8P (2 << 0) #define DPP_IMG_FORMAT_YUV420_P010 (3 << 0) #define DPP_IMG_FORMAT_YUV420_8P2 (4 << 0) /* [9820] 3 kinds of YUV422 formats are added to DPP format */ #define DPP_IMG_FORMAT_YUV422_8P (5 << 0) #define DPP_IMG_FORMAT_YUV422_P210 (6 << 0) #define DPP_IMG_FORMAT_YUV422_8P2 (7 << 0) #define DPP_IMG_SIZE 0x0018 #define DPP_IMG_HEIGHT(_v) ((_v) << 16) #define DPP_IMG_HEIGHT_MASK (0x1FFF << 16) #define DPP_IMG_WIDTH(_v) ((_v) << 0) #define DPP_IMG_WIDTH_MASK (0x1FFF << 0) #define DPP_MAIN_H_RATIO 0x0044 #define DPP_H_RATIO(_v) ((_v) << 0) #define DPP_H_RATIO_MASK (0xFFFFFF << 0) #define DPP_MAIN_V_RATIO 0x0048 #define DPP_V_RATIO(_v) ((_v) << 0) #define DPP_V_RATIO_MASK (0xFFFFFF << 0) #define DPP_H_COEF(n, s, x) (0x290 + (n) * 0x4 + (s) * 0x24 + (x) * 0x200) #define DPP_V_COEF(n, s, x) (0x200 + (n) * 0x4 + (s) * 0x24 + (x) * 0x200) #define DPP_DYNAMIC_GATING_EN 0x0A54 #define DPP_DG_EN(_n, _v) ((_v) << (_n)) #define DPP_DG_EN_MASK(_n) (1 << (_n)) #define DPP_DG_EN_ALL (0x7F << 0) #define DPP_LINECNT_CON 0x0D00 #define DPP_LC_CAPTURE(_v) ((_v) << 2) #define DPP_LC_CAPTURE_MASK (1 << 2) #define DPP_LC_MODE(_V) ((_V) << 1) #define DPP_LC_MODE_MASK (1 << 1) #define DPP_LC_ENABLE(_v) ((_v) << 0) #define DPP_LC_ENABLE_MASK (1 << 0) #endif /* __DPP_REGS_H__ */