#ifndef __SOC_H__
#define __SOC_H__

/* SOC REV */
#define SOCREV_BASE 			0x10000000
#define CHIPID_REV 			0x10
#define MAIN_REVISION_BIT 		20
#define MAIN_REVISION_MASK 		(0xF << MAIN_REVISION_BIT)
#define SOCREV_SIZE 			0x20

/* DECON */
#define SEC_DECON_ID			0

#define DECON_MAIN_BASE 		0x19F00000
#define DECON_WIN_BASE 			0x19F10000
#define DECON_SUB_BASE 			0x19F20000
#define DECON_WINCON_BASE 		0x19F30000
#define DECON_SRAMC_D_BASE_EVT0 	0x19D58000
#define DECON_SRAMC_D_BASE_EVT1 	0x1AD58000
#define DECON_SRAMC_D1_BASE 		0x1AF58000

#define DECON_MAIN_SIZE 		0xFFFF
#define DECON_WIN_SIZE 			0xFFFF
#define DECON_SUB_SIZE 			0xFFFF
#define DECON_WINCON_SIZE 		0xFFFF
#define DECON_SRAMC_D_SIZE 		0x1000
#define DECON_SRAMC_D1_SIZE 		0x1000

/* DSIM */
#define SEC_DSIM_ID			0

#define MIPI_DSIM0_BASE 		0x19EB0000
#define MIPI_DCPHY_M4M4_BASE 		0x19EE0100
#define MIPI_DCPHY_M4M4_BIAS_BASE 	0x19EE0000
#define SYSREG_DPU_BASE 		0x19E21000

#define PMU_ALIVE_BASE 			0x15860000
#define PHY_CTRL_MIPI_DCPHY_M4M4	0x0714
#define PHY_ISO_BIT_POS			0x0

#define DSIM_BASE 			MIPI_DSIM0_BASE
#define DPHY_BASE 			MIPI_DCPHY_M4M4_BASE
#define DPHY_EXTRA_BASE 		MIPI_DCPHY_M4M4_BIAS_BASE
#define DPHY_ISO_CONTROL 		(PMU_ALIVE_BASE + PHY_CTRL_MIPI_DCPHY_M4M4)

#define DSIM_SIZE 			0x300
#define DPHY_SIZE 			0x700
#define DPHY_EXTRA_SIZE 		0x100
#define SYSREG_SIZE 			0x10
#define DPHY_ISO_SIZE			0x10

/* DPP */
#define SEC_DPP_ID			0

#define IDMA_L0_BASE_EVT0 		0x19D00000
#define DPP_L0_BASE_EVT0 		0x19D30000
#define SRAMC_L0_BASE_EVT0 		0x19D50000
#define VOTF_L0_BASE_EVT0 		0x19D20000
#define SCL_COEF_L0_BASE_EVT0 		0x19D40000
#define HDR_COMM_L0_BASE_EVT0 		0x19D60000
#define DPP_DEBUG_L0_BASE_EVT0 		0x19D3F000
#define IDMA_L0_BASE_EVT1 		0x1AD00000
#define DPP_L0_BASE_EVT1 		0x1AD30000
#define SRAMC_L0_BASE_EVT1 		0x1AD50000
#define VOTF_L0_BASE_EVT1 		0x1AD20000
#define SCL_COEF_L0_BASE_EVT1 		0x1AD40000
#define HDR_COMM_L0_BASE_EVT1 		0x1AD60000
#define DPP_DEBUG_L0_BASE_EVT1 		0x1AD3F000
#define IDMA_L8_BASE 			0x1AF00000
#define DPP_L8_BASE 			0x1AF30000
#define SRAMC_L8_BASE 			0x1AF50000
#define VOTF_L8_BASE 			0x1AF20000
#define SCL_COEF_L8_BASE 		0x1AF40000
#define HDR_COMM_L8_BASE 		0x1AF60000
#define DPP_DEBUG_L8_BASE 		0x1AF3F000

#define IDMA_SIZE 			0x1000
#define DPP_SIZE 			0x1000
#define SRAMC_SIZE 			0x1000
#define VOTF_SIZE 			0x1000
#define SCL_COEF_SIZE 			0x4000
#define HDR_COMM_SIZE 			0x1000
#define DPP_DEBUG_SIZE 			0x1000

#define IDMA_BASE(id, rev) 		((id < 8) ? (((rev == 0) ? IDMA_L0_BASE_EVT0 : IDMA_L0_BASE_EVT1) + (id) * IDMA_SIZE)	\
						: (IDMA_L8_BASE + (id - 8) * IDMA_SIZE))
#define DPP_BASE(id, rev) 		((id < 8) ? (((rev == 0) ? DPP_L0_BASE_EVT0 : DPP_L0_BASE_EVT1) + (id) * DPP_SIZE)	\
						: (DPP_L8_BASE + (id - 8) * DPP_SIZE))
#define SRAMC_BASE(id, rev) 		((id < 8) ? (((rev == 0) ? SRAMC_L0_BASE_EVT0 : SRAMC_L0_BASE_EVT1) + (id) * SRAMC_SIZE) \
						: (SRAMC_L8_BASE + (id - 8) * SRAMC_SIZE))
#define VOTF_BASE(id, rev) 		((id < 8) ? ((rev == 0) ? IDMA_L0_BASE_EVT0 : IDMA_L0_BASE_EVT1) : (IDMA_L8_BASE))
#define SCL_COEF_BASE(id, rev) 		((id < 8) ? ((rev == 0) ? SCL_COEF_L0_BASE_EVT0 : SCL_COEF_L0_BASE_EVT1) : (SCL_COEF_L8_BASE))
#define HDR_COMM_BASE(id, rev) 		((id < 8) ? (((rev == 0) ? HDR_COMM_L0_BASE_EVT0 : HDR_COMM_L0_BASE_EVT1) + (id) * HDR_COMM_SIZE) \
						: (HDR_COMM_L8_BASE + (id - 8) * HDR_COMM_SIZE))
#define DPP_DEBUG_BASE(id, rev) 	((id == 0) ? ((rev == 0) ? DPP_DEBUG_L0_BASE_EVT0 : DPP_DEBUG_L0_BASE_EVT1) : (DPP_DEBUG_L8_BASE)) /* id = (0 or 8) */

#define DPP0_ATTR_EVT0 			0x1D0004
#define DPP1_ATTR_EVT0 			0x1D043C
#define DPP2_ATTR_EVT0 			0x1D0004
#define DPP3_ATTR_EVT0 			0x1D0014
#define DPP4_ATTR_EVT0 			0x1D0004
#define DPP5_ATTR_EVT0 			0x1D0434
#define DPP6_ATTR_EVT0 			0x1D0004
#define DPP7_ATTR_EVT0 			0x1D0014
#define DPP8_ATTR_EVT0 			0x1D0004
#define DPP9_ATTR_EVT0 			0x1D043C
#define DPP10_ATTR_EVT0 		0x1D0004
#define DPP11_ATTR_EVT0 		0x1D0014
#define DPP12_ATTR_EVT0 		0x1D0004
#define DPP13_ATTR_EVT0 		0x1D0434
#define DPP14_ATTR_EVT0 		0x1D0004
#define DPP15_ATTR_EVT0 		0x1D0014

#define DPP0_ATTR_EVT1 			0x1D0004
#define DPP1_ATTR_EVT1 			0x1D043D
#define DPP2_ATTR_EVT1 			0x1D0004
#define DPP3_ATTR_EVT1 			0x1D0015
#define DPP4_ATTR_EVT1 			0x1D0004
#define DPP5_ATTR_EVT1 			0x1D0435
#define DPP6_ATTR_EVT1 			0x1D0004
#define DPP7_ATTR_EVT1 			0x1D0015
#define DPP8_ATTR_EVT1 			0x1D0004
#define DPP9_ATTR_EVT1 			0x1D043D
#define DPP10_ATTR_EVT1 		0x1D0004
#define DPP11_ATTR_EVT1 		0x1D0015
#define DPP12_ATTR_EVT1 		0x1D0004
#define DPP13_ATTR_EVT1 		0x1D0435
#define DPP14_ATTR_EVT1 		0x1D0004
#define DPP15_ATTR_EVT1 		0x1D0015

#define DPP_ATTR(rev)			((rev == 0) ? DPP0_ATTR_EVT0 : DPP0_ATTR_EVT1)

#endif /* __SOC_H__ */