/** * @file rtic_sfr.h * @brief Defines RTIC SFR address, and control macro * * Copyright (c) 2014 Samsung Electronics Co., Ltd. * * This software is proprietary of Samsung Electronics. * No part of this software, either material or conceptual may be copied * or distributed, transmitted, transcribed, stored in a retrieval system * or translated into any human or computer language in any form by any means, * electronic, mechanical, manual or otherwise, or disclosed to third parties * without the express written permission of Samsung Electronics. */ #ifndef __RTIC_SFR_H__ #define __RTIC_SFR_H__ #ifdef __cplusplus extern "C" { #endif /****************************************************** Base Address & Interrupt *******************************************************/ /* Address mapping for SFR */ #if defined(CONFIG_SMDK3250) || defined(CONFIG_SMDK5433) || defined(CONFIG_SMDK7420) || defined(CONFIG_SMDK8890) || defined(CONFIG_SMDK5430) || defined(CONFIG_SMDK3470) #define RTIC_CLK_PHY_BASE 0x11060000 #define RTIC_SFR_PHY_BASE 0x11150000 #elif defined(CONFIG_SMDK7580) || defined(CONFIG_SMDK3475) #define RTIC_CLK_PHY_BASE 0x10C60000 #define RTIC_SFR_PHY_BASE 0x10CC0000 #elif defined(CONFIG_SMDK7870) || defined(CONFIG_SMDK7880) || defined(CONFIG_SMDK7570) #define RTIC_CLK_PHY_BASE 0x13730000 #define RTIC_SFR_PHY_BASE 0x134C0000 #elif defined(CONFIG_SMDK8895) || defined(CONFIG_SMDK9810) #define RTIC_SFR_PHY_BASE 0x11630000 #elif defined(CONFIG_SMDK7885) #define RTIC_SFR_PHY_BASE 0x13480000 #endif #ifdef USE_SCRYPTO #define RTIC_CLK_VER_BASE 0xF0000 #define RTIC_SFR_VER_BASE 0xF1000 #else #define RTIC_CLK_VER_BASE 0xA0000 #define RTIC_SFR_VER_BASE 0xA1000 #endif #if defined(CONFIG_SMDK5433) #define IRQ_INFEEDCTRL_RTIC 348 #elif defined(CONFIG_SMDK7420) #define IRQ_INFEEDCTRL_RTIC 348 #elif defined(CONFIG_SMDK7580) #define IRQ_INFEEDCTRL_RTIC 348 #elif defined(CONFIG_SMDK3475) #define IRQ_INFEEDCTRL_RTIC 348 #elif defined(CONFIG_SMDK8890) #define CONFIG_RTIC_USE_HWACG #define IRQ_INFEEDCTRL_RTIC 497 #elif defined(CONFIG_SMDK7870) || defined(CONFIG_SMDK7880) || defined(CONFIG_SMDK7570) #undef CONFIG_RTIC_USE_HWACG #define IRQ_INFEEDCTRL_RTIC 294 #elif defined(CONFIG_SMDK8895) #define CONFIG_RTIC_USE_HWACG #define IRQ_INFEEDCTRL_RTIC 380 #elif defined(CONFIG_SMDK7885) #define CONFIG_RTIC_USE_HWACG #define IRQ_INFEEDCTRL_RTIC 188 #elif defined(CONFIG_SMDK9810) #define CONFIG_RTIC_USE_HWACG #define IRQ_INFEEDCTRL_RTIC 289 #endif #if TBASE_API_LEVEL >= 5 #if defined(CONFIG_SMDK5433) #define RTIC_CLK_ADDR (0x0B14) #elif defined(CONFIG_SMDK7420) #define RTIC_ACLK_ADDR (0x0814) #define RTIC_PCLK_ADDR (0x090C) #elif defined(CONFIG_SMDK7580) #define RTIC_ACLK_ADDR (0x080C) #define RTIC_PCLK_ADDR (0x0908) #elif defined(CONFIG_SMDK3475) #define RTIC_ACLK_ADDR (0x0818) #define RTIC_PCLK_ADDR (0x080C) #elif defined(CONFIG_SMDK7870) || defined(CONFIG_SMDK7880) || defined(CONFIG_SMDK7570) #define RTIC_CLK_ADDR (0x0808) #endif #else #if defined(CONFIG_SMDK5433) #define RTIC_CLK_ADDR (RTIC_CLK_VER_BASE + 0x0B14) #elif defined(CONFIG_SMDK7420) #define RTIC_ACLK_ADDR (RTIC_CLK_VER_BASE + 0x0814) #define RTIC_PCLK_ADDR (RTIC_CLK_VER_BASE + 0x090C) #elif defined(CONFIG_SMDK7580) #define RTIC_ACLK_ADDR (RTIC_CLK_VER_BASE + 0x080C) #define RTIC_PCLK_ADDR (RTIC_CLK_VER_BASE + 0x0908) #elif defined(CONFIG_SMDK3475) #define RTIC_ACLK_ADDR (RTIC_CLK_VER_BASE + 0x0818) #define RTIC_PCLK_ADDR (RTIC_CLK_VER_BASE + 0x080C) #elif defined(CONFIG_SMDK7870) || defined(CONFIG_SMDK7880) || defined(CONFIG_SMDK7570) #define RTIC_CLK_ADDR (RTIC_CLK_VER_BASE + 0x0808) #endif #endif /* RTIC CLOCK - CLK_GATE_IP_FSYS */ #if defined(CONFIG_SMDK7870) || defined(CONFIG_SMDK7880) || defined(CONFIG_SMDK7570) #define RTIC_CLK_MASK (0 << 0) #define RTIC_CLK_PASS (3 << 0) #else #define RTIC_CLK_MASK (0 << 0) #define RTIC_CLK_PASS (1 << 0) #endif /****************************************************** SFR address *****************************************************/ #if TBASE_API_LEVEL >= 5 /* Command Register */ #define RTIC_COMMAND (0x00) /* Control Register */ #define RTIC_CONTROL (0x04) /* Status Register */ #define RTIC_STATUS (0x08) /* Timer Configuration Registers */ #define RTIC_ACCESS_TIMER (0x0C) #define RTIC_PERIOD_TIMER (0x10) /* DMA Configuration Registers */ #define RTIC_MEMA_ADDR (0x14) #define RTIC_MEMA_LEN (0x18) #define RTIC_MEMB_ADDR (0x1C) #define RTIC_MEMB_LEN (0x20) #define RTIC_MEMC_ADDR (0x24) #define RTIC_MEMC_LEN (0x28) #define RTIC_MEMD_ADDR (0x2C) #define RTIC_MEMD_LEN (0x30) #define RTIC_MEME_ADDR (0x34) #define RTIC_MEME_LEN (0x38) /* FIFO Configuration Registers */ #define RTIC_FIFO_CONTROL (0x3C) #define RTIC_FIFO_STATUS (0x40) #define RTIC_HASH_SWAP (0x44) /* HASH Value Registers */ #define RTIC_HASH_VALUE_1 (0x48) #define RTIC_HASH_VALUE_2 (0x4C) #define RTIC_HASH_VALUE_3 (0x50) #define RTIC_HASH_VALUE_4 (0x54) #define RTIC_HASH_VALUE_5 (0x58) #define RTIC_HASH_VALUE_6 (0x5C) #define RTIC_HASH_VALUE_7 (0x60) #define RTIC_HASH_VALUE_8 (0x64) #define RTIC_HASH_VALUE_9 (0x68) #define RTIC_HASH_VALUE_10 (0x6C) #define RTIC_HASH_VALUE_11 (0x70) #define RTIC_HASH_VALUE_12 (0x74) #define RTIC_HASH_VALUE_13 (0x78) #define RTIC_HASH_VALUE_14 (0x7C) #define RTIC_HASH_VALUE_15 (0x80) #define RTIC_HASH_VALUE_16 (0x84) #define RTIC_HASH_VALUE_17 (0x88) #define RTIC_HASH_VALUE_18 (0x8C) #define RTIC_HASH_VALUE_19 (0x90) #define RTIC_HASH_VALUE_20 (0x94) #define RTIC_HASH_VALUE_21 (0x98) #define RTIC_HASH_VALUE_22 (0x9C) #define RTIC_HASH_VALUE_23 (0xA0) #define RTIC_HASH_VALUE_24 (0xA4) #define RTIC_HASH_VALUE_25 (0xA8) /* Interrupt Controller Registers */ #define RTIC_INT_STATUS (0xB0) #define RTIC_INT_EN_SET (0xB4) #define RTIC_INT_PEND (0xB8) #else //TBASE_API_LEVEL >= 5 #define RTIC_OFFSET (RTIC_SFR_VER_BASE) //same as RTRIC_VER_BASE /* Command Register */ #define RTIC_COMMAND (RTIC_OFFSET + 0x00) /* Control Register */ #define RTIC_CONTROL (RTIC_OFFSET + 0x04) /* Status Register */ #define RTIC_STATUS (RTIC_OFFSET + 0x08) /* Timer Configuration Registers */ #define RTIC_ACCESS_TIMER (RTIC_OFFSET + 0x0C) #define RTIC_PERIOD_TIMER (RTIC_OFFSET + 0x10) /* DMA Configuration Registers */ #define RTIC_MEMA_ADDR (RTIC_OFFSET + 0x14) #define RTIC_MEMA_LEN (RTIC_OFFSET + 0x18) #define RTIC_MEMB_ADDR (RTIC_OFFSET + 0x1C) #define RTIC_MEMB_LEN (RTIC_OFFSET + 0x20) #define RTIC_MEMC_ADDR (RTIC_OFFSET + 0x24) #define RTIC_MEMC_LEN (RTIC_OFFSET + 0x28) #define RTIC_MEMD_ADDR (RTIC_OFFSET + 0x2C) #define RTIC_MEMD_LEN (RTIC_OFFSET + 0x30) #define RTIC_MEME_ADDR (RTIC_OFFSET + 0x34) #define RTIC_MEME_LEN (RTIC_OFFSET + 0x38) /* FIFO Configuration Registers */ #define RTIC_FIFO_CONTROL (RTIC_OFFSET + 0x3C) #define RTIC_FIFO_STATUS (RTIC_OFFSET + 0x40) #define RTIC_HASH_SWAP (RTIC_OFFSET + 0x44) /* HASH Value Registers */ #define RTIC_HASH_VALUE_1 (RTIC_OFFSET + 0x48) #define RTIC_HASH_VALUE_2 (RTIC_OFFSET + 0x4C) #define RTIC_HASH_VALUE_3 (RTIC_OFFSET + 0x50) #define RTIC_HASH_VALUE_4 (RTIC_OFFSET + 0x54) #define RTIC_HASH_VALUE_5 (RTIC_OFFSET + 0x58) #define RTIC_HASH_VALUE_6 (RTIC_OFFSET + 0x5C) #define RTIC_HASH_VALUE_7 (RTIC_OFFSET + 0x60) #define RTIC_HASH_VALUE_8 (RTIC_OFFSET + 0x64) #define RTIC_HASH_VALUE_9 (RTIC_OFFSET + 0x68) #define RTIC_HASH_VALUE_10 (RTIC_OFFSET + 0x6C) #define RTIC_HASH_VALUE_11 (RTIC_OFFSET + 0x70) #define RTIC_HASH_VALUE_12 (RTIC_OFFSET + 0x74) #define RTIC_HASH_VALUE_13 (RTIC_OFFSET + 0x78) #define RTIC_HASH_VALUE_14 (RTIC_OFFSET + 0x7C) #define RTIC_HASH_VALUE_15 (RTIC_OFFSET + 0x80) #define RTIC_HASH_VALUE_16 (RTIC_OFFSET + 0x84) #define RTIC_HASH_VALUE_17 (RTIC_OFFSET + 0x88) #define RTIC_HASH_VALUE_18 (RTIC_OFFSET + 0x8C) #define RTIC_HASH_VALUE_19 (RTIC_OFFSET + 0x90) #define RTIC_HASH_VALUE_20 (RTIC_OFFSET + 0x94) #define RTIC_HASH_VALUE_21 (RTIC_OFFSET + 0x98) #define RTIC_HASH_VALUE_22 (RTIC_OFFSET + 0x9C) #define RTIC_HASH_VALUE_23 (RTIC_OFFSET + 0xA0) #define RTIC_HASH_VALUE_24 (RTIC_OFFSET + 0xA4) #define RTIC_HASH_VALUE_25 (RTIC_OFFSET + 0xA8) /* Interrupt Controller Registers */ #define RTIC_INT_STATUS (RTIC_OFFSET + 0xB0) #define RTIC_INT_EN_SET (RTIC_OFFSET + 0xB4) #define RTIC_INT_PEND (RTIC_OFFSET + 0xB8) #endif //TBASE_API_LEVEL >= 5 /****************************************************** SFR control *****************************************************/ /* RTIC command */ #define RTIC_IDLE (0 << 0) #define RTIC_RUN (1 << 0) #define RTIC_SW_RESET (1 << 1) #define RTIC_HASH_ONCE_RUN (1 << 3) #define RTIC_HASH_ONCE_RUN_test (0 << 3) #define RTIC_RUNTIME_CON_DIS (0 << 4) #define RTIC_RUNTIME_CON_EN (1 << 4) /* RTIC FIFO control */ #define RTIC_DMA_SWAPA_OFF (0 << 0) #define RTIC_DMA_SWAPA_ON (1 << 0) #define RTIC_DMA_SWAPB_OFF (0 << 1) #define RTIC_DMA_SWAPB_ON (1 << 1) #define RTIC_DMA_SWAPC_OFF (0 << 2) #define RTIC_DMA_SWAPC_ON (1 << 2) #define RTIC_DMA_SWAPD_OFF (0 << 3) #define RTIC_DMA_SWAPD_ON (1 << 3) #define RTIC_DMA_SWAPE_OFF (0 << 4) #define RTIC_DMA_SWAPE_ON (1 << 4) #define RTIC_AXI_ENDIAN_MASK (3 << 5) #define RTIC_AXI_LITTLE_ENDIAN (0 << 5) #define RTIC_AXI_B_BIG_ENDIAN (1 << 5) #define RTIC_AXI_W_BIG_ENDIAN (2 << 5) /* RTIC control */ #define RTIC_HASH_ENGINE_MASK (3 << 1) #define RTIC_HASH_ENGINE_CON1 (0 << 1) #define RTIC_HASH_ENGINE_CON2 (1 << 1) #define RTIC_HASH_ENGINE_CON3 (2 << 1) #define RTIC_HASH_ENGINE_CON4 (3 << 1) #define RTIC_MEMA_OFF (0 << 3) #define RTIC_MEMA_ON (1 << 3) #define RTIC_MEMB_OFF (0 << 4) #define RTIC_MEMB_ON (1 << 4) #define RTIC_MEMC_OFF (0 << 5) #define RTIC_MEMC_ON (1 << 5) #define RTIC_MEMD_OFF (0 << 6) #define RTIC_MEMD_ON (1 << 6) #define RTIC_MEME_OFF (0 << 7) #define RTIC_MEME_ON (1 << 7) #define RTIC_PERIOD_TIMER_OFF (0 << 8) #define RTIC_PERIOD_TIMER_ON (1 << 8) #define RTIC_ACCESS_TIMER_OFF (0 << 9) #define RTIC_ACCESS_TIMER_ON (1 << 9) #define RTIC_MEMA_HASH_ONCE_OFF (0 << 10) #define RTIC_MEMA_HASH_ONCE_ON (1 << 10) #define RTIC_MEMB_HASH_ONCE_OFF (0 << 11) #define RTIC_MEMB_HASH_ONCE_ON (1 << 11) #define RTIC_MEMC_HASH_ONCE_OFF (0 << 12) #define RTIC_MEMC_HASH_ONCE_ON (1 << 12) #define RTIC_MEMD_HASH_ONCE_OFF (0 << 13) #define RTIC_MEMD_HASH_ONCE_ON (1 << 13) #define RTIC_MEME_HASH_ONCE_OFF (0 << 14) #define RTIC_MEME_HASH_ONCE_ON (1 << 14) /* RTIC status */ #define RTIC_DMA_IDLE (0 << 0) #define RTIC_DMA_BUSY (1 << 0) #define RTIC_REQ_PEND (2 << 0) #define RTIC_ACCESS_TIMER_MASK (3 << 2) #define RTIC_ACCESS_TIMER_IDLE (0 << 2) #define RTIC_ACCESS_TIMER_BUSY (1 << 2) #define RTIC_ACCESS_TIMER_WAIT (2 << 2) #define RTIC_PERIOD_TIMER_MASK (3 << 4) #define RTIC_PERIOD_TIMER_IDLE (0 << 4) #define RTIC_PERIOD_TIMER_BUSY (1 << 4) #define RTIC_PERIOD_TIMER_WAIT (2 << 4) #define RTIC_ENG_STAT_MASK (7 << 16) /* RTIC hash swap */ #define RTIC_HASH_SWAP_MASK (0x3FF << 0) #define RTIC_HASH_SWAP_ALL_ON (0x3FF << 0) #define RTIC_HASH_SWAPDOA_OFF (0 << 0) #define RTIC_HASH_SWAPDOA_ON (1 << 0) #define RTIC_HASH_SWAPDOB_OFF (0 << 1) #define RTIC_HASH_SWAPDOB_ON (1 << 1) #define RTIC_HASH_SWAPDOC_OFF (0 << 2) #define RTIC_HASH_SWAPDOC_ON (1 << 2) #define RTIC_HASH_SWAPDOD_OFF (0 << 3) #define RTIC_HASH_SWAPDOD_ON (1 << 3) #define RTIC_HASH_SWAPDOE_OFF (0 << 4) #define RTIC_HASH_SWAPDOE_ON (1 << 4) #define RTIC_HASH_SWAPDIA_OFF (0 << 5) #define RTIC_HASH_SWAPDIA_ON (1 << 5) #define RTIC_HASH_SWAPDIB_OFF (0 << 6) #define RTIC_HASH_SWAPDIB_ON (1 << 6) #define RTIC_HASH_SWAPDIC_OFF (0 << 7) #define RTIC_HASH_SWAPDIC_ON (1 << 7) #define RTIC_HASH_SWAPDID_OFF (0 << 8) #define RTIC_HASH_SWAPDID_ON (1 << 8) #define RTIC_HASH_SWAPDIE_OFF (0 << 9) #define RTIC_HASH_SWAPDIE_ON (1 << 9) /* RTIC interrupt - status */ #define RTIC_INT_HASH_MIS_NOT (0 << 0) #define RTIC_INT_HASH_MIS_DONE (1 << 0) #define RTIC_INT_HASH_ONCE_NOT (0 << 1) #define RTIC_INT_HASH_ONCE_DONE (1 << 1) /* RTIC interrupt - enable setting */ #define RTIC_INT_HASH_MIS_OFF (0 << 0) #define RTIC_INT_HASH_MIS_ON (1 << 0) #define RTIC_INT_HASH_ONCE_OFF (0 << 1) #define RTIC_INT_HASH_ONCE_ON (1 << 1) /* RTIC intterupt - pending setting */ #define RTIC_INT_PEND_HASH_MIS (1 << 0) #define RTIC_INT_PEND_HASH_ONCE (1 << 1) #ifdef __cplusplus } #endif #endif