#ifndef __BKSECAPP_FUSE_LOCATION_H #define __BKSECAPP_FUSE_LOCATION_H /* Define for OEM Spare Region (Spare region 26 onwards) */ /* The fuse address get from xbl */ #define SECURITY_CONTROL_BASE 0x00780000 #define SECURITY_CONTROL_CORE_REG_BASE (SECURITY_CONTROL_BASE + 0x00000000) #define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_LSB_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x00000660 + 0x10 * (n)) #define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW0_MSB_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x00000664 + 0x10 * (n)) #define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_LSB_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x00000668 + 0x10 * (n)) #define HWIO_QFPROM_RAW_OEM_SPARE_REGn_ROW1_MSB_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x0000066c + 0x10 * (n)) #define QFPROM_RAW_OEM_SPARE_REG_WARRANTY_BIT 28 // Spare Reg 28 Bit 0 #define QFPROM_RAW_OEM_SPARE_REG_MEM_ACC 28 // Spare Reg 28 Bit 0 /* Define for EK FUSE in OEM Spare Region */ #define QFPROM_RAW_OEM_SPARE_REG_EK_FUSE 28 #define EK_FUSE_SHFT 8 #define EK_FUSE_BMSK 0x3 #define EK_FUSE_DEV 0x1 #define EK_FUSE_FORCE_USER 0x2 /* DEV -> USER */ #define EK_FUSE_USER 0x3 /* Define for OEM Secure Boot Region */ #define HWIO_QFPROM_RAW_OEM_SEC_BOOT_ROWn_LSB_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x000005e8 + 0x8 * (n)) #define OEM_SECURE_BOOT1_PK_HASH_IN_FUSE (1 << 4) #define OEM_SECURE_BOOT1_AUTH_EN (1 << 5) #define OEM_SECURE_BOOT2_PK_HASH_IN_FUSE (1 << 12) #define OEM_SECURE_BOOT2_AUTH_EN (1 << 13) #define OEM_SECURE_BOOT3_PK_HASH_IN_FUSE (1 << 20) #define OEM_SECURE_BOOT3_AUTH_EN (1 << 21) #define OEM_SECURE_BOOT_BLOWN_ALL ( OEM_SECURE_BOOT1_PK_HASH_IN_FUSE | OEM_SECURE_BOOT1_AUTH_EN | \ OEM_SECURE_BOOT2_PK_HASH_IN_FUSE | OEM_SECURE_BOOT2_AUTH_EN | \ OEM_SECURE_BOOT3_PK_HASH_IN_FUSE | OEM_SECURE_BOOT3_AUTH_EN ) /* Define for RP Count */ #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000238) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000240) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000248) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000250) #define HWIO_QFPROM_RAW_ANTI_ROLLBACK_5_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x00000258) #define ANTI_ROLLBACK_XBL0_ADDRESS HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR #define ANTI_ROLLBACK_XBL0_BMSK (0xFFFFFFFF) #define ANTI_ROLLBACK_XBL0_SHFT (0) #define ANTI_ROLLBACK_XBL0_MAX (0x20) #define ANTI_ROLLBACK_XBL1_ADDRESS HWIO_QFPROM_RAW_ANTI_ROLLBACK_1_LSB_ADDR #define ANTI_ROLLBACK_XBL1_BMSK (0xFFFFFFFF) #define ANTI_ROLLBACK_XBL1_SHFT (0) #define ANTI_ROLLBACK_XBL1_MAX (0x20) #define ANTI_ROLLBACK_PIL_LSB_ADDRESS HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR #define ANTI_ROLLBACK_PIL_LSB_BMSK (0xFFFFFFFF) #define ANTI_ROLLBACK_PIL_LSB_SHFT (0) #define ANTI_ROLLBACK_PIL_LSB_MAX (0x20) #define ANTI_ROLLBACK_PIL_MSB_ADDRESS HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR #define ANTI_ROLLBACK_PIL_MSB_BMSK (0xFFFF00) #define ANTI_ROLLBACK_PIL_MSB_SHFT (8) #define ANTI_ROLLBACK_PIL_MSB_MAX (0x10) #define ANTI_ROLLBACK_TZ_ADDRESS HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR #define ANTI_ROLLBACK_TZ_BMSK (0x1FFFF) #define ANTI_ROLLBACK_TZ_SHFT (0) #define ANTI_ROLLBACK_TZ_MAX (0x11) #define ANTI_ROLLBACK_RPM_ADDRESS HWIO_QFPROM_RAW_ANTI_ROLLBACK_2_LSB_ADDR #define ANTI_ROLLBACK_RPM_BMSK (0x1FE0000) #define ANTI_ROLLBACK_RPM_SHFT (17) #define ANTI_ROLLBACK_RPM_MAX (0x8) #define ANTI_ROLLBACK_HYP_ADDRESS HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR #define ANTI_ROLLBACK_HYP_BMSK (0xFFF) #define ANTI_ROLLBACK_HYP_SHFT (0) #define ANTI_ROLLBACK_HYP_MAX (0xC) #define ANTI_ROLLBACK_DP_ADDRESS HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR #define ANTI_ROLLBACK_DP_BMSK (0x1F000) #define ANTI_ROLLBACK_DP_SHFT (12) #define ANTI_ROLLBACK_DP_MAX (0x5) #define ANTI_ROLLBACK_DEV_CFG_ADDRESS HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR #define ANTI_ROLLBACK_DEV_CFG_BMSK (0xFFE0000) #define ANTI_ROLLBACK_DEV_CFG_SHFT (17) #define ANTI_ROLLBACK_DEV_CFG_MAX (0xB) #define ANTI_ROLLBACK_XBL_CONFIG_ADDRESS HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR #define ANTI_ROLLBACK_XBL_CONFIG0_BMSK (0xC0000000) #define ANTI_ROLLBACK_XBL_CONFIG0_SHFT (30) #define ANTI_ROLLBACK_XBL_CONFIG0_MAX (0x2) #define ANTI_ROLLBACK_XBL_CONFIG1_BMSK (0xF0000000) #define ANTI_ROLLBACK_XBL_CONFIG1_SHFT (28) #define ANTI_ROLLBACK_XBL_CONFIG1_MAX (0x4) #define ANTI_ROLLBACK_MISC_ADDRESS HWIO_QFPROM_RAW_ANTI_ROLLBACK_4_LSB_ADDR #define ANTI_ROLLBACK_MISC_BMSK (0xFFFF) #define ANTI_ROLLBACK_MISC_SHFT (0) #define ANTI_ROLLBACK_MISC_MAX (0x10) /* Define for RPMB Fuse */ #define RPMB_FUSE_ADDRESS (HWIO_QFPROM_RAW_ANTI_ROLLBACK_3_LSB_ADDR) #define RPMB_FUSE_BMSK (0x1000000) #define RPMB_FUSE_SHFT (24) /* Define for Oem Config Region */ #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001e0) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001e8) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001f0) #define ANTI_ROLLBACK_EN_SHFT (0) #define ANTI_ROLLBACK_EN_BMSK (0xF) #define ANTI_ROLLBACK_BOOT_FEATURE_EN (1 << 0) #define ANTI_ROLLBACK_TZAPP_FEATURE_EN (1 << 1) #define ANTI_ROLLBACK_PIL_FEATURE_EN (1 << 2) #define ANTI_ROLLBACK_MSA_FEATURE_EN (1 << 3) /* Define for Read Permission Region */ #define HWIO_QFPROM_RAW_RD_PERM_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001c8) /* Define for Write Permission Region */ #define HWIO_QFPROM_RAW_WR_PERM_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001d0) #define HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_BMSK 0x80 #define HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_SHFT 0x7 #define HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_BMSK 0x100 #define HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_SHFT 0x8 #define HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_BMSK 0x200 #define HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_SHFT 0x9 #define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_BMSK 0x400 #define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_SHFT 0xa #define HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_BMSK 0x20000 #define HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_SHFT 0x11 #define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_BMSK 0x800000 #define HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_SHFT 0x17 #define HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK 0x1000000 #define HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT 0x18 /* Define for Anti-Rollback ignore */ #define ANTI_ROLLBACK_IGNORE_BMSK (HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_BMSK | \ HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_BMSK | \ HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_BMSK) #define ANTI_ROLLBACK_IGNORE_VALUE (1 << HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_SHFT | \ 1 << HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_SHFT | \ 1 << HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_SHFT) #define QFPROM_RAW_WR_PERM_BLOWN_ALL_BMSK_WITHOUT_RP ( HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_BMSK ) #define QFPROM_RAW_WR_PERM_BLOWN_ALL_VALUE_WITHOUT_RP ( 1 << HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_SHFT ) #define QFPROM_RAW_WR_PERM_BLOWN_ALL_BMSK_WITH_RP ( HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_BMSK | \ HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_BMSK | \ HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_BMSK | \ HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_BMSK | \ HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_BMSK | \ HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_BMSK | \ HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_BMSK ) #define QFPROM_RAW_WR_PERM_BLOWN_ALL_VALUE_WITH_RP ( 1 << HWIO_QFPROM_RAW_WR_PERM_LSB_RD_PERM_SHFT | \ 1 << HWIO_QFPROM_RAW_WR_PERM_LSB_WR_PERM_SHFT | \ 1 << HWIO_QFPROM_RAW_WR_PERM_LSB_FEC_EN_SHFT | \ 1 << HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_CONFIG_SHFT | \ 1 << HWIO_QFPROM_RAW_WR_PERM_LSB_PK_HASH0_SHFT | \ 1 << HWIO_QFPROM_RAW_WR_PERM_LSB_OEM_SEC_BOOT_SHFT | \ 1 << HWIO_QFPROM_RAW_WR_PERM_LSB_SEC_KEY_DERIVATION_KEY_SHFT ) /* Define for PK Hash */ #define HWIO_QFPROM_RAW_PK_HASH0_ROWn_LSB_ADDR(n) (SECURITY_CONTROL_CORE_REG_BASE + 0x00000260 + 0x8 * (n)) /* Define for OEM CONFIG Enable */ #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW0_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001e0) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW1_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001e8) #define HWIO_QFPROM_RAW_OEM_CONFIG_ROW2_LSB_ADDR (SECURITY_CONTROL_CORE_REG_BASE + 0x000001f0) #define ANTI_ROLLBACK_EN_SHFT (0) #define ANTI_ROLLBACK_EN_BMSK (0xF) #define QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_QSEE_SPIDEN_DISABLE (1 << 30) #define QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_QSEE_SPNIDEN_DISABLE (1 << 31) #define QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_MSS_DBGEN_DISABLE (1<<0) #define QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_MSS_NIDEN_DISABLE (1<<1) #define QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_CP_DBGEN_DISABLE (1<<2) #define QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_CP_NIDEN_DISABLE (1<<3) #define QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_NS_DBGEN_DISABLE (1<<4) #define QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_NS_NIDEN_DISABLE (1<<5) #define QFPROM_RAW_OEM_CONFIG_ROW0_APPS_DBGEN_DISABLE (1<<6) #define QFPROM_RAW_OEM_CONFIG_ROW0_APPS_NIDEN_DISABLE (1<<7) #define QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_MISC_DEBUG_DISABLE (1<<8) #define QFPROM_RAW_OEM_CONFIG_BOOT_LSB_BLOWN_ALL ( QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_QSEE_SPIDEN_DISABLE | \ QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_QSEE_SPNIDEN_DISABLE ) #define QFPROM_RAW_OEM_CONFIG_BOOT_MSB_BLOWN_ALL ( QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_MSS_DBGEN_DISABLE | \ QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_MSS_NIDEN_DISABLE | \ QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_CP_DBGEN_DISABLE | \ QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_CP_NIDEN_DISABLE | \ QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_NS_DBGEN_DISABLE | \ QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_NS_NIDEN_DISABLE | \ QFPROM_RAW_OEM_CONFIG_ROW0_APPS_DBGEN_DISABLE | \ QFPROM_RAW_OEM_CONFIG_ROW0_APPS_NIDEN_DISABLE | \ QFPROM_RAW_OEM_CONFIG_ROW0_SHARED_MISC_DEBUG_DISABLE \ ) #endif