#ifndef __GPIO_ESE_PLATFORM_H__
#define __GPIO_ESE_PLATFORM_H__

/************************************************************************/
/* TZPC SFR Address                                                     */
/************************************************************************/
#define TZPC_PERIC1_0_BASE	0x10042000

#define TZPC0_SFR_PERIC0        0x10010000
#define TZPC0_SRF_STAT          0x200
#define TZPC0_SRF_SET           0x204
#define TZPC0_SRF_CLR           0x208

#define TZPC0_SFR_USI_MODE        0x10010000
#define TZPC0_SRF_USI_STAT          0x210
#define TZPC0_SRF_USI_SET           0x214
#define TZPC0_SRF_USI_CLR           0x218

/************************************************************************/
/* TZPC control Register                                                */
/************************************************************************/


#define USI_I_MODE		(0x1 << 17)
#define GPIO_PERI_PROTECION_BIT (0xFFFFFF00)


/************************************************************************/
/* TZPC control                                                         */
/************************************************************************/
#define TZPC_SECURE	0x0

#define ESE_TZPC_CONFIG_COUNT 3
#define ESE_GPIO_CONFIG_COUNT 1

/************************************************************************/
/* GPIO control Register                                                */
/************************************************************************/

#define GPIO_PERIC1_BASE	0x10040000

#define GPIOCON		0x0000
#define GPIODAT		0x0004
#define GPIOPUD		0x0008
#define GPIODRV		0x000C
#define GPIOCONPDN	0x0010
#define GPIOPUDPDN	0x0014

#define ESE_GPIOCON_ACTIVE	0x00002222
#define ESE_GPIODATA_ACTIVE	0x00000000
#define ESE_GPIOPUD_ACTIVE	0x00000000
#define ESE_GPIODRV_ACTIVE	0x00000000

#define ESE_GPIOCON_SLEEP	0x00001111
#define ESE_GPIODATA_SLEEP	0x00000000
#define ESE_GPIOPUD_SLEEP	0x00001111
#define ESE_GPIODRV_SLEEP	0x00000000

#define ESE_GPIOCON_MASK	0x0000FFFF
#define ESE_GPIODATA_MASK	0x0000000F
#define ESE_GPIOPUD_MASK	0x0000FFFF
#define ESE_GPIODRV_MASK	0x0000FFFF


enum ese_gpio_config_mode {
	ESE_GPIO_CFG_CON, /* function : input/output/func */
	ESE_GPIO_CFG_DAT, /* output value */ 
	ESE_GPIO_CFG_PUD, /* pull */
	ESE_GPIO_CFG_DRV, /* drv strength */
	ESE_GPIO_CFG_CONPDN,
	ESE_GPIO_CFG_PUDPDN,
	/* mode count. if you want to define new mode, you should add it above this property*/
	ESE_GPIO_CFG_MOD_CNT,
};

typedef struct _ese_gpio_config_eliment {
	uint32_t offset;
	uint32_t active_value;
	uint32_t sleep_value;
	uint32_t mask;
} ese_gpio_cfg_eliment;

typedef struct _ese_gpio_config {
	uint32_t base_va; /* virtual adress */
	uint32_t base_pa; /* phsical address */
	ese_gpio_cfg_eliment gpio_cfg[ESE_GPIO_CFG_MOD_CNT];
} ese_gpio_config;

enum ese_tzpc_protection_type {
	ESE_GPIO_PROTECTION = 1,
	ESE_GPIO_PERI_PROTECTION,
	ESE_SPI_PROTECTION,
};

typedef struct _ese_tzpc_config {
	int tzpc_type; /* protection_type */
	uint32_t base_va; /* virtual address */
	uint32_t base_pa; /* physical address */
	uint32_t decprotx_clr;
	uint32_t decprotx_stat;
	uint32_t decprotx_bit;	
} ese_tzpc_config;

ese_tzpc_config* get_ese_tzpc_config(int index);
ese_gpio_config* get_ese_gpio_config(int index);

#endif