/**

 *

 * Copyright (c) 2014-2015 Samsung Electronics Co., Ltd.

 *

 */



#ifndef __GPIO_FP_H__

#define __GPIO_FP_H__



#ifdef __cplusplus

extern "C" {

#endif



#define CONFIG_EXYNOS7420 /* FIXME : It should be controlled by make option */



/* FIXME : Move below two line to somewhere */

#define SFR_PHYS_BASE               0x10000000

#define SFR_VIRT_BASE               (0x80000000 - 0x10000000)

#define DEV_ADDR(phys)              (SFR_VIRT_BASE - SFR_PHYS_BASE + (phys))

#define SFR_REG(base, offset)       *((volatile uint32_t *)(DEV_ADDR(base) + (offset)))

#define read_sfr_value(_sfr_)  SFR_REG(_sfr_, 0)

#define write_sfr_value(_sfr_, _val_)  SFR_REG(_sfr_, 0) = (_val_)



/************************************************************************/

/* Virtual address for SFRs                                             */

/************************************************************************/

#define FP_SFR_VA_BASE	    0x10090000 //0x90000

#define TZPC_SPI_SFR_VA		(FP_SFR_VA_BASE)

#define TZPC_GPIO_SFR_VA	(FP_SFR_VA_BASE + 0x1000)

#define FP_GPIO_SFR_VA	    0x14CA0000 //(FP_SFR_VA_BASE + 0x2000)





/************************************************************************/

/* TZPC control                                                         */

/************************************************************************/

#define FP_MODE		0x1

#define TZPC_SECURE	0x0



#define FP_RET_BIT      (0x1 << 2)



#if defined(CONFIG_EXYNOS7420) || defined(CONFIG_EXYNOS5433)

#define FP_GPIO_PROTECTION

#endif



#if defined(CONFIG_EXYNOS7420)

#define TZPC_SPI_SFR_BASE			TZPC12_SFR_BASE

#define TZPC_SPI_DECPROT_NUM		TZPC_DECPROT3CLR

#define TZPC_SPI_DECSTAT_NUM		TZPC_DECPROT3STAT

#define TZPC_SPI_DECPROT_BIT		TZPC_SPI4_M

#if defined(FP_GPIO_PROTECTION)

#define TZPC_GPIO_SFR_BASE			TZPC13_SFR_BASE

#define TZPC_GPIO_DECPROT_NUM		TZPC_DECPROT1CLR

#define TZPC_GPIO_DECSTAT_NUM		TZPC_DECPROT1STAT

#define TZPC_GPIO_DECPROT_BIT		TZPC_GPIO_ESE_M

#endif	/* FP_GPIO_PROTECTION */



#elif defined(CONFIG_EXYNOS5433) || defined(CONFIG_EXYNOS5430)

#define TZPC_SPI_SFR_BASE			TZPC5_SFR_BASE

#define TZPC_SPI_DECPROT_NUM		TZPC_DECPROT0CLR

#define TZPC_SPI_DECSTAT_NUM		TZPC_DECPROT0STAT

#define TZPC_SPI_DECPROT_BIT		TZPC_SPI2_M

#if defined(FP_GPIO_PROTECTION)

#define TZPC_GPIO_SFR_BASE			TZPC12_SFR_BASE

#define TZPC_GPIO_DECPROT_NUM		TZPC_DECPROT2CLR

#define TZPC_GPIO_DECSTAT_NUM		TZPC_DECPROT2STAT

#define TZPC_GPIO_DECPROT_BIT		TZPC_GPIO_FINGER

#endif	/* FP_GPIO_PROTECTION */



#elif defined(CONFIG_EXYNOS5422) || defined(CONFIG_EXYNOS5420)

#define TZPC_SPI_SFR_BASE			TZPC3_SFR_BASE

#define TZPC_SPI_DECPROT_NUM		TZPC_DECPROT2CLR

#define TZPC_SPI_DECSTAT_NUM		TZPC_DECPROT2STAT

#define TZPC_SPI_DECPROT_BIT		TZPC_SPI1_M



#endif





/************************************************************************/

/* GPIO control                                                         */

/************************************************************************/

#define GPIO_HIGH	0x1

#define GPIO_LOW	0x0



#if defined(CONFIG_EXYNOS7420)

#define FP_GPIO_SFR_BASE			GPIO_ESE_SFR_BASE

#define FP_GPIOCON_INIT_VALUE		0x12222

#define FP_GPIODAT_INIT_VALUE		0x00000

#define FP_GPIOPUD_INIT_VALUE		0x01FF

#define FP_GPIODRV_INIT_VALUE		0x0200

#define FP_GPIOCONPDN_VALUE			0x0320

#define FP_GPIOPUDPDN_VALUE			0x0010

#elif defined(CONFIG_EXYNOS5433) || defined(CONFIG_EXYNOS5430)

#if defined(CONFIG_EXYNOS5433)

#define FP_GPIO_SFR_BASE			GPIO_FINGER_SFR_BASE

#else	/* CONFIG_EXYNOS5430 */

#define FP_GPIO_SFR_BASE			GPIO_PERIC_SFR_BASE

#endif

#define FP_GPIOCON_INIT_VALUE		0x2222

#define FP_GPIODAT_INIT_VALUE		0x0000

#define FP_GPIOPUD_INIT_VALUE		0x0055

#define FP_GPIODRV_INIT_VALUE		0x2222

#define FP_GPIOCONPDN_VALUE			0x0020

#define FP_GPIOPUDPDN_VALUE			0x0010

#elif defined(CONFIG_EXYNOS5422) || defined(CONFIG_EXYNOS5420)

#define FP_GPIO_SFR_BASE			GPIO_BLOCK_SFR_BASE

/* TODO : GPIO Control is needed for these chipsets? */

#endif





/* For TZPC */

uint32_t set_tzpc_fp_secure(void);



/* GPIO */

uint32_t gpio_set_fp_init(void);

uint32_t save_fp_gpio_regs(void);

uint32_t restore_fp_gpio_regs(void);

uint32_t gpio_set_fp_btp_ocp(uint32_t gpio_dat_bit);



#ifdef __cplusplus

}

#endif



#endif