;============================================================================ ; ; *************** THIS SCRIPT WAS AUTOGENERATED **************** ; ; TARGET ; ; ; SCRIPT ; TESTCLOCK.CMM ; ; GENERAL DESCRIPTION ; This script can be used to route specific clocks to the clock test output. ; ; FUNCTIONS ; N/A ; ; Copyright (c) 2019 by QUALCOMM Technologies Inc. All Rights Reserved. ;============================================================================ ; Template inputs: ; &dbg_mux_max ;; Total clock controllers ; &max_clks ;; Max number of clocks in a clock controller ; \a_clock_str ;; The GCC clock names array ; \a_clock_data ;; The GCC clock addresses w/ same index as names ;----------------------------------------------------------------------------- ; Local variables ;----------------------------------------------------------------------------- local &clk local &clk_name local &clk_state local &clk_state_filter local &clk_freq local &clk_freq_str local &header_printed local &clk_test_mux local &clk_test_sel local &clk_reg local &clk_reg_str local &clk_reg_name local &clk_reg_val local &clk_reg_val_str local &clk_reg_cbcr_type local &state_change local &clock_count local &multiplier local &tcxo_count local &match local &chipset_name local &frq_measure_ctl_addr local &frq_measure_status_addr local &xo_div4_cbcr_addr ; ; ARGS script file, absolute path. ; local &ARGS_SCRIPT_FILE &ARGS_SCRIPT_FILE=os.ppf() ; ; ARGS history buffer dimensions: (32 * 512 ) = 16 KB/client. ; local &ARGS_MAX_HIST_ENTRIES local &ARGS_HIST_ENTRY_MAX_LEN local &ARGS_HIST_ENTRY_LAST_IDX &ARGS_MAX_HIST_ENTRIES=32. ; Max number of history entries. &ARGS_HIST_ENTRY_MAX_LEN=512. ; Max length of history entry. &ARGS_HIST_ENTRY_LAST_IDX=(&ARGS_HIST_ENTRY_MAX_LEN-1.) ; ARGS error scratchpad (used for "ON ERROR gosub" execution detection). local &err ; ; ARGS client global variable names. ; local &gvar_name_client_name ; => char[128.] "args_client_name_" local &gvar_name_area_name ; => char[128.] "args_area_name_" local &gvar_name_client_error ; => char[64.] "args_err_" local &gvar_name_cmd_line ; => char[512.] "args_cmd_line_" local &gvar_name_read_idx ; => int "args_read_idx_ local &gvar_name_help_cmd ; => char[64.] "args_help_cmd_" local &gvar_name_help_sub ; => char[64.] "args_help_sub_" local &gvar_name_hist_cmd ; => char[64.] "args_hist_cmd_" local &gvar_name_hist_sub ; => char[64.] "args_hist_sub_" local &gvar_name_nonempty_cmds ; => int (bool) "args_non_empty_cmds_" local &gvar_name_nonempty_vals ; => int (bool) "args_non_empty_vals_" local &gvar_name_print_errors_en ; => int (bool) "args_print_errors_en_" local &gvar_name_hist_en ; => int (bool) "args_hist_en_" local &gvar_name_hist_tip_idx ; => int "args_hist_tip_idx_" local &gvar_name_num_hist_entries ; => int "args_num_hist_entries_" local &gvar_name_hist_buf ; => char[32.][512.] "args_hist_buf_" ; ; Declare/initialize a global monotonically increasing ARGS client counter. ; global &args_client_count if ("&args_client_count"=="") ( &args_client_count=0. ) ; ; Declare/initialize a global ARGS macro to hold the previous ARGS error type. ; This error type macro is common to all clients. Its content is returned when ; no client ID is provided to "get_error". The primary use-cases are to ; trouble-shoot client creation errors and invalid client ID errors. ; global &args_latest_error if ("&args_latest_error"=="") ( &args_latest_error="NO_ERROR" ) ;----------------------------------------------------------------------------- ; Initialize autogenerated constants ;----------------------------------------------------------------------------- goto Init_Constants Init_Constants: ; Chipset Name &chipset_name="sm7250" ; Generated Date &gendate="5/24/2019" ; Access Mode &access_mode="ezaxi" ; Debug Mux Strings &dbg_mux_str_name=0. &dbg_mux_str_access_mode=1. &dbg_mux_str_max=2. ; Debug Mux Regs &dbg_mux_reg_addr=0. &dbg_mux_reg_mask=1. &dbg_mux_reg_shft=2. &dbg_mux_reg_enable_addr=3. &dbg_mux_reg_enable_mask=4. &dbg_mux_reg_parent_idx=5. &dbg_mux_reg_parent_sel=6. &dbg_mux_reg_div_val=7. &dbg_mux_reg_div_hw_val=8. &dbg_mux_reg_div_addr=9. &dbg_mux_reg_div_shft=10. &dbg_mux_reg_div_mask=11. &dbg_mux_reg_num_clks=12. &dbg_mux_reg_plltestpad=13. &dbg_mux_reg_measure_ctl=14. &dbg_mux_reg_measure_status=15. &dbg_mux_reg_xo_div4_addr=16. &dbg_mux_reg_max=17. ; Registers stored &clk_reg_cbc=0. &clk_reg_tc_mux=1. &clk_reg_tc_sel=2. &clk_reg_vote_bit=3. &clk_reg_total_div=4. &clk_reg_mux_input_en_addr=5. &clk_reg_mux_input_en_mask=6. &clk_reg_total=7. ; Registers stored &clk_str_name=0 &clk_str_type=1 &clk_str_regname=2 &clk_str_aliases=3 &clk_str_total=4 &dbg_mux_aoss_cc=0x0 &dbg_mux_apss_cc=0x1 &dbg_mux_cam_cc=0x2 &dbg_mux_disp_cc=0x3 &dbg_mux_dpcc=0x4 &dbg_mux_gcc=0x5 &dbg_mux_gpu_cc=0x6 &dbg_mux_lpass_aon_cc=0x7 &dbg_mux_lpass_aon_cc_q6=0x8 &dbg_mux_lpass_audio_cc=0x9 &dbg_mux_lpass_core_cc=0xa &dbg_mux_lpass_top_cc=0xb &dbg_mux_mss_cc=0xc &dbg_mux_mss_cc_q6=0xd &dbg_mux_mss_cc_vq6=0xe &dbg_mux_nav_cc=0xf &dbg_mux_npu_cc=0x10 &dbg_mux_npu_cc_q6=0x11 &dbg_mux_scc=0x12 &dbg_mux_turing_cc=0x13 &dbg_mux_turing_cc_q6=0x14 &dbg_mux_video_cc=0x15 &dbg_mux_wcss_cc=0x16 &dbg_mux_max=0x17 &dbg_mux_none=0x3ff &max_clk_len=50. &max_mux_len=16. &max_clks=0x145 v.new int[&dbg_mux_max][&dbg_mux_reg_max] \a_dbg_mux_data v.new char[&dbg_mux_max][&dbg_mux_str_max][&max_mux_len] \a_dbg_mux_str v.new char[&dbg_mux_max][&max_clks][&clk_str_total][&max_clk_len] \a_clock_str v.new int[&dbg_mux_max][&max_clks][&clk_reg_total] \a_clock_data v.new int[0x2] \vote_regs v.a \vote_regs[0x0]=0x157000 v.a \vote_regs[0x1]=0x157008 v.a \a_dbg_mux_str[&dbg_mux_aoss_cc][&dbg_mux_str_name]="AOSS_CC" v.a \a_dbg_mux_str[&dbg_mux_aoss_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_num_clks]=0x26 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_addr]=0xc2a3004 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_mask]=0xff v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_enable_addr]=0xc2a2344 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_parent_sel]=0xa2 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_div_val]=0x2 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_div_hw_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_div_addr]=0xc2a2340 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_div_mask]=0x3 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_aoss_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_apss_cc][&dbg_mux_str_name]="APSS_CC" v.a \a_dbg_mux_str[&dbg_mux_apss_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_num_clks]=0x18 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_addr]=0x182a0018 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_mask]=0x7f0 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_shft]=0x4 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_enable_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_enable_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_parent_sel]=0xdb v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_div_addr]=0x182a0018 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_div_shft]=0xb v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_div_mask]=0x7800 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_apss_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_cam_cc][&dbg_mux_str_name]="CAM_CC" v.a \a_dbg_mux_str[&dbg_mux_cam_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_num_clks]=0x40 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_addr]=0xad0d000 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_mask]=0xff v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_enable_addr]=0xad0d008 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_parent_sel]=0x4f v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_div_val]=0x4 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_div_hw_val]=0x3 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_div_addr]=0xad0d004 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_div_mask]=0xf v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_cam_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_disp_cc][&dbg_mux_str_name]="DISP_CC" v.a \a_dbg_mux_str[&dbg_mux_disp_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_num_clks]=0x31 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_addr]=0xaf07000 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_mask]=0xff v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_enable_addr]=0xaf0500c v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_parent_sel]=0x50 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_div_val]=0x4 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_div_hw_val]=0x3 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_div_addr]=0xaf05008 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_div_mask]=0x3 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_disp_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_dpcc][&dbg_mux_str_name]="DPCC" v.a \a_dbg_mux_str[&dbg_mux_dpcc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_num_clks]=0x35 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_addr]=0x90c8000 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_mask]=0x3f v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_enable_addr]=0x90c8008 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_parent_sel]=0xc5 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_div_addr]=0x90c8004 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_div_mask]=0x3 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_dpcc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_gcc][&dbg_mux_str_name]="GCC" v.a \a_dbg_mux_str[&dbg_mux_gcc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_num_clks]=0x145 v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_addr]=0x162000 v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_mask]=0x3ff v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_enable_addr]=0x162008 v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_parent_idx]=&dbg_mux_none v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_parent_sel]=&dbg_mux_none v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_addr]=0x162004 v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_mask]=0xf v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_plltestpad]=0x162034 v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_measure_ctl]=0x162038 v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_measure_status]=0x16203c v.a \a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_xo_div4_addr]=0x14300c v.a \a_dbg_mux_str[&dbg_mux_gpu_cc][&dbg_mux_str_name]="GPU_CC" v.a \a_dbg_mux_str[&dbg_mux_gpu_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_num_clks]=0x20 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_addr]=0x3d91568 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_mask]=0xff v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_enable_addr]=0x3d91100 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_parent_sel]=0x129 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_div_val]=0x2 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_div_hw_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_div_addr]=0x3d910fc v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_div_mask]=0x3 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_gpu_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_lpass_aon_cc][&dbg_mux_str_name]="LPASS_AON_CC" v.a \a_dbg_mux_str[&dbg_mux_lpass_aon_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_num_clks]=0x27 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_addr]=0x338005c v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_mask]=0x7e v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_shft]=0x1 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_enable_addr]=0x338a084 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_lpass_core_cc v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_parent_sel]=0x1 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_div_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_div_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_str_name]="LPASS_AON_CC_Q6" v.a \a_dbg_mux_str[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_num_clks]=0x9 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_addr]=0x3002010 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_mask]=0x1f v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_enable_addr]=0x3002010 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_enable_mask]=0x40 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_parent_idx]=&dbg_mux_lpass_aon_cc v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_parent_sel]=0x1e v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_div_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_div_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_aon_cc_q6][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_lpass_audio_cc][&dbg_mux_str_name]="LPASS_AUDIO_CC" v.a \a_dbg_mux_str[&dbg_mux_lpass_audio_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_num_clks]=0x16 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_addr]=0x332f000 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_mask]=0x3f v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_enable_addr]=0x332d004 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_lpass_aon_cc v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_parent_sel]=0x3f v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_div_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_div_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_audio_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_lpass_core_cc][&dbg_mux_str_name]="LPASS_CORE_CC" v.a \a_dbg_mux_str[&dbg_mux_lpass_core_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_num_clks]=0x27 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_addr]=0x394e000 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_mask]=0xffff v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_enable_addr]=0x394e008 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_lpass_top_cc v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_parent_sel]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_div_val]=0x2 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_div_hw_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_div_addr]=0x394e004 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_div_mask]=0x3 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_core_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_lpass_top_cc][&dbg_mux_str_name]="LPASS_TOP_CC" v.a \a_dbg_mux_str[&dbg_mux_lpass_top_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_num_clks]=0x6 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_addr]=0x3c03008 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_mask]=0x7 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_enable_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_enable_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_parent_sel]=0xcc v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_div_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_div_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_lpass_top_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_mss_cc][&dbg_mux_str_name]="MSS_CC" v.a \a_dbg_mux_str[&dbg_mux_mss_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_num_clks]=0x2a v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_addr]=0x41a8014 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_mask]=0x7ff v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_enable_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_enable_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_parent_sel]=0x11c v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_div_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_div_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_mss_cc_q6][&dbg_mux_str_name]="MSS_CC_Q6" v.a \a_dbg_mux_str[&dbg_mux_mss_cc_q6][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_num_clks]=0x9 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_addr]=0x4082010 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_mask]=0x1f v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_enable_addr]=0x4082010 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_enable_mask]=0x40 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_parent_idx]=&dbg_mux_mss_cc v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_parent_sel]=0x29 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_div_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_div_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_q6][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_mss_cc_vq6][&dbg_mux_str_name]="MSS_CC_VQ6" v.a \a_dbg_mux_str[&dbg_mux_mss_cc_vq6][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_num_clks]=0x9 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_addr]=0x4402010 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_mask]=0x1f v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_enable_addr]=0x4402010 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_enable_mask]=0x40 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_parent_idx]=&dbg_mux_mss_cc v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_parent_sel]=0x2a v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_div_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_div_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_mss_cc_vq6][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_nav_cc][&dbg_mux_str_name]="NAV_CC" v.a \a_dbg_mux_str[&dbg_mux_nav_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_num_clks]=0xd v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_addr]=0x4301a84 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_mask]=0xff v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_enable_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_enable_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_parent_sel]=0x130 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_div_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_div_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_nav_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_npu_cc][&dbg_mux_str_name]="NPU_CC" v.a \a_dbg_mux_str[&dbg_mux_npu_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_num_clks]=0x1f v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_addr]=0x9983000 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_mask]=0xff v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_enable_addr]=0x9983008 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_parent_sel]=0x13b v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_div_val]=0x2 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_div_hw_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_div_addr]=0x9983004 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_div_mask]=0x3 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_npu_cc_q6][&dbg_mux_str_name]="NPU_CC_Q6" v.a \a_dbg_mux_str[&dbg_mux_npu_cc_q6][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_num_clks]=0x9 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_addr]=0x9802010 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_mask]=0x1f v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_enable_addr]=0x9802010 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_enable_mask]=0x40 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_parent_idx]=&dbg_mux_npu_cc v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_parent_sel]=0x20 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_div_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_div_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_npu_cc_q6][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_scc][&dbg_mux_str_name]="SCC" v.a \a_dbg_mux_str[&dbg_mux_scc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_num_clks]=0x14 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_addr]=0x380006c v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_mask]=0x3f v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_enable_addr]=0x380a084 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_parent_idx]=&dbg_mux_lpass_aon_cc v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_parent_sel]=0x3e v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_div_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_div_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_scc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_turing_cc][&dbg_mux_str_name]="TURING_CC" v.a \a_dbg_mux_str[&dbg_mux_turing_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_num_clks]=0x2d v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_addr]=0x8022000 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_mask]=0xff v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_enable_addr]=0x8022008 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_parent_sel]=0xd4 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_div_val]=0x2 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_div_hw_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_div_addr]=0x8022004 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_div_mask]=0x3 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_turing_cc_q6][&dbg_mux_str_name]="TURING_CC_Q6" v.a \a_dbg_mux_str[&dbg_mux_turing_cc_q6][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_num_clks]=0xc v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_addr]=0x8302010 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_mask]=0x1f v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_enable_addr]=0x8302010 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_enable_mask]=0x40 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_parent_idx]=&dbg_mux_turing_cc v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_parent_sel]=0x27 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_div_addr]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_div_mask]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_turing_cc_q6][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_video_cc][&dbg_mux_str_name]="VIDEO_CC" v.a \a_dbg_mux_str[&dbg_mux_video_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_num_clks]=0x10 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_addr]=0xab00acc v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_mask]=0x3f v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_enable_addr]=0xab0093c v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_parent_sel]=0x51 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_div_val]=0x5 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_div_hw_val]=0x4 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_div_addr]=0xab00934 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_div_mask]=0x7 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_video_cc][&dbg_mux_reg_xo_div4_addr]=0x0 v.a \a_dbg_mux_str[&dbg_mux_wcss_cc][&dbg_mux_str_name]="WCSS_CC" v.a \a_dbg_mux_str[&dbg_mux_wcss_cc][&dbg_mux_str_access_mode]="ezaxi" v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_num_clks]=0x43 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_addr]=0x189d6f00 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_mask]=0x7ff v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_enable_addr]=0x189d60f4 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_enable_mask]=0x1 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_parent_idx]=&dbg_mux_gcc v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_parent_sel]=0x125 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_div_val]=0x1 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_div_hw_val]=0x0 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_div_addr]=0x189d6104 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_div_shft]=0x0 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_div_mask]=0x3 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_plltestpad]=0x0 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_measure_ctl]=0x0 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_measure_status]=0x0 v.a \a_dbg_mux_data[&dbg_mux_wcss_cc][&dbg_mux_reg_xo_div4_addr]=0x0 ; AOSS_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_aoss_cc][0x0][&clk_str_name]="aoss_cc_ao_dap_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x0][&clk_str_regname]="AOSS_CC_AO_DAP_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x0][&clk_reg_cbc]=0xc2a2024 v.a \a_clock_data[&dbg_mux_aoss_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x0][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_aoss_cc][0x0][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x1][&clk_str_name]="aoss_cc_aop_bus_ahb_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1][&clk_str_regname]="AOSS_CC_AOP_BUS_AHB_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x1][&clk_reg_cbc]=0xc2a2010 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x1][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x2][&clk_str_name]="aoss_cc_aop_dap_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x2][&clk_str_regname]="AOSS_CC_AOP_DAP_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x2][&clk_reg_cbc]=0xc2a2028 v.a \a_clock_data[&dbg_mux_aoss_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x2][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_aoss_cc][0x2][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x3][&clk_str_name]="aoss_cc_aop_proc_ahb_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x3][&clk_str_regname]="AOSS_CC_AOP_PROC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x3][&clk_reg_cbc]=0xc2a200c v.a \a_clock_data[&dbg_mux_aoss_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x3][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_aoss_cc][0x3][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x4][&clk_str_name]="aoss_cc_aop_proc_freerun_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x4][&clk_str_regname]="AOSS_CC_AOP_PROC_FREERUN_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x4][&clk_reg_cbc]=0xc2a2004 v.a \a_clock_data[&dbg_mux_aoss_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x4][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_aoss_cc][0x4][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x5][&clk_str_name]="aoss_cc_aop_proc_riscv_ahb_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x5][&clk_str_regname]="AOSS_CC_AOP_PROC_RISCV_AHB_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x5][&clk_reg_cbc]=0xc2a2008 v.a \a_clock_data[&dbg_mux_aoss_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x5][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x5][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x6][&clk_str_name]="aoss_cc_aop_ro_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x6][&clk_str_regname]="AOSS_CC_AOP_RO_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x6][&clk_reg_cbc]=0xc2a201c v.a \a_clock_data[&dbg_mux_aoss_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x6][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_aoss_cc][0x6][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x7][&clk_str_name]="aoss_cc_bus_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x7][&clk_str_regname]="AOSS_CC_BUS_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x7][&clk_reg_cbc]=0xc2a2014 v.a \a_clock_data[&dbg_mux_aoss_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x7][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_aoss_cc][0x7][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x8][&clk_str_name]="aoss_cc_eud_at_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x8][&clk_str_regname]="AOSS_CC_EUD_AT_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x8][&clk_reg_cbc]=0xc2a2034 v.a \a_clock_data[&dbg_mux_aoss_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x8][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_aoss_cc][0x8][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x9][&clk_str_name]="aoss_cc_gdsc_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x9][&clk_str_regname]="AOSS_CC_GDSC_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x9][&clk_reg_cbc]=0xc2a203c v.a \a_clock_data[&dbg_mux_aoss_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x9][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_aoss_cc][0x9][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0xa][&clk_str_name]="aoss_cc_ibi_ctrl0_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0xa][&clk_str_regname]="AOSS_CC_IBI_CTRL0_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0xa][&clk_reg_cbc]=0xc2a2154 v.a \a_clock_data[&dbg_mux_aoss_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0xa][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_aoss_cc][0xa][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0xb][&clk_str_name]="aoss_cc_ibi_ctrl1_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0xb][&clk_str_regname]="AOSS_CC_IBI_CTRL1_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0xb][&clk_reg_cbc]=0xc2a2158 v.a \a_clock_data[&dbg_mux_aoss_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0xb][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_aoss_cc][0xb][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0xc][&clk_str_name]="aoss_cc_ibi_ctrl2_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0xc][&clk_str_regname]="AOSS_CC_IBI_CTRL2_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0xc][&clk_reg_cbc]=0xc2a215c v.a \a_clock_data[&dbg_mux_aoss_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0xc][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_aoss_cc][0xc][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0xd][&clk_str_name]="aoss_cc_ibi_ctrl3_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0xd][&clk_str_regname]="AOSS_CC_IBI_CTRL3_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0xd][&clk_reg_cbc]=0xc2a2160 v.a \a_clock_data[&dbg_mux_aoss_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0xd][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_aoss_cc][0xd][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0xe][&clk_str_name]="aoss_cc_message_ram_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0xe][&clk_str_regname]="AOSS_CC_MESSAGE_RAM_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0xe][&clk_reg_cbc]=0xc2a2018 v.a \a_clock_data[&dbg_mux_aoss_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0xe][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_aoss_cc][0xe][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0xf][&clk_str_name]="aoss_cc_pdc_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0xf][&clk_str_regname]="AOSS_CC_PDC_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0xf][&clk_reg_cbc]=0xc2a2044 v.a \a_clock_data[&dbg_mux_aoss_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0xf][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_aoss_cc][0xf][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x10][&clk_str_name]="aoss_cc_pdc_global_cntr_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x10][&clk_str_regname]="AOSS_CC_PDC_GLOBAL_CNTR_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x10][&clk_reg_cbc]=0xc2a2048 v.a \a_clock_data[&dbg_mux_aoss_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x10][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_aoss_cc][0x10][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x11][&clk_str_name]="aoss_cc_periph_slp_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x11][&clk_str_regname]="AOSS_CC_PERIPH_SLP_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x11][&clk_reg_cbc]=0xc2a2228 v.a \a_clock_data[&dbg_mux_aoss_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x11][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_aoss_cc][0x11][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x12][&clk_str_name]="aoss_cc_pwr_mux_ctrl_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x12][&clk_str_regname]="AOSS_CC_PWR_MUX_CTRL_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x12][&clk_reg_cbc]=0xc2a2020 v.a \a_clock_data[&dbg_mux_aoss_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x12][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_aoss_cc][0x12][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x13][&clk_str_name]="aoss_cc_ro_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x13][&clk_str_regname]="AOSS_CC_RO_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x13][&clk_reg_cbc]=0xc2a2030 v.a \a_clock_data[&dbg_mux_aoss_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x13][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_aoss_cc][0x13][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x14][&clk_str_name]="aoss_cc_rpmh_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x14][&clk_str_regname]="AOSS_CC_RPMH_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x14][&clk_reg_cbc]=0xc2a2364 v.a \a_clock_data[&dbg_mux_aoss_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x14][&clk_reg_tc_sel]=0x26 v.a \a_clock_data[&dbg_mux_aoss_cc][0x14][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x15][&clk_str_name]="aoss_cc_rpmh_global_cntr_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x15][&clk_str_regname]="AOSS_CC_RPMH_GLOBAL_CNTR_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x15][&clk_reg_cbc]=0xc2a23a4 v.a \a_clock_data[&dbg_mux_aoss_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x15][&clk_reg_tc_sel]=0x27 v.a \a_clock_data[&dbg_mux_aoss_cc][0x15][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x16][&clk_str_name]="aoss_cc_sleep_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x16][&clk_str_regname]="AOSS_CC_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x16][&clk_reg_cbc]=0xc2a21e8 v.a \a_clock_data[&dbg_mux_aoss_cc][0x16][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x16][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_aoss_cc][0x16][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x17][&clk_str_name]="aoss_cc_spmi_aod_ser_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x17][&clk_str_regname]="AOSS_CC_SPMI_AOD_SER_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x17][&clk_reg_cbc]=0xc2a22e4 v.a \a_clock_data[&dbg_mux_aoss_cc][0x17][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x17][&clk_reg_tc_sel]=0x23 v.a \a_clock_data[&dbg_mux_aoss_cc][0x17][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x18][&clk_str_name]="aoss_cc_spmi_cfg_ahb_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x18][&clk_str_regname]="AOSS_CC_SPMI_CFG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x18][&clk_reg_cbc]=0xc2a22dc v.a \a_clock_data[&dbg_mux_aoss_cc][0x18][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x18][&clk_reg_tc_sel]=0x21 v.a \a_clock_data[&dbg_mux_aoss_cc][0x18][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x19][&clk_str_name]="aoss_cc_spmi_ser_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x19][&clk_str_regname]="AOSS_CC_SPMI_SER_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x19][&clk_reg_cbc]=0xc2a22e0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x19][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x19][&clk_reg_tc_sel]=0x22 v.a \a_clock_data[&dbg_mux_aoss_cc][0x19][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x1a][&clk_str_name]="aoss_cc_swao_ao_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1a][&clk_str_regname]="AOSS_CC_SWAO_AO_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x1a][&clk_reg_cbc]=0xc2a2244 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1a][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x1a][&clk_reg_tc_sel]=0x1c v.a \a_clock_data[&dbg_mux_aoss_cc][0x1a][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x1b][&clk_str_name]="aoss_cc_swao_bus_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1b][&clk_str_regname]="AOSS_CC_SWAO_BUS_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x1b][&clk_reg_cbc]=0xc2a2254 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1b][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x1b][&clk_reg_tc_sel]=0x20 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1b][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x1c][&clk_str_name]="aoss_cc_swao_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1c][&clk_str_regname]="AOSS_CC_SWAO_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x1c][&clk_reg_cbc]=0xc2a2240 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1c][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x1c][&clk_reg_tc_sel]=0x1b v.a \a_clock_data[&dbg_mux_aoss_cc][0x1c][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x1d][&clk_str_name]="aoss_cc_swao_mem_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1d][&clk_str_regname]="AOSS_CC_SWAO_MEM_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x1d][&clk_reg_cbc]=0xc2a2248 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1d][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x1d][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_aoss_cc][0x1d][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x1e][&clk_str_name]="aoss_cc_swao_rpmh_debug_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1e][&clk_str_regname]="AOSS_CC_SWAO_RPMH_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x1e][&clk_reg_cbc]=0xc2a223c v.a \a_clock_data[&dbg_mux_aoss_cc][0x1e][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x1e][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_aoss_cc][0x1e][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x1f][&clk_str_name]="aoss_cc_swao_ts_ao_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1f][&clk_str_regname]="AOSS_CC_SWAO_TS_AO_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x1f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x1f][&clk_reg_cbc]=0xc2a2250 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1f][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x1f][&clk_reg_tc_sel]=0x1f v.a \a_clock_data[&dbg_mux_aoss_cc][0x1f][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x1f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x1f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x20][&clk_str_name]="aoss_cc_swao_ts_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x20][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x20][&clk_str_regname]="AOSS_CC_SWAO_TS_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x20][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x20][&clk_reg_cbc]=0xc2a224c v.a \a_clock_data[&dbg_mux_aoss_cc][0x20][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x20][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_aoss_cc][0x20][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x20][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x20][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x20][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x21][&clk_str_name]="aoss_cc_tsens_hw_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x21][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x21][&clk_str_regname]="AOSS_CC_TSENS_HW_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x21][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x21][&clk_reg_cbc]=0xc2a2040 v.a \a_clock_data[&dbg_mux_aoss_cc][0x21][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x21][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_aoss_cc][0x21][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x21][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x21][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x21][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x22][&clk_str_name]="aoss_cc_wcss_ts_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x22][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x22][&clk_str_regname]="AOSS_CC_WCSS_TS_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x22][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x22][&clk_reg_cbc]=0xc2a202c v.a \a_clock_data[&dbg_mux_aoss_cc][0x22][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x22][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_aoss_cc][0x22][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x22][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x22][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x22][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x23][&clk_str_name]="aoss_cc_xo_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x23][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_aoss_cc][0x23][&clk_str_regname]="AOSS_CC_XO_CBCR" v.a \a_clock_str[&dbg_mux_aoss_cc][0x23][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x23][&clk_reg_cbc]=0xc2a2038 v.a \a_clock_data[&dbg_mux_aoss_cc][0x23][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x23][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_aoss_cc][0x23][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x23][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x23][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x23][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x24][&clk_str_name]="ssc_dbg_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x24][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_aoss_cc][0x24][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_aoss_cc][0x24][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x24][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x24][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x24][&clk_reg_tc_sel]=0x25 v.a \a_clock_data[&dbg_mux_aoss_cc][0x24][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x24][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x24][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x24][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_aoss_cc][0x25][&clk_str_name]="wcss_dbg_clk" v.a \a_clock_str[&dbg_mux_aoss_cc][0x25][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_aoss_cc][0x25][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_aoss_cc][0x25][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_aoss_cc][0x25][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x25][&clk_reg_tc_mux]=&dbg_mux_aoss_cc v.a \a_clock_data[&dbg_mux_aoss_cc][0x25][&clk_reg_tc_sel]=0x24 v.a \a_clock_data[&dbg_mux_aoss_cc][0x25][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_aoss_cc][0x25][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_aoss_cc][0x25][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_aoss_cc][0x25][&clk_reg_mux_input_en_mask]=0x0 ; APSS_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_apss_cc][0x0][&clk_str_name]="apcs_apb_apcsdbg_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x0][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_apss_cc][0x0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x1][&clk_str_name]="apcs_gold_pll_bist_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x1][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x1][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x1][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x1][&clk_reg_tc_sel]=0x26 v.a \a_clock_data[&dbg_mux_apss_cc][0x1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x2][&clk_str_name]="apcs_gold_pll_dtest_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x2][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x2][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x2][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x2][&clk_reg_tc_sel]=0x24 v.a \a_clock_data[&dbg_mux_apss_cc][0x2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x3][&clk_str_name]="apcs_gold_post_acd_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x3][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x3][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x3][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x3][&clk_reg_tc_sel]=0x25 v.a \a_clock_data[&dbg_mux_apss_cc][0x3][&clk_reg_total_div]=0x8 v.a \a_clock_data[&dbg_mux_apss_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x4][&clk_str_name]="apcs_gold_pre_acd_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x4][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x4][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x4][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x4][&clk_reg_tc_sel]=0x45 v.a \a_clock_data[&dbg_mux_apss_cc][0x4][&clk_reg_total_div]=0x10 v.a \a_clock_data[&dbg_mux_apss_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x5][&clk_str_name]="apcs_goldplus_pll_bist_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x5][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x5][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x5][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x5][&clk_reg_tc_sel]=0x62 v.a \a_clock_data[&dbg_mux_apss_cc][0x5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x6][&clk_str_name]="apcs_goldplus_pll_dtest_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x6][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x6][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x6][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x6][&clk_reg_tc_sel]=0x60 v.a \a_clock_data[&dbg_mux_apss_cc][0x6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x7][&clk_str_name]="apcs_goldplus_post_acd_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x7][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x7][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x7][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x7][&clk_reg_tc_sel]=0x61 v.a \a_clock_data[&dbg_mux_apss_cc][0x7][&clk_reg_total_div]=0x8 v.a \a_clock_data[&dbg_mux_apss_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x8][&clk_str_name]="apcs_goldplus_pre_acd_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x8][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x8][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x8][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x8][&clk_reg_tc_sel]=0x47 v.a \a_clock_data[&dbg_mux_apss_cc][0x8][&clk_reg_total_div]=0x10 v.a \a_clock_data[&dbg_mux_apss_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x9][&clk_str_name]="apcs_hdcd_ahbgated_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x9][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x9][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x9][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x9][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_apss_cc][0x9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0xa][&clk_str_name]="apcs_im_ref_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0xa][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xa][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0xa][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0xa][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_apss_cc][0xa][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0xb][&clk_str_name]="apcs_im_sleep_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0xb][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xb][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0xb][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0xb][&clk_reg_tc_sel]=0x1c v.a \a_clock_data[&dbg_mux_apss_cc][0xb][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0xc][&clk_str_name]="apcs_ipm_cbc_clk_out" v.a \a_clock_str[&dbg_mux_apss_cc][0xc][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xc][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0xc][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0xc][&clk_reg_tc_sel]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xc][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0xd][&clk_str_name]="apcs_l3_pll_bist_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0xd][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xd][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0xd][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0xd][&clk_reg_tc_sel]=0x42 v.a \a_clock_data[&dbg_mux_apss_cc][0xd][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0xe][&clk_str_name]="apcs_l3_pll_dtest_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0xe][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xe][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0xe][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0xe][&clk_reg_tc_sel]=0x40 v.a \a_clock_data[&dbg_mux_apss_cc][0xe][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0xf][&clk_str_name]="apcs_l3_post_acd_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0xf][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xf][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0xf][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0xf][&clk_reg_tc_sel]=0x41 v.a \a_clock_data[&dbg_mux_apss_cc][0xf][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_apss_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x10][&clk_str_name]="apcs_l3_pre_acd_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x10][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x10][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x10][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x10][&clk_reg_tc_sel]=0x46 v.a \a_clock_data[&dbg_mux_apss_cc][0x10][&clk_reg_total_div]=0x10 v.a \a_clock_data[&dbg_mux_apss_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x11][&clk_str_name]="apcs_lmh_lite_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x11][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x11][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x11][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x11][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_apss_cc][0x11][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x12][&clk_str_name]="apcs_osm_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x12][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x12][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x12][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x12][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_apss_cc][0x12][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x13][&clk_str_name]="apcs_periph_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x13][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x13][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x13][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x13][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_apss_cc][0x13][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x14][&clk_str_name]="apcs_silver_pll_bist_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x14][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x14][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x14][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x14][&clk_reg_tc_sel]=0x22 v.a \a_clock_data[&dbg_mux_apss_cc][0x14][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x15][&clk_str_name]="apcs_silver_pll_dtest_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x15][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x15][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x15][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x15][&clk_reg_tc_sel]=0x20 v.a \a_clock_data[&dbg_mux_apss_cc][0x15][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_apss_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x16][&clk_str_name]="apcs_silver_post_acd_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x16][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x16][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x16][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x16][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x16][&clk_reg_tc_sel]=0x21 v.a \a_clock_data[&dbg_mux_apss_cc][0x16][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_apss_cc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_apss_cc][0x17][&clk_str_name]="apcs_silver_pre_acd_clk" v.a \a_clock_str[&dbg_mux_apss_cc][0x17][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x17][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_apss_cc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_apss_cc][0x17][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x17][&clk_reg_tc_mux]=&dbg_mux_apss_cc v.a \a_clock_data[&dbg_mux_apss_cc][0x17][&clk_reg_tc_sel]=0x44 v.a \a_clock_data[&dbg_mux_apss_cc][0x17][&clk_reg_total_div]=0x10 v.a \a_clock_data[&dbg_mux_apss_cc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_apss_cc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_apss_cc][0x17][&clk_reg_mux_input_en_mask]=0x0 ; CAM_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_cam_cc][0x0][&clk_str_name]="cam_cc_bps_ahb_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x0][&clk_str_regname]="CAM_CC_BPS_AHB_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x0][&clk_reg_cbc]=0xad07070 v.a \a_clock_data[&dbg_mux_cam_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x0][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_cam_cc][0x0][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x1][&clk_str_name]="cam_cc_bps_areg_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x1][&clk_str_regname]="CAM_CC_BPS_AREG_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x1][&clk_reg_cbc]=0xad07054 v.a \a_clock_data[&dbg_mux_cam_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x1][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_cam_cc][0x1][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x2][&clk_str_name]="cam_cc_bps_axi_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x2][&clk_str_regname]="CAM_CC_BPS_AXI_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x2][&clk_reg_cbc]=0xad07038 v.a \a_clock_data[&dbg_mux_cam_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x2][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_cam_cc][0x2][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x3][&clk_str_name]="cam_cc_bps_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x3][&clk_str_regname]="CAM_CC_BPS_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x3][&clk_reg_cbc]=0xad07028 v.a \a_clock_data[&dbg_mux_cam_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x3][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_cam_cc][0x3][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x4][&clk_str_name]="cam_cc_camnoc_axi_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x4][&clk_str_regname]="CAM_CC_CAMNOC_AXI_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x4][&clk_reg_cbc]=0xad0c148 v.a \a_clock_data[&dbg_mux_cam_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x4][&clk_reg_tc_sel]=0x27 v.a \a_clock_data[&dbg_mux_cam_cc][0x4][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x5][&clk_str_name]="cam_cc_camnoc_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x5][&clk_str_regname]="CAM_CC_CAMNOC_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x5][&clk_reg_cbc]=0xad0c150 v.a \a_clock_data[&dbg_mux_cam_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x5][&clk_reg_tc_sel]=0x33 v.a \a_clock_data[&dbg_mux_cam_cc][0x5][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x6][&clk_str_name]="cam_cc_cci_0_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x6][&clk_str_regname]="CAM_CC_CCI_0_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x6][&clk_reg_cbc]=0xad0c0dc v.a \a_clock_data[&dbg_mux_cam_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x6][&clk_reg_tc_sel]=0x2a v.a \a_clock_data[&dbg_mux_cam_cc][0x6][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x7][&clk_str_name]="cam_cc_cci_1_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x7][&clk_str_regname]="CAM_CC_CCI_1_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x7][&clk_reg_cbc]=0xad0c0f8 v.a \a_clock_data[&dbg_mux_cam_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x7][&clk_reg_tc_sel]=0x3b v.a \a_clock_data[&dbg_mux_cam_cc][0x7][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x8][&clk_str_name]="cam_cc_core_ahb_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x8][&clk_str_regname]="CAM_CC_CORE_AHB_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x8][&clk_reg_cbc]=0xad0c184 v.a \a_clock_data[&dbg_mux_cam_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x8][&clk_reg_tc_sel]=0x2e v.a \a_clock_data[&dbg_mux_cam_cc][0x8][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x9][&clk_str_name]="cam_cc_cpas_ahb_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x9][&clk_str_regname]="CAM_CC_CPAS_AHB_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x9][&clk_reg_cbc]=0xad0c124 v.a \a_clock_data[&dbg_mux_cam_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x9][&clk_reg_tc_sel]=0x2c v.a \a_clock_data[&dbg_mux_cam_cc][0x9][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0xa][&clk_str_name]="cam_cc_csi0phytimer_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0xa][&clk_str_regname]="CAM_CC_CSI0PHYTIMER_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0xa][&clk_reg_cbc]=0xad0601c v.a \a_clock_data[&dbg_mux_cam_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0xa][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_cam_cc][0xa][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0xb][&clk_str_name]="cam_cc_csi1phytimer_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0xb][&clk_str_regname]="CAM_CC_CSI1PHYTIMER_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0xb][&clk_reg_cbc]=0xad06040 v.a \a_clock_data[&dbg_mux_cam_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0xb][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_cam_cc][0xb][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0xc][&clk_str_name]="cam_cc_csi2phytimer_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0xc][&clk_str_regname]="CAM_CC_CSI2PHYTIMER_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0xc][&clk_reg_cbc]=0xad06064 v.a \a_clock_data[&dbg_mux_cam_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0xc][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_cam_cc][0xc][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0xd][&clk_str_name]="cam_cc_csi3phytimer_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0xd][&clk_str_regname]="CAM_CC_CSI3PHYTIMER_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0xd][&clk_reg_cbc]=0xad06088 v.a \a_clock_data[&dbg_mux_cam_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0xd][&clk_reg_tc_sel]=0x35 v.a \a_clock_data[&dbg_mux_cam_cc][0xd][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0xe][&clk_str_name]="cam_cc_csiphy0_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0xe][&clk_str_regname]="CAM_CC_CSIPHY0_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0xe][&clk_reg_cbc]=0xad06020 v.a \a_clock_data[&dbg_mux_cam_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0xe][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_cam_cc][0xe][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0xf][&clk_str_name]="cam_cc_csiphy1_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0xf][&clk_str_regname]="CAM_CC_CSIPHY1_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0xf][&clk_reg_cbc]=0xad06044 v.a \a_clock_data[&dbg_mux_cam_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0xf][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_cam_cc][0xf][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x10][&clk_str_name]="cam_cc_csiphy2_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x10][&clk_str_regname]="CAM_CC_CSIPHY2_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x10][&clk_reg_cbc]=0xad06068 v.a \a_clock_data[&dbg_mux_cam_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x10][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_cam_cc][0x10][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x11][&clk_str_name]="cam_cc_csiphy3_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x11][&clk_str_regname]="CAM_CC_CSIPHY3_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x11][&clk_reg_cbc]=0xad0608c v.a \a_clock_data[&dbg_mux_cam_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x11][&clk_reg_tc_sel]=0x36 v.a \a_clock_data[&dbg_mux_cam_cc][0x11][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x12][&clk_str_name]="cam_cc_fd_core_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x12][&clk_str_regname]="CAM_CC_FD_CORE_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x12][&clk_reg_cbc]=0xad0c0b4 v.a \a_clock_data[&dbg_mux_cam_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x12][&clk_reg_tc_sel]=0x28 v.a \a_clock_data[&dbg_mux_cam_cc][0x12][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x13][&clk_str_name]="cam_cc_fd_core_uar_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x13][&clk_str_regname]="CAM_CC_FD_CORE_UAR_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x13][&clk_reg_cbc]=0xad0c0bc v.a \a_clock_data[&dbg_mux_cam_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x13][&clk_reg_tc_sel]=0x29 v.a \a_clock_data[&dbg_mux_cam_cc][0x13][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x14][&clk_str_name]="cam_cc_gdsc_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x14][&clk_str_regname]="CAM_CC_GDSC_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x14][&clk_reg_cbc]=0xad0c1a0 v.a \a_clock_data[&dbg_mux_cam_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x14][&clk_reg_tc_sel]=0x3c v.a \a_clock_data[&dbg_mux_cam_cc][0x14][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x15][&clk_str_name]="cam_cc_icp_ahb_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x15][&clk_str_regname]="CAM_CC_ICP_AHB_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x15][&clk_reg_cbc]=0xad0c094 v.a \a_clock_data[&dbg_mux_cam_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x15][&clk_reg_tc_sel]=0x37 v.a \a_clock_data[&dbg_mux_cam_cc][0x15][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x16][&clk_str_name]="cam_cc_icp_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x16][&clk_str_regname]="CAM_CC_ICP_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x16][&clk_reg_cbc]=0xad0c08c v.a \a_clock_data[&dbg_mux_cam_cc][0x16][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x16][&clk_reg_tc_sel]=0x26 v.a \a_clock_data[&dbg_mux_cam_cc][0x16][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x17][&clk_str_name]="cam_cc_ife_0_axi_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x17][&clk_str_regname]="CAM_CC_IFE_0_AXI_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x17][&clk_reg_cbc]=0xad0a080 v.a \a_clock_data[&dbg_mux_cam_cc][0x17][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x17][&clk_reg_tc_sel]=0x1b v.a \a_clock_data[&dbg_mux_cam_cc][0x17][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x18][&clk_str_name]="cam_cc_ife_0_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x18][&clk_str_regname]="CAM_CC_IFE_0_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x18][&clk_reg_cbc]=0xad0a028 v.a \a_clock_data[&dbg_mux_cam_cc][0x18][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x18][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_cam_cc][0x18][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x19][&clk_str_name]="cam_cc_ife_0_cphy_rx_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x19][&clk_str_regname]="CAM_CC_IFE_0_CPHY_RX_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x19][&clk_reg_cbc]=0xad0a07c v.a \a_clock_data[&dbg_mux_cam_cc][0x19][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x19][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_cam_cc][0x19][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x1a][&clk_str_name]="cam_cc_ife_0_csid_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x1a][&clk_str_regname]="CAM_CC_IFE_0_CSID_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x1a][&clk_reg_cbc]=0xad0a054 v.a \a_clock_data[&dbg_mux_cam_cc][0x1a][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x1a][&clk_reg_tc_sel]=0x19 v.a \a_clock_data[&dbg_mux_cam_cc][0x1a][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x1b][&clk_str_name]="cam_cc_ife_0_dsp_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x1b][&clk_str_regname]="CAM_CC_IFE_0_DSP_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x1b][&clk_reg_cbc]=0xad0a038 v.a \a_clock_data[&dbg_mux_cam_cc][0x1b][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x1b][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_cam_cc][0x1b][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x1c][&clk_str_name]="cam_cc_ife_1_axi_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x1c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x1c][&clk_str_regname]="CAM_CC_IFE_1_AXI_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x1c][&clk_reg_cbc]=0xad0b058 v.a \a_clock_data[&dbg_mux_cam_cc][0x1c][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x1c][&clk_reg_tc_sel]=0x21 v.a \a_clock_data[&dbg_mux_cam_cc][0x1c][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x1d][&clk_str_name]="cam_cc_ife_1_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x1d][&clk_str_regname]="CAM_CC_IFE_1_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x1d][&clk_reg_cbc]=0xad0b028 v.a \a_clock_data[&dbg_mux_cam_cc][0x1d][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x1d][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_cam_cc][0x1d][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x1e][&clk_str_name]="cam_cc_ife_1_cphy_rx_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x1e][&clk_str_regname]="CAM_CC_IFE_1_CPHY_RX_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x1e][&clk_reg_cbc]=0xad0b054 v.a \a_clock_data[&dbg_mux_cam_cc][0x1e][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x1e][&clk_reg_tc_sel]=0x20 v.a \a_clock_data[&dbg_mux_cam_cc][0x1e][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x1e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x1f][&clk_str_name]="cam_cc_ife_1_csid_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x1f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x1f][&clk_str_regname]="CAM_CC_IFE_1_CSID_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x1f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x1f][&clk_reg_cbc]=0xad0b04c v.a \a_clock_data[&dbg_mux_cam_cc][0x1f][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x1f][&clk_reg_tc_sel]=0x1f v.a \a_clock_data[&dbg_mux_cam_cc][0x1f][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x1f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x1f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x1f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x20][&clk_str_name]="cam_cc_ife_1_dsp_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x20][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x20][&clk_str_regname]="CAM_CC_IFE_1_DSP_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x20][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x20][&clk_reg_cbc]=0xad0b030 v.a \a_clock_data[&dbg_mux_cam_cc][0x20][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x20][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_cam_cc][0x20][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x20][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x20][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x20][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x21][&clk_str_name]="cam_cc_ife_lite_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x21][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x21][&clk_str_regname]="CAM_CC_IFE_LITE_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x21][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x21][&clk_reg_cbc]=0xad0c01c v.a \a_clock_data[&dbg_mux_cam_cc][0x21][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x21][&clk_reg_tc_sel]=0x22 v.a \a_clock_data[&dbg_mux_cam_cc][0x21][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x21][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x21][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x21][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x22][&clk_str_name]="cam_cc_ife_lite_cphy_rx_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x22][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x22][&clk_str_regname]="CAM_CC_IFE_LITE_CPHY_RX_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x22][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x22][&clk_reg_cbc]=0xad0c040 v.a \a_clock_data[&dbg_mux_cam_cc][0x22][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x22][&clk_reg_tc_sel]=0x24 v.a \a_clock_data[&dbg_mux_cam_cc][0x22][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x22][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x22][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x22][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x23][&clk_str_name]="cam_cc_ife_lite_csid_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x23][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x23][&clk_str_regname]="CAM_CC_IFE_LITE_CSID_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x23][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x23][&clk_reg_cbc]=0xad0c038 v.a \a_clock_data[&dbg_mux_cam_cc][0x23][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x23][&clk_reg_tc_sel]=0x23 v.a \a_clock_data[&dbg_mux_cam_cc][0x23][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x23][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x23][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x23][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x24][&clk_str_name]="cam_cc_ipe_0_ahb_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x24][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x24][&clk_str_regname]="CAM_CC_IPE_0_AHB_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x24][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x24][&clk_reg_cbc]=0xad08040 v.a \a_clock_data[&dbg_mux_cam_cc][0x24][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x24][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_cam_cc][0x24][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x24][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x24][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x24][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x25][&clk_str_name]="cam_cc_ipe_0_areg_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x25][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x25][&clk_str_regname]="CAM_CC_IPE_0_AREG_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x25][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x25][&clk_reg_cbc]=0xad0803c v.a \a_clock_data[&dbg_mux_cam_cc][0x25][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x25][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_cam_cc][0x25][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x25][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x25][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x25][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x26][&clk_str_name]="cam_cc_ipe_0_axi_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x26][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x26][&clk_str_regname]="CAM_CC_IPE_0_AXI_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x26][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x26][&clk_reg_cbc]=0xad08038 v.a \a_clock_data[&dbg_mux_cam_cc][0x26][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x26][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_cam_cc][0x26][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x26][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x26][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x26][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x27][&clk_str_name]="cam_cc_ipe_0_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x27][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x27][&clk_str_regname]="CAM_CC_IPE_0_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x27][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x27][&clk_reg_cbc]=0xad08028 v.a \a_clock_data[&dbg_mux_cam_cc][0x27][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x27][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_cam_cc][0x27][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x27][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x27][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x27][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x28][&clk_str_name]="cam_cc_ipe_1_ahb_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x28][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x28][&clk_str_regname]="CAM_CC_IPE_1_AHB_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x28][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x28][&clk_reg_cbc]=0xad09028 v.a \a_clock_data[&dbg_mux_cam_cc][0x28][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x28][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_cam_cc][0x28][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x28][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x28][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x28][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x29][&clk_str_name]="cam_cc_ipe_1_areg_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x29][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x29][&clk_str_regname]="CAM_CC_IPE_1_AREG_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x29][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x29][&clk_reg_cbc]=0xad09024 v.a \a_clock_data[&dbg_mux_cam_cc][0x29][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x29][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_cam_cc][0x29][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x29][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x29][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x29][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x2a][&clk_str_name]="cam_cc_ipe_1_axi_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x2a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x2a][&clk_str_regname]="CAM_CC_IPE_1_AXI_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x2a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x2a][&clk_reg_cbc]=0xad09020 v.a \a_clock_data[&dbg_mux_cam_cc][0x2a][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x2a][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_cam_cc][0x2a][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x2a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x2a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x2a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x2b][&clk_str_name]="cam_cc_ipe_1_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x2b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x2b][&clk_str_regname]="CAM_CC_IPE_1_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x2b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x2b][&clk_reg_cbc]=0xad09010 v.a \a_clock_data[&dbg_mux_cam_cc][0x2b][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x2b][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_cam_cc][0x2b][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x2b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x2b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x2b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x2c][&clk_str_name]="cam_cc_jpeg_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x2c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x2c][&clk_str_regname]="CAM_CC_JPEG_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x2c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x2c][&clk_reg_cbc]=0xad0c060 v.a \a_clock_data[&dbg_mux_cam_cc][0x2c][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x2c][&clk_reg_tc_sel]=0x25 v.a \a_clock_data[&dbg_mux_cam_cc][0x2c][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x2c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x2c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x2c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x2d][&clk_str_name]="cam_cc_lrme_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x2d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x2d][&clk_str_regname]="CAM_CC_LRME_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x2d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x2d][&clk_reg_cbc]=0xad0c118 v.a \a_clock_data[&dbg_mux_cam_cc][0x2d][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x2d][&clk_reg_tc_sel]=0x2b v.a \a_clock_data[&dbg_mux_cam_cc][0x2d][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x2d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x2d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x2d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x2e][&clk_str_name]="cam_cc_mclk0_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x2e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x2e][&clk_str_regname]="CAM_CC_MCLK0_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x2e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x2e][&clk_reg_cbc]=0xad0501c v.a \a_clock_data[&dbg_mux_cam_cc][0x2e][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x2e][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_cam_cc][0x2e][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x2e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x2e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x2e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x2f][&clk_str_name]="cam_cc_mclk1_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x2f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x2f][&clk_str_regname]="CAM_CC_MCLK1_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x2f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x2f][&clk_reg_cbc]=0xad0503c v.a \a_clock_data[&dbg_mux_cam_cc][0x2f][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x2f][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_cam_cc][0x2f][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x2f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x2f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x2f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x30][&clk_str_name]="cam_cc_mclk2_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x30][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x30][&clk_str_regname]="CAM_CC_MCLK2_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x30][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x30][&clk_reg_cbc]=0xad0505c v.a \a_clock_data[&dbg_mux_cam_cc][0x30][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x30][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_cam_cc][0x30][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x30][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x30][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x30][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x31][&clk_str_name]="cam_cc_mclk3_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x31][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x31][&clk_str_regname]="CAM_CC_MCLK3_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x31][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x31][&clk_reg_cbc]=0xad0507c v.a \a_clock_data[&dbg_mux_cam_cc][0x31][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x31][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x31][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x31][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x31][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x31][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x32][&clk_str_name]="cam_cc_mclk4_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x32][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x32][&clk_str_regname]="CAM_CC_MCLK4_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x32][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x32][&clk_reg_cbc]=0xad0509c v.a \a_clock_data[&dbg_mux_cam_cc][0x32][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x32][&clk_reg_tc_sel]=0x44 v.a \a_clock_data[&dbg_mux_cam_cc][0x32][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x32][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x32][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x32][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x33][&clk_str_name]="cam_cc_qdss_debug_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x33][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x33][&clk_str_regname]="CAM_CC_QDSS_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x33][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x33][&clk_reg_cbc]=0xad0c170 v.a \a_clock_data[&dbg_mux_cam_cc][0x33][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x33][&clk_reg_tc_sel]=0x3d v.a \a_clock_data[&dbg_mux_cam_cc][0x33][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x33][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x33][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x33][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x34][&clk_str_name]="cam_cc_qdss_debug_xo_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x34][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x34][&clk_str_regname]="CAM_CC_QDSS_DEBUG_XO_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x34][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x34][&clk_reg_cbc]=0xad0c174 v.a \a_clock_data[&dbg_mux_cam_cc][0x34][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x34][&clk_reg_tc_sel]=0x3e v.a \a_clock_data[&dbg_mux_cam_cc][0x34][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x34][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x34][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x34][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x35][&clk_str_name]="cam_cc_sleep_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x35][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x35][&clk_str_regname]="CAM_CC_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x35][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x35][&clk_reg_cbc]=0xad0c1bc v.a \a_clock_data[&dbg_mux_cam_cc][0x35][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x35][&clk_reg_tc_sel]=0x3f v.a \a_clock_data[&dbg_mux_cam_cc][0x35][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x35][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x35][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x35][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x36][&clk_str_name]="cam_cc_spdm_bps_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x36][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x36][&clk_str_regname]="CAM_CC_SPDM_BPS_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x36][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x36][&clk_reg_cbc]=0xad07034 v.a \a_clock_data[&dbg_mux_cam_cc][0x36][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x36][&clk_reg_tc_sel]=0x2d v.a \a_clock_data[&dbg_mux_cam_cc][0x36][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x36][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x36][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x36][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x37][&clk_str_name]="cam_cc_spdm_ife_0_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x37][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x37][&clk_str_regname]="CAM_CC_SPDM_IFE_0_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x37][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x37][&clk_reg_cbc]=0xad0a034 v.a \a_clock_data[&dbg_mux_cam_cc][0x37][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x37][&clk_reg_tc_sel]=0x31 v.a \a_clock_data[&dbg_mux_cam_cc][0x37][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x37][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x37][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x37][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x38][&clk_str_name]="cam_cc_spdm_ife_0_csid_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x38][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x38][&clk_str_regname]="CAM_CC_SPDM_IFE_0_CSID_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x38][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x38][&clk_reg_cbc]=0xad0a060 v.a \a_clock_data[&dbg_mux_cam_cc][0x38][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x38][&clk_reg_tc_sel]=0x32 v.a \a_clock_data[&dbg_mux_cam_cc][0x38][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x38][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x38][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x38][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x39][&clk_str_name]="cam_cc_spdm_ipe_0_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x39][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x39][&clk_str_regname]="CAM_CC_SPDM_IPE_0_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x39][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x39][&clk_reg_cbc]=0xad08034 v.a \a_clock_data[&dbg_mux_cam_cc][0x39][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x39][&clk_reg_tc_sel]=0x2f v.a \a_clock_data[&dbg_mux_cam_cc][0x39][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x39][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x39][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x39][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x3a][&clk_str_name]="cam_cc_spdm_ipe_1_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x3a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x3a][&clk_str_regname]="CAM_CC_SPDM_IPE_1_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x3a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x3a][&clk_reg_cbc]=0xad0901c v.a \a_clock_data[&dbg_mux_cam_cc][0x3a][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x3a][&clk_reg_tc_sel]=0x30 v.a \a_clock_data[&dbg_mux_cam_cc][0x3a][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x3a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x3a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x3a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x3b][&clk_str_name]="cam_cc_spdm_jpeg_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x3b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x3b][&clk_str_regname]="CAM_CC_SPDM_JPEG_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x3b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x3b][&clk_reg_cbc]=0xad0c06c v.a \a_clock_data[&dbg_mux_cam_cc][0x3b][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x3b][&clk_reg_tc_sel]=0x34 v.a \a_clock_data[&dbg_mux_cam_cc][0x3b][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x3b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x3b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x3b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x3c][&clk_str_name]="csiphy0_cam_cc_debug_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x3c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x3c][&clk_str_regname]="CAM_CC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x3c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x3c][&clk_reg_cbc]=0xad0d008 v.a \a_clock_data[&dbg_mux_cam_cc][0x3c][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x3c][&clk_reg_tc_sel]=0x40 v.a \a_clock_data[&dbg_mux_cam_cc][0x3c][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x3c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x3c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x3c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x3d][&clk_str_name]="csiphy1_cam_cc_debug_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x3d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x3d][&clk_str_regname]="CAM_CC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x3d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x3d][&clk_reg_cbc]=0xad0d008 v.a \a_clock_data[&dbg_mux_cam_cc][0x3d][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x3d][&clk_reg_tc_sel]=0x41 v.a \a_clock_data[&dbg_mux_cam_cc][0x3d][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x3d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x3d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x3d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x3e][&clk_str_name]="csiphy2_cam_cc_debug_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x3e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x3e][&clk_str_regname]="CAM_CC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x3e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x3e][&clk_reg_cbc]=0xad0d008 v.a \a_clock_data[&dbg_mux_cam_cc][0x3e][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x3e][&clk_reg_tc_sel]=0x42 v.a \a_clock_data[&dbg_mux_cam_cc][0x3e][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x3e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x3e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x3e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_cam_cc][0x3f][&clk_str_name]="csiphy3_cam_cc_debug_clk" v.a \a_clock_str[&dbg_mux_cam_cc][0x3f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_cam_cc][0x3f][&clk_str_regname]="CAM_CC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_cam_cc][0x3f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_cam_cc][0x3f][&clk_reg_cbc]=0xad0d008 v.a \a_clock_data[&dbg_mux_cam_cc][0x3f][&clk_reg_tc_mux]=&dbg_mux_cam_cc v.a \a_clock_data[&dbg_mux_cam_cc][0x3f][&clk_reg_tc_sel]=0x43 v.a \a_clock_data[&dbg_mux_cam_cc][0x3f][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_cam_cc][0x3f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_cam_cc][0x3f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_cam_cc][0x3f][&clk_reg_mux_input_en_mask]=0x0 ; DISP_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_disp_cc][0x0][&clk_str_name]="chip_sleep_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x0][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_disp_cc][0x0][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x1][&clk_str_name]="disp_cc_mdss_ahb_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x1][&clk_str_regname]="DISP_CC_MDSS_AHB_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x1][&clk_reg_cbc]=0xaf02080 v.a \a_clock_data[&dbg_mux_disp_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x1][&clk_reg_tc_sel]=0x1f v.a \a_clock_data[&dbg_mux_disp_cc][0x1][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x2][&clk_str_name]="disp_cc_mdss_byte0_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x2][&clk_str_regname]="DISP_CC_MDSS_BYTE0_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x2][&clk_reg_cbc]=0xaf02028 v.a \a_clock_data[&dbg_mux_disp_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x2][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_disp_cc][0x2][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x3][&clk_str_name]="disp_cc_mdss_byte0_intf_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x3][&clk_str_regname]="DISP_CC_MDSS_BYTE0_INTF_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x3][&clk_reg_cbc]=0xaf0202c v.a \a_clock_data[&dbg_mux_disp_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x3][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_disp_cc][0x3][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x4][&clk_str_name]="disp_cc_mdss_byte1_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x4][&clk_str_regname]="DISP_CC_MDSS_BYTE1_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x4][&clk_reg_cbc]=0xaf02030 v.a \a_clock_data[&dbg_mux_disp_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x4][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_disp_cc][0x4][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x5][&clk_str_name]="disp_cc_mdss_byte1_intf_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x5][&clk_str_regname]="DISP_CC_MDSS_BYTE1_INTF_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x5][&clk_reg_cbc]=0xaf02034 v.a \a_clock_data[&dbg_mux_disp_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x5][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_disp_cc][0x5][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x6][&clk_str_name]="disp_cc_mdss_dp_aux_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x6][&clk_str_regname]="DISP_CC_MDSS_DP_AUX_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x6][&clk_reg_cbc]=0xaf02054 v.a \a_clock_data[&dbg_mux_disp_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x6][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_disp_cc][0x6][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x7][&clk_str_name]="disp_cc_mdss_dp_crypto_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x7][&clk_str_regname]="DISP_CC_MDSS_DP_CRYPTO_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x7][&clk_reg_cbc]=0xaf02048 v.a \a_clock_data[&dbg_mux_disp_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x7][&clk_reg_tc_sel]=0x1b v.a \a_clock_data[&dbg_mux_disp_cc][0x7][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x8][&clk_str_name]="disp_cc_mdss_dp_link_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x8][&clk_str_regname]="DISP_CC_MDSS_DP_LINK_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x8][&clk_reg_cbc]=0xaf02040 v.a \a_clock_data[&dbg_mux_disp_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x8][&clk_reg_tc_sel]=0x19 v.a \a_clock_data[&dbg_mux_disp_cc][0x8][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x9][&clk_str_name]="disp_cc_mdss_dp_link_intf_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x9][&clk_str_regname]="DISP_CC_MDSS_DP_LINK_INTF_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x9][&clk_reg_cbc]=0xaf02044 v.a \a_clock_data[&dbg_mux_disp_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x9][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_disp_cc][0x9][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0xa][&clk_str_name]="disp_cc_mdss_dp_pixel1_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0xa][&clk_str_regname]="DISP_CC_MDSS_DP_PIXEL1_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0xa][&clk_reg_cbc]=0xaf02050 v.a \a_clock_data[&dbg_mux_disp_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0xa][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_disp_cc][0xa][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0xb][&clk_str_name]="disp_cc_mdss_dp_pixel_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0xb][&clk_str_regname]="DISP_CC_MDSS_DP_PIXEL_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0xb][&clk_reg_cbc]=0xaf0204c v.a \a_clock_data[&dbg_mux_disp_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0xb][&clk_reg_tc_sel]=0x1c v.a \a_clock_data[&dbg_mux_disp_cc][0xb][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0xc][&clk_str_name]="disp_cc_mdss_esc0_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0xc][&clk_str_regname]="DISP_CC_MDSS_ESC0_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0xc][&clk_reg_cbc]=0xaf02038 v.a \a_clock_data[&dbg_mux_disp_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0xc][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_disp_cc][0xc][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0xd][&clk_str_name]="disp_cc_mdss_esc1_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0xd][&clk_str_regname]="DISP_CC_MDSS_ESC1_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0xd][&clk_reg_cbc]=0xaf0203c v.a \a_clock_data[&dbg_mux_disp_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0xd][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_disp_cc][0xd][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0xe][&clk_str_name]="disp_cc_mdss_mdp_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0xe][&clk_str_regname]="DISP_CC_MDSS_MDP_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0xe][&clk_reg_cbc]=0xaf0200c v.a \a_clock_data[&dbg_mux_disp_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0xe][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_disp_cc][0xe][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0xf][&clk_str_name]="disp_cc_mdss_mdp_lut_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0xf][&clk_str_regname]="DISP_CC_MDSS_MDP_LUT_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0xf][&clk_reg_cbc]=0xaf0201c v.a \a_clock_data[&dbg_mux_disp_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0xf][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_disp_cc][0xf][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x10][&clk_str_name]="disp_cc_mdss_non_gdsc_ahb_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x10][&clk_str_regname]="DISP_CC_MDSS_NON_GDSC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x10][&clk_reg_cbc]=0xaf04004 v.a \a_clock_data[&dbg_mux_disp_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x10][&clk_reg_tc_sel]=0x20 v.a \a_clock_data[&dbg_mux_disp_cc][0x10][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x11][&clk_str_name]="disp_cc_mdss_pclk0_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x11][&clk_str_regname]="DISP_CC_MDSS_PCLK0_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x11][&clk_reg_cbc]=0xaf02004 v.a \a_clock_data[&dbg_mux_disp_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x11][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_disp_cc][0x11][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x12][&clk_str_name]="disp_cc_mdss_pclk1_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x12][&clk_str_regname]="DISP_CC_MDSS_PCLK1_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x12][&clk_reg_cbc]=0xaf02008 v.a \a_clock_data[&dbg_mux_disp_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x12][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_disp_cc][0x12][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x13][&clk_str_name]="disp_cc_mdss_rot_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x13][&clk_str_regname]="DISP_CC_MDSS_ROT_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x13][&clk_reg_cbc]=0xaf02014 v.a \a_clock_data[&dbg_mux_disp_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x13][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_disp_cc][0x13][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x14][&clk_str_name]="disp_cc_mdss_rscc_ahb_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x14][&clk_str_regname]="DISP_CC_MDSS_RSCC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x14][&clk_reg_cbc]=0xaf0400c v.a \a_clock_data[&dbg_mux_disp_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x14][&clk_reg_tc_sel]=0x22 v.a \a_clock_data[&dbg_mux_disp_cc][0x14][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x15][&clk_str_name]="disp_cc_mdss_rscc_vsync_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x15][&clk_str_regname]="DISP_CC_MDSS_RSCC_VSYNC_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x15][&clk_reg_cbc]=0xaf04008 v.a \a_clock_data[&dbg_mux_disp_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x15][&clk_reg_tc_sel]=0x21 v.a \a_clock_data[&dbg_mux_disp_cc][0x15][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x16][&clk_str_name]="disp_cc_mdss_spdm_dp_crypto_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x16][&clk_str_regname]="DISP_CC_MDSS_SPDM_DP_CRYPTO_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x16][&clk_reg_cbc]=0xaf06014 v.a \a_clock_data[&dbg_mux_disp_cc][0x16][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x16][&clk_reg_tc_sel]=0x27 v.a \a_clock_data[&dbg_mux_disp_cc][0x16][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x17][&clk_str_name]="disp_cc_mdss_spdm_dp_pixel1_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x17][&clk_str_regname]="DISP_CC_MDSS_SPDM_DP_PIXEL1_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x17][&clk_reg_cbc]=0xaf0601c v.a \a_clock_data[&dbg_mux_disp_cc][0x17][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x17][&clk_reg_tc_sel]=0x29 v.a \a_clock_data[&dbg_mux_disp_cc][0x17][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x18][&clk_str_name]="disp_cc_mdss_spdm_dp_pixel_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x18][&clk_str_regname]="DISP_CC_MDSS_SPDM_DP_PIXEL_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x18][&clk_reg_cbc]=0xaf06018 v.a \a_clock_data[&dbg_mux_disp_cc][0x18][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x18][&clk_reg_tc_sel]=0x28 v.a \a_clock_data[&dbg_mux_disp_cc][0x18][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x19][&clk_str_name]="disp_cc_mdss_spdm_mdp_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x19][&clk_str_regname]="DISP_CC_MDSS_SPDM_MDP_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x19][&clk_reg_cbc]=0xaf0600c v.a \a_clock_data[&dbg_mux_disp_cc][0x19][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x19][&clk_reg_tc_sel]=0x25 v.a \a_clock_data[&dbg_mux_disp_cc][0x19][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x1a][&clk_str_name]="disp_cc_mdss_spdm_pclk0_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x1a][&clk_str_regname]="DISP_CC_MDSS_SPDM_PCLK0_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x1a][&clk_reg_cbc]=0xaf06004 v.a \a_clock_data[&dbg_mux_disp_cc][0x1a][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x1a][&clk_reg_tc_sel]=0x23 v.a \a_clock_data[&dbg_mux_disp_cc][0x1a][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x1b][&clk_str_name]="disp_cc_mdss_spdm_pclk1_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x1b][&clk_str_regname]="DISP_CC_MDSS_SPDM_PCLK1_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x1b][&clk_reg_cbc]=0xaf06008 v.a \a_clock_data[&dbg_mux_disp_cc][0x1b][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x1b][&clk_reg_tc_sel]=0x24 v.a \a_clock_data[&dbg_mux_disp_cc][0x1b][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x1c][&clk_str_name]="disp_cc_mdss_spdm_rot_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x1c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x1c][&clk_str_regname]="DISP_CC_MDSS_SPDM_ROT_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x1c][&clk_reg_cbc]=0xaf06010 v.a \a_clock_data[&dbg_mux_disp_cc][0x1c][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x1c][&clk_reg_tc_sel]=0x26 v.a \a_clock_data[&dbg_mux_disp_cc][0x1c][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x1d][&clk_str_name]="disp_cc_mdss_vsync_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x1d][&clk_str_regname]="DISP_CC_MDSS_VSYNC_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x1d][&clk_reg_cbc]=0xaf02024 v.a \a_clock_data[&dbg_mux_disp_cc][0x1d][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x1d][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_disp_cc][0x1d][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x1e][&clk_str_name]="disp_cc_sleep_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x1e][&clk_str_regname]="DISP_CC_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x1e][&clk_reg_cbc]=0xaf06078 v.a \a_clock_data[&dbg_mux_disp_cc][0x1e][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x1e][&clk_reg_tc_sel]=0x2b v.a \a_clock_data[&dbg_mux_disp_cc][0x1e][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x1e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x1f][&clk_str_name]="disp_cc_xo_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x1f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_disp_cc][0x1f][&clk_str_regname]="DISP_CC_XO_CBCR" v.a \a_clock_str[&dbg_mux_disp_cc][0x1f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x1f][&clk_reg_cbc]=0xaf0605c v.a \a_clock_data[&dbg_mux_disp_cc][0x1f][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x1f][&clk_reg_tc_sel]=0x2a v.a \a_clock_data[&dbg_mux_disp_cc][0x1f][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x1f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x1f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x1f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x20][&clk_str_name]="dp_phy_pll_link_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x20][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x20][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x20][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x20][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x20][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x20][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_disp_cc][0x20][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x20][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x20][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x20][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x21][&clk_str_name]="dp_phy_pll_vco_div_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x21][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x21][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x21][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x21][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x21][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x21][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x21][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x21][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x21][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x21][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x22][&clk_str_name]="dptx1_phy_pll_link_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x22][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x22][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x22][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x22][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x22][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x22][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_disp_cc][0x22][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x22][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x22][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x22][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x23][&clk_str_name]="dptx1_phy_pll_vco_div_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x23][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x23][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x23][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x23][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x23][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x23][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_disp_cc][0x23][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x23][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x23][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x23][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x24][&clk_str_name]="dptx2_phy_pll_link_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x24][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x24][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x24][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x24][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x24][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x24][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_disp_cc][0x24][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x24][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x24][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x24][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x25][&clk_str_name]="dptx2_phy_pll_vco_div_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x25][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x25][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x25][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x25][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x25][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x25][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_disp_cc][0x25][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x25][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x25][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x25][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x26][&clk_str_name]="dsi0_phy_pll_out_byteclk" v.a \a_clock_str[&dbg_mux_disp_cc][0x26][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x26][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x26][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x26][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x26][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x26][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_disp_cc][0x26][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x26][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x26][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x26][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x27][&clk_str_name]="dsi0_phy_pll_out_dsiclk" v.a \a_clock_str[&dbg_mux_disp_cc][0x27][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x27][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x27][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x27][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x27][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x27][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_disp_cc][0x27][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x27][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x27][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x27][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x28][&clk_str_name]="dsi1_phy_pll_out_byteclk" v.a \a_clock_str[&dbg_mux_disp_cc][0x28][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x28][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x28][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x28][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x28][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x28][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_disp_cc][0x28][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x28][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x28][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x28][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x29][&clk_str_name]="dsi1_phy_pll_out_dsiclk" v.a \a_clock_str[&dbg_mux_disp_cc][0x29][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x29][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x29][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x29][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x29][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x29][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_disp_cc][0x29][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x29][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x29][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x29][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x2a][&clk_str_name]="gpll0_out_main" v.a \a_clock_str[&dbg_mux_disp_cc][0x2a][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2a][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x2a][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2a][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x2a][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_disp_cc][0x2a][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x2a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x2a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x2b][&clk_str_name]="phy_debug0_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x2b][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2b][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x2b][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2b][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x2b][&clk_reg_tc_sel]=0x2c v.a \a_clock_data[&dbg_mux_disp_cc][0x2b][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x2b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x2b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x2c][&clk_str_name]="phy_debug1_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x2c][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2c][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x2c][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2c][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x2c][&clk_reg_tc_sel]=0x2d v.a \a_clock_data[&dbg_mux_disp_cc][0x2c][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x2c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x2c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x2d][&clk_str_name]="phy_debug2_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x2d][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2d][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x2d][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2d][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x2d][&clk_reg_tc_sel]=0x2e v.a \a_clock_data[&dbg_mux_disp_cc][0x2d][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x2d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x2d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x2e][&clk_str_name]="phy_debug3_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x2e][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2e][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x2e][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2e][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x2e][&clk_reg_tc_sel]=0x2f v.a \a_clock_data[&dbg_mux_disp_cc][0x2e][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x2e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x2e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x2f][&clk_str_name]="phy_debug4_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x2f][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2f][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x2f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x2f][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2f][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x2f][&clk_reg_tc_sel]=0x30 v.a \a_clock_data[&dbg_mux_disp_cc][0x2f][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x2f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x2f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x2f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_disp_cc][0x30][&clk_str_name]="phy_debug5_clk" v.a \a_clock_str[&dbg_mux_disp_cc][0x30][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x30][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_disp_cc][0x30][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_disp_cc][0x30][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x30][&clk_reg_tc_mux]=&dbg_mux_disp_cc v.a \a_clock_data[&dbg_mux_disp_cc][0x30][&clk_reg_tc_sel]=0x31 v.a \a_clock_data[&dbg_mux_disp_cc][0x30][&clk_reg_total_div]=0x4 v.a \a_clock_data[&dbg_mux_disp_cc][0x30][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_disp_cc][0x30][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_disp_cc][0x30][&clk_reg_mux_input_en_mask]=0x0 ; DPCC Controller Clock Names v.a \a_clock_str[&dbg_mux_dpcc][0x0][&clk_str_name]="ddrcc_pll_test0_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x0][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x0][&clk_reg_tc_sel]=0x2b v.a \a_clock_data[&dbg_mux_dpcc][0x0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x1][&clk_str_name]="ddrcc_pll_test1_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x1][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x1][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x1][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x1][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x1][&clk_reg_tc_sel]=0x2c v.a \a_clock_data[&dbg_mux_dpcc][0x1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x2][&clk_str_name]="dpcc_cdsp_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x2][&clk_str_regname]="DPC_REG_DPCC_CDSP_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x2][&clk_reg_cbc]=0x90c8048 v.a \a_clock_data[&dbg_mux_dpcc][0x2][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x2][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_dpcc][0x2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x3][&clk_str_name]="dpcc_dcnoc_core_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x3][&clk_str_regname]="DPC_REG_DPCC_DCNOC_CORE_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x3][&clk_reg_cbc]=0x90c80d4 v.a \a_clock_data[&dbg_mux_dpcc][0x3][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x3][&clk_reg_tc_sel]=0x21 v.a \a_clock_data[&dbg_mux_dpcc][0x3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x4][&clk_str_name]="dpcc_dcnoc_src_cbc_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x4][&clk_str_regname]="DPC_REG_DPCC_DCNOC_SRC_CBC_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x4][&clk_reg_cbc]=0x90c80d0 v.a \a_clock_data[&dbg_mux_dpcc][0x4][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x4][&clk_reg_tc_sel]=0x20 v.a \a_clock_data[&dbg_mux_dpcc][0x4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x5][&clk_str_name]="dpcc_ddrss_top_sleep_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x5][&clk_str_regname]="DPC_REG_DPCC_DDRSS_TOP_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x5][&clk_reg_cbc]=0x90c80ec v.a \a_clock_data[&dbg_mux_dpcc][0x5][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x5][&clk_reg_tc_sel]=0x25 v.a \a_clock_data[&dbg_mux_dpcc][0x5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x6][&clk_str_name]="dpcc_ddrss_top_xo_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x6][&clk_str_regname]="DPC_REG_DPCC_DDRSS_TOP_XO_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x6][&clk_reg_cbc]=0x90c80e4 v.a \a_clock_data[&dbg_mux_dpcc][0x6][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x6][&clk_reg_tc_sel]=0x23 v.a \a_clock_data[&dbg_mux_dpcc][0x6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x7][&clk_str_name]="dpcc_gemnoc_shub_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x7][&clk_str_regname]="DPC_REG_DPCC_GEMNOC_SHUB_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x7][&clk_reg_cbc]=0x90c8044 v.a \a_clock_data[&dbg_mux_dpcc][0x7][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x7][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_dpcc][0x7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x8][&clk_str_name]="dpcc_gemnoc_xo_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x8][&clk_str_regname]="DPC_REG_DPCC_GEMNOC_XO_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x8][&clk_reg_cbc]=0x90c8034 v.a \a_clock_data[&dbg_mux_dpcc][0x8][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x8][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_dpcc][0x8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x9][&clk_str_name]="dpcc_gladiator_shub_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x9][&clk_str_regname]="DPC_REG_DPCC_GLADIATOR_SHUB_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x9][&clk_reg_cbc]=0x90c8040 v.a \a_clock_data[&dbg_mux_dpcc][0x9][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x9][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_dpcc][0x9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0xa][&clk_str_name]="dpcc_gpu_clk" v.a \a_clock_str[&dbg_mux_dpcc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0xa][&clk_str_regname]="DPC_REG_DPCC_GPU_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0xa][&clk_reg_cbc]=0x90c804c v.a \a_clock_data[&dbg_mux_dpcc][0xa][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0xa][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_dpcc][0xa][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0xb][&clk_str_name]="dpcc_llcc0_shub_clk" v.a \a_clock_str[&dbg_mux_dpcc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0xb][&clk_str_regname]="DPC_REG_DPCC_LLCC0_SHUB_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0xb][&clk_reg_cbc]=0x90c8038 v.a \a_clock_data[&dbg_mux_dpcc][0xb][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0xb][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_dpcc][0xb][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0xc][&clk_str_name]="dpcc_llcc0_xo_clk" v.a \a_clock_str[&dbg_mux_dpcc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0xc][&clk_str_regname]="DPC_REG_DPCC_LLCC0_XO_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0xc][&clk_reg_cbc]=0x90c802c v.a \a_clock_data[&dbg_mux_dpcc][0xc][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0xc][&clk_reg_tc_sel]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0xc][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0xd][&clk_str_name]="dpcc_llcc1_shub_clk" v.a \a_clock_str[&dbg_mux_dpcc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0xd][&clk_str_regname]="DPC_REG_DPCC_LLCC1_SHUB_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0xd][&clk_reg_cbc]=0x90c803c v.a \a_clock_data[&dbg_mux_dpcc][0xd][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0xd][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_dpcc][0xd][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0xe][&clk_str_name]="dpcc_llcc1_xo_clk" v.a \a_clock_str[&dbg_mux_dpcc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0xe][&clk_str_regname]="DPC_REG_DPCC_LLCC1_XO_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0xe][&clk_reg_cbc]=0x90c8030 v.a \a_clock_data[&dbg_mux_dpcc][0xe][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0xe][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0xe][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0xf][&clk_str_name]="dpcc_mc0_shub_clk" v.a \a_clock_str[&dbg_mux_dpcc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0xf][&clk_str_regname]="DPC_REG_DPCC_MC0_SHUB_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0xf][&clk_reg_cbc]=0x90c8098 v.a \a_clock_data[&dbg_mux_dpcc][0xf][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0xf][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_dpcc][0xf][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x10][&clk_str_name]="dpcc_mc0_sleep_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x10][&clk_str_regname]="DPC_REG_DPCC_MC0_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x10][&clk_reg_cbc]=0x90c8090 v.a \a_clock_data[&dbg_mux_dpcc][0x10][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x10][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_dpcc][0x10][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x11][&clk_str_name]="dpcc_mc0_xo_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x11][&clk_str_regname]="DPC_REG_DPCC_MC0_XO_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x11][&clk_reg_cbc]=0x90c8088 v.a \a_clock_data[&dbg_mux_dpcc][0x11][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x11][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_dpcc][0x11][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x12][&clk_str_name]="dpcc_mc1_shub_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x12][&clk_str_regname]="DPC_REG_DPCC_MC1_SHUB_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x12][&clk_reg_cbc]=0x90c809c v.a \a_clock_data[&dbg_mux_dpcc][0x12][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x12][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_dpcc][0x12][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x13][&clk_str_name]="dpcc_mc1_sleep_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x13][&clk_str_regname]="DPC_REG_DPCC_MC1_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x13][&clk_reg_cbc]=0x90c8094 v.a \a_clock_data[&dbg_mux_dpcc][0x13][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x13][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_dpcc][0x13][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x14][&clk_str_name]="dpcc_mc1_xo_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x14][&clk_str_regname]="DPC_REG_DPCC_MC1_XO_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x14][&clk_reg_cbc]=0x90c808c v.a \a_clock_data[&dbg_mux_dpcc][0x14][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x14][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_dpcc][0x14][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x15][&clk_str_name]="dpcc_mc_atb_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x15][&clk_str_regname]="DPC_REG_DPCC_MC_ATB_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x15][&clk_reg_cbc]=0x90c80a4 v.a \a_clock_data[&dbg_mux_dpcc][0x15][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x15][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_dpcc][0x15][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x16][&clk_str_name]="dpcc_mc_cfg_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x16][&clk_str_regname]="DPC_REG_DPCC_MC_CFG_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x16][&clk_reg_cbc]=0x90c80a0 v.a \a_clock_data[&dbg_mux_dpcc][0x16][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x16][&clk_reg_tc_sel]=0x19 v.a \a_clock_data[&dbg_mux_dpcc][0x16][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x17][&clk_str_name]="dpcc_mccc_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x17][&clk_str_regname]="DPC_REG_DPCC_MCCC_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x17][&clk_reg_cbc]=0x90c80dc v.a \a_clock_data[&dbg_mux_dpcc][0x17][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x17][&clk_reg_tc_sel]=0x22 v.a \a_clock_data[&dbg_mux_dpcc][0x17][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x18][&clk_str_name]="dpcc_mcdma_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x18][&clk_str_regname]="DPC_REG_DPCC_MCDMA_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x18][&clk_reg_cbc]=0x90c806c v.a \a_clock_data[&dbg_mux_dpcc][0x18][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x18][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_dpcc][0x18][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x19][&clk_str_name]="dpcc_mdsp_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x19][&clk_str_regname]="DPC_REG_DPCC_MDSP_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x19][&clk_reg_cbc]=0x90c8050 v.a \a_clock_data[&dbg_mux_dpcc][0x19][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x19][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_dpcc][0x19][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x1a][&clk_str_name]="dpcc_mnoc_hf_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x1a][&clk_str_regname]="DPC_REG_DPCC_MNOC_HF_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x1a][&clk_reg_cbc]=0x90c8054 v.a \a_clock_data[&dbg_mux_dpcc][0x1a][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x1a][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_dpcc][0x1a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x1b][&clk_str_name]="dpcc_mnoc_sf_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x1b][&clk_str_regname]="DPC_REG_DPCC_MNOC_SF_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x1b][&clk_reg_cbc]=0x90c8058 v.a \a_clock_data[&dbg_mux_dpcc][0x1b][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x1b][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_dpcc][0x1b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x1c][&clk_str_name]="dpcc_phy_sleep_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x1c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x1c][&clk_str_regname]="DPC_REG_DPCC_PHY_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x1c][&clk_reg_cbc]=0x90c80bc v.a \a_clock_data[&dbg_mux_dpcc][0x1c][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x1c][&clk_reg_tc_sel]=0x1c v.a \a_clock_data[&dbg_mux_dpcc][0x1c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x1d][&clk_str_name]="dpcc_phy_xo_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x1d][&clk_str_regname]="DPC_REG_DPCC_PHY_XO_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x1d][&clk_reg_cbc]=0x90c80b8 v.a \a_clock_data[&dbg_mux_dpcc][0x1d][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x1d][&clk_reg_tc_sel]=0x1b v.a \a_clock_data[&dbg_mux_dpcc][0x1d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x1e][&clk_str_name]="dpcc_pscbc_shrm_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x1e][&clk_str_regname]="DPC_REG_DPCC_PSCBC_SHRM_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x1e][&clk_reg_cbc]=0x90c80cc v.a \a_clock_data[&dbg_mux_dpcc][0x1e][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x1e][&clk_reg_tc_sel]=0x1f v.a \a_clock_data[&dbg_mux_dpcc][0x1e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x1e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x1f][&clk_str_name]="dpcc_shrm_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x1f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x1f][&clk_str_regname]="DPC_REG_DPCC_SHRM_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x1f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x1f][&clk_reg_cbc]=0x90c80c8 v.a \a_clock_data[&dbg_mux_dpcc][0x1f][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x1f][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_dpcc][0x1f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x1f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x1f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x1f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x20][&clk_str_name]="dpcc_shrm_xo_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x20][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x20][&clk_str_regname]="DPC_REG_DPCC_SHRM_XO_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x20][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x20][&clk_reg_cbc]=0x90c80c4 v.a \a_clock_data[&dbg_mux_dpcc][0x20][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x20][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_dpcc][0x20][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x20][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x20][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x20][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x21][&clk_str_name]="dpcc_shub_atb_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x21][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x21][&clk_str_regname]="DPC_REG_DPCC_SHUB_ATB_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x21][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x21][&clk_reg_cbc]=0x90c8074 v.a \a_clock_data[&dbg_mux_dpcc][0x21][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x21][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_dpcc][0x21][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x21][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x21][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x21][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x22][&clk_str_name]="dpcc_shub_cfg_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x22][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x22][&clk_str_regname]="DPC_REG_DPCC_SHUB_CFG_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x22][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x22][&clk_reg_cbc]=0x90c8068 v.a \a_clock_data[&dbg_mux_dpcc][0x22][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x22][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_dpcc][0x22][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x22][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x22][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x22][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x23][&clk_str_name]="dpcc_snoc_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x23][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x23][&clk_str_regname]="DPC_REG_DPCC_SNOC_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x23][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x23][&clk_reg_cbc]=0x90c805c v.a \a_clock_data[&dbg_mux_dpcc][0x23][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x23][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_dpcc][0x23][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x23][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x23][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x23][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x24][&clk_str_name]="dpcc_snoc_gc_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x24][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x24][&clk_str_regname]="DPC_REG_DPCC_SNOC_GC_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x24][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x24][&clk_reg_cbc]=0x90c8070 v.a \a_clock_data[&dbg_mux_dpcc][0x24][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x24][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_dpcc][0x24][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x24][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x24][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x24][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x25][&clk_str_name]="dpcc_snoc_hs_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x25][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x25][&clk_str_regname]="DPC_REG_DPCC_SNOC_HS_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x25][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x25][&clk_reg_cbc]=0x90c8060 v.a \a_clock_data[&dbg_mux_dpcc][0x25][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x25][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_dpcc][0x25][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x25][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x25][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x25][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x26][&clk_str_name]="dpcc_tcu_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x26][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x26][&clk_str_regname]="DPC_REG_DPCC_TCU_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x26][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x26][&clk_reg_cbc]=0x90c8064 v.a \a_clock_data[&dbg_mux_dpcc][0x26][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x26][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_dpcc][0x26][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x26][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x26][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x26][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x27][&clk_str_name]="dpcc_tgu_xo_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x27][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_dpcc][0x27][&clk_str_regname]="DPC_REG_DPCC_TGU_XO_CBCR" v.a \a_clock_str[&dbg_mux_dpcc][0x27][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x27][&clk_reg_cbc]=0x90c80e8 v.a \a_clock_data[&dbg_mux_dpcc][0x27][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x27][&clk_reg_tc_sel]=0x24 v.a \a_clock_data[&dbg_mux_dpcc][0x27][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x27][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x27][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x27][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x28][&clk_str_name]="mccc_debug0_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x28][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x28][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x28][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x28][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x28][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x28][&clk_reg_tc_sel]=0x26 v.a \a_clock_data[&dbg_mux_dpcc][0x28][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x28][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x28][&clk_reg_mux_input_en_addr]=0x90b0270 v.a \a_clock_data[&dbg_mux_dpcc][0x28][&clk_reg_mux_input_en_mask]=0x1 v.a \a_clock_str[&dbg_mux_dpcc][0x29][&clk_str_name]="mccc_debug1_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x29][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x29][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x29][&clk_str_aliases]="dpcc_ddr_ch0_clk" v.a \a_clock_data[&dbg_mux_dpcc][0x29][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x29][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x29][&clk_reg_tc_sel]=0x27 v.a \a_clock_data[&dbg_mux_dpcc][0x29][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x29][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x29][&clk_reg_mux_input_en_addr]=0x9250100 v.a \a_clock_data[&dbg_mux_dpcc][0x29][&clk_reg_mux_input_en_mask]=0x1 v.a \a_clock_str[&dbg_mux_dpcc][0x2a][&clk_str_name]="mccc_debug2_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x2a][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2a][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2a][&clk_str_aliases]="dpcc_ddr_ch1_clk" v.a \a_clock_data[&dbg_mux_dpcc][0x2a][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2a][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x2a][&clk_reg_tc_sel]=0x28 v.a \a_clock_data[&dbg_mux_dpcc][0x2a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x2a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x2a][&clk_reg_mux_input_en_addr]=0x92d0100 v.a \a_clock_data[&dbg_mux_dpcc][0x2a][&clk_reg_mux_input_en_mask]=0x1 v.a \a_clock_str[&dbg_mux_dpcc][0x2b][&clk_str_name]="mccc_debug3_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x2b][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2b][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x2b][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2b][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x2b][&clk_reg_tc_sel]=0x29 v.a \a_clock_data[&dbg_mux_dpcc][0x2b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x2b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x2b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x2c][&clk_str_name]="mccc_debug4_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x2c][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2c][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x2c][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2c][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x2c][&clk_reg_tc_sel]=0x2a v.a \a_clock_data[&dbg_mux_dpcc][0x2c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x2c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x2c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x2d][&clk_str_name]="mccc_pll_test2_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x2d][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2d][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x2d][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2d][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x2d][&clk_reg_tc_sel]=0x2d v.a \a_clock_data[&dbg_mux_dpcc][0x2d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x2d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x2d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x2e][&clk_str_name]="mccc_pll_test3_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x2e][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2e][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x2e][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2e][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x2e][&clk_reg_tc_sel]=0x2e v.a \a_clock_data[&dbg_mux_dpcc][0x2e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x2e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x2e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x2f][&clk_str_name]="mccc_pll_test4_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x2f][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2f][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x2f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x2f][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2f][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x2f][&clk_reg_tc_sel]=0x2f v.a \a_clock_data[&dbg_mux_dpcc][0x2f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x2f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x2f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x2f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x30][&clk_str_name]="mccc_pll_test5_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x30][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x30][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x30][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x30][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x30][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x30][&clk_reg_tc_sel]=0x30 v.a \a_clock_data[&dbg_mux_dpcc][0x30][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x30][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x30][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x30][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x31][&clk_str_name]="mccc_pll_test6_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x31][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x31][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x31][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x31][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x31][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x31][&clk_reg_tc_sel]=0x31 v.a \a_clock_data[&dbg_mux_dpcc][0x31][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x31][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x31][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x31][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x32][&clk_str_name]="mccc_pll_test7_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x32][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x32][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x32][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x32][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x32][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x32][&clk_reg_tc_sel]=0x32 v.a \a_clock_data[&dbg_mux_dpcc][0x32][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x32][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x32][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x32][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x33][&clk_str_name]="mccc_pll_test8_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x33][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x33][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x33][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x33][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x33][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x33][&clk_reg_tc_sel]=0x33 v.a \a_clock_data[&dbg_mux_dpcc][0x33][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x33][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x33][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x33][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_dpcc][0x34][&clk_str_name]="mccc_pll_test9_clk" v.a \a_clock_str[&dbg_mux_dpcc][0x34][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x34][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_dpcc][0x34][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_dpcc][0x34][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x34][&clk_reg_tc_mux]=&dbg_mux_dpcc v.a \a_clock_data[&dbg_mux_dpcc][0x34][&clk_reg_tc_sel]=0x34 v.a \a_clock_data[&dbg_mux_dpcc][0x34][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_dpcc][0x34][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_dpcc][0x34][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_dpcc][0x34][&clk_reg_mux_input_en_mask]=0x0 ; GCC Controller Clock Names v.a \a_clock_str[&dbg_mux_gcc][0x0][&clk_str_name]="aoss_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x0][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x0][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x0][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x0][&clk_reg_tc_sel]=0xa2 v.a \a_clock_data[&dbg_mux_gcc][0x0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x1][&clk_str_name]="aud_ref_clk" v.a \a_clock_str[&dbg_mux_gcc][0x1][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x1][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x1][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x1][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x1][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_gcc][0x1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x2][&clk_str_name]="bi_tcxo" v.a \a_clock_str[&dbg_mux_gcc][0x2][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x2][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x2][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x2][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x2][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x3][&clk_str_name]="camera_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x3][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x3][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x3][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x3][&clk_reg_tc_sel]=0x4f v.a \a_clock_data[&dbg_mux_gcc][0x3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x4][&clk_str_name]="core_bi_pll_test_se" v.a \a_clock_str[&dbg_mux_gcc][0x4][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x4][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x4][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x4][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x4][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_gcc][0x4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x5][&clk_str_name]="core_pi_sleep_clk" v.a \a_clock_str[&dbg_mux_gcc][0x5][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x5][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x5][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x5][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x5][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_gcc][0x5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x6][&clk_str_name]="cpuss_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x6][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x6][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x6][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x6][&clk_reg_tc_sel]=0xdb v.a \a_clock_data[&dbg_mux_gcc][0x6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x7][&clk_str_name]="ddrss_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x7][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x7][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x7][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x7][&clk_reg_tc_sel]=0xc5 v.a \a_clock_data[&dbg_mux_gcc][0x7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x8][&clk_str_name]="gcc_aggre_cnoc_periph_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x8][&clk_str_regname]="GCC_AGGRE_CNOC_PERIPH_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x8][&clk_reg_cbc]=0x18229c v.a \a_clock_data[&dbg_mux_gcc][0x8][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x8][&clk_reg_tc_sel]=0x10c v.a \a_clock_data[&dbg_mux_gcc][0x8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x9][&clk_str_name]="gcc_aggre_cnoc_periph_north_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x9][&clk_str_regname]="GCC_AGGRE_CNOC_PERIPH_NORTH_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x9][&clk_reg_cbc]=0x182010 v.a \a_clock_data[&dbg_mux_gcc][0x9][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x9][&clk_reg_tc_sel]=0x100 v.a \a_clock_data[&dbg_mux_gcc][0x9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xa][&clk_str_name]="gcc_aggre_cnoc_periph_southwest_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xa][&clk_str_regname]="GCC_AGGRE_CNOC_PERIPH_SOUTHWEST_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xa][&clk_reg_cbc]=0x182014 v.a \a_clock_data[&dbg_mux_gcc][0xa][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xa][&clk_reg_tc_sel]=0x101 v.a \a_clock_data[&dbg_mux_gcc][0xa][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xb][&clk_str_name]="gcc_aggre_noc_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xb][&clk_str_regname]="GCC_AGGRE_NOC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xb][&clk_reg_cbc]=0x182008 v.a \a_clock_data[&dbg_mux_gcc][0xb][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xb][&clk_reg_tc_sel]=0xfe v.a \a_clock_data[&dbg_mux_gcc][0xb][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xc][&clk_str_name]="gcc_aggre_noc_audio_tbu_clk" v.a \a_clock_str[&dbg_mux_gcc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xc][&clk_str_regname]="GCC_AGGRE_NOC_AUDIO_TBU_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xc][&clk_reg_cbc]=0x190004 v.a \a_clock_data[&dbg_mux_gcc][0xc][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xc][&clk_reg_tc_sel]=0x32 v.a \a_clock_data[&dbg_mux_gcc][0xc][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xd][&clk_str_name]="gcc_aggre_noc_cdsp_noc_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xd][&clk_str_regname]="GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xd][&clk_reg_cbc]=0x145164 v.a \a_clock_data[&dbg_mux_gcc][0xd][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xd][&clk_reg_tc_sel]=0x10b v.a \a_clock_data[&dbg_mux_gcc][0xd][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xe][&clk_str_name]="gcc_aggre_noc_center_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xe][&clk_str_regname]="GCC_AGGRE_NOC_CENTER_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xe][&clk_reg_cbc]=0x182020 v.a \a_clock_data[&dbg_mux_gcc][0xe][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xe][&clk_reg_tc_sel]=0x104 v.a \a_clock_data[&dbg_mux_gcc][0xe][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xf][&clk_str_name]="gcc_aggre_noc_compute_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xf][&clk_str_regname]="GCC_AGGRE_NOC_COMPUTE_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xf][&clk_reg_cbc]=0x18200c v.a \a_clock_data[&dbg_mux_gcc][0xf][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xf][&clk_reg_tc_sel]=0xff v.a \a_clock_data[&dbg_mux_gcc][0xf][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x10][&clk_str_name]="gcc_aggre_noc_ipa_clk" v.a \a_clock_str[&dbg_mux_gcc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x10][&clk_str_regname]="GCC_AGGRE_NOC_IPA_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x10][&clk_reg_cbc]=0x189164 v.a \a_clock_data[&dbg_mux_gcc][0x10][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x10][&clk_reg_tc_sel]=0x10a v.a \a_clock_data[&dbg_mux_gcc][0x10][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x11][&clk_str_name]="gcc_aggre_noc_north_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x11][&clk_str_regname]="GCC_AGGRE_NOC_NORTH_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x11][&clk_reg_cbc]=0x18202c v.a \a_clock_data[&dbg_mux_gcc][0x11][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x11][&clk_reg_tc_sel]=0x107 v.a \a_clock_data[&dbg_mux_gcc][0x11][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x12][&clk_str_name]="gcc_aggre_noc_qosgen_extref_clk" v.a \a_clock_str[&dbg_mux_gcc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x12][&clk_str_regname]="GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x12][&clk_reg_cbc]=0x18201c v.a \a_clock_data[&dbg_mux_gcc][0x12][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x12][&clk_reg_tc_sel]=0x103 v.a \a_clock_data[&dbg_mux_gcc][0x12][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x13][&clk_str_name]="gcc_aggre_noc_sf_center_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x13][&clk_str_regname]="GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x13][&clk_reg_cbc]=0x182018 v.a \a_clock_data[&dbg_mux_gcc][0x13][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x13][&clk_reg_tc_sel]=0x102 v.a \a_clock_data[&dbg_mux_gcc][0x13][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x14][&clk_str_name]="gcc_aggre_noc_south_ahb_cfg_clk" v.a \a_clock_str[&dbg_mux_gcc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x14][&clk_str_regname]="GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x14][&clk_reg_cbc]=0x182004 v.a \a_clock_data[&dbg_mux_gcc][0x14][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x14][&clk_reg_tc_sel]=0xfd v.a \a_clock_data[&dbg_mux_gcc][0x14][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x15][&clk_str_name]="gcc_aggre_noc_south_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x15][&clk_str_regname]="GCC_AGGRE_NOC_SOUTH_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x15][&clk_reg_cbc]=0x182028 v.a \a_clock_data[&dbg_mux_gcc][0x15][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x15][&clk_reg_tc_sel]=0x106 v.a \a_clock_data[&dbg_mux_gcc][0x15][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x16][&clk_str_name]="gcc_aggre_noc_tbu1_clk" v.a \a_clock_str[&dbg_mux_gcc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x16][&clk_str_regname]="GCC_AGGRE_NOC_TBU1_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x16][&clk_reg_cbc]=0x19000c v.a \a_clock_data[&dbg_mux_gcc][0x16][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x16][&clk_reg_tc_sel]=0x33 v.a \a_clock_data[&dbg_mux_gcc][0x16][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x17][&clk_str_name]="gcc_aggre_noc_tbu2_clk" v.a \a_clock_str[&dbg_mux_gcc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x17][&clk_str_regname]="GCC_AGGRE_NOC_TBU2_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x17][&clk_reg_cbc]=0x190014 v.a \a_clock_data[&dbg_mux_gcc][0x17][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x17][&clk_reg_tc_sel]=0x34 v.a \a_clock_data[&dbg_mux_gcc][0x17][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x18][&clk_str_name]="gcc_aggre_noc_west_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x18][&clk_str_regname]="GCC_AGGRE_NOC_WEST_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x18][&clk_reg_cbc]=0x182024 v.a \a_clock_data[&dbg_mux_gcc][0x18][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x18][&clk_reg_tc_sel]=0x105 v.a \a_clock_data[&dbg_mux_gcc][0x18][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x19][&clk_str_name]="gcc_aggre_noc_wlan_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x19][&clk_str_regname]="GCC_AGGRE_NOC_WLAN_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x19][&clk_reg_cbc]=0x1822a4 v.a \a_clock_data[&dbg_mux_gcc][0x19][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x19][&clk_reg_tc_sel]=0x10d v.a \a_clock_data[&dbg_mux_gcc][0x19][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x1a][&clk_str_name]="gcc_aggre_ufs_phy_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x1a][&clk_str_regname]="GCC_AGGRE_UFS_PHY_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x1a][&clk_reg_cbc]=0x1770cc v.a \a_clock_data[&dbg_mux_gcc][0x1a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x1a][&clk_reg_tc_sel]=0x109 v.a \a_clock_data[&dbg_mux_gcc][0x1a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x1b][&clk_str_name]="gcc_aggre_usb3_prim_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x1b][&clk_str_regname]="GCC_AGGRE_USB3_PRIM_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x1b][&clk_reg_cbc]=0x10f080 v.a \a_clock_data[&dbg_mux_gcc][0x1b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x1b][&clk_reg_tc_sel]=0x108 v.a \a_clock_data[&dbg_mux_gcc][0x1b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x1c][&clk_str_name]="gcc_ahb2phy0_clk" v.a \a_clock_str[&dbg_mux_gcc][0x1c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x1c][&clk_str_regname]="GCC_AHB2PHY0_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x1c][&clk_reg_cbc]=0x107004 v.a \a_clock_data[&dbg_mux_gcc][0x1c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x1c][&clk_reg_tc_sel]=0x131 v.a \a_clock_data[&dbg_mux_gcc][0x1c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x1d][&clk_str_name]="gcc_ahb2phy2_cfg_clk" v.a \a_clock_str[&dbg_mux_gcc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x1d][&clk_str_regname]="GCC_AHB2PHY2_CFG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x1d][&clk_reg_cbc]=0x16a004 v.a \a_clock_data[&dbg_mux_gcc][0x1d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x1d][&clk_reg_tc_sel]=0x7b v.a \a_clock_data[&dbg_mux_gcc][0x1d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x1e][&clk_str_name]="gcc_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x1e][&clk_str_regname]="GCC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x1e][&clk_reg_cbc]=0x143000 v.a \a_clock_data[&dbg_mux_gcc][0x1e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x1e][&clk_reg_tc_sel]=0xb0 v.a \a_clock_data[&dbg_mux_gcc][0x1e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x1e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x1f][&clk_str_name]="gcc_aoss_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0x1f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x1f][&clk_str_regname]="GCC_AOSS_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x1f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x1f][&clk_reg_cbc]=0x13c00c v.a \a_clock_data[&dbg_mux_gcc][0x1f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x1f][&clk_reg_tc_sel]=0xa1 v.a \a_clock_data[&dbg_mux_gcc][0x1f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x1f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x1f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x1f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x20][&clk_str_name]="gcc_aoss_cnoc_m_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x20][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x20][&clk_str_regname]="GCC_AOSS_CNOC_M_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x20][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x20][&clk_reg_cbc]=0x13c004 v.a \a_clock_data[&dbg_mux_gcc][0x20][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x20][&clk_reg_tc_sel]=0x9f v.a \a_clock_data[&dbg_mux_gcc][0x20][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x20][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x20][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x20][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x21][&clk_str_name]="gcc_aoss_cnoc_s_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x21][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x21][&clk_str_regname]="GCC_AOSS_CNOC_S_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x21][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x21][&clk_reg_cbc]=0x13c008 v.a \a_clock_data[&dbg_mux_gcc][0x21][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x21][&clk_reg_tc_sel]=0xa0 v.a \a_clock_data[&dbg_mux_gcc][0x21][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x21][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x21][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x21][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x22][&clk_str_name]="gcc_apb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x22][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x22][&clk_str_regname]="GCC_APB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x22][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x22][&clk_reg_cbc]=0x10c03c v.a \a_clock_data[&dbg_mux_gcc][0x22][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x22][&clk_reg_tc_sel]=0x6d v.a \a_clock_data[&dbg_mux_gcc][0x22][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x22][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x22][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x22][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x23][&clk_str_name]="gcc_apc_vs_clk" v.a \a_clock_str[&dbg_mux_gcc][0x23][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x23][&clk_str_regname]="GCC_APC_VS_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x23][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x23][&clk_reg_cbc]=0x17a050 v.a \a_clock_data[&dbg_mux_gcc][0x23][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x23][&clk_reg_tc_sel]=0xfa v.a \a_clock_data[&dbg_mux_gcc][0x23][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x23][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x23][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x23][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x24][&clk_str_name]="gcc_apss_qdss_apb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x24][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x24][&clk_str_regname]="GCC_APSS_QDSS_APB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x24][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x24][&clk_reg_cbc]=0x148060 v.a \a_clock_data[&dbg_mux_gcc][0x24][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x24][&clk_reg_tc_sel]=0xda v.a \a_clock_data[&dbg_mux_gcc][0x24][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x24][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x24][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x24][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x25][&clk_str_name]="gcc_apss_qdss_tsctr_clk" v.a \a_clock_str[&dbg_mux_gcc][0x25][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x25][&clk_str_regname]="GCC_APSS_QDSS_TSCTR_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x25][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x25][&clk_reg_cbc]=0x14805c v.a \a_clock_data[&dbg_mux_gcc][0x25][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x25][&clk_reg_tc_sel]=0xd9 v.a \a_clock_data[&dbg_mux_gcc][0x25][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x25][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x25][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x25][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x26][&clk_str_name]="gcc_boot_rom_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x26][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x26][&clk_str_regname]="GCC_BOOT_ROM_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x26][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x26][&clk_reg_cbc]=0x138004 v.a \a_clock_data[&dbg_mux_gcc][0x26][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x26][&clk_reg_tc_sel]=0x99 v.a \a_clock_data[&dbg_mux_gcc][0x26][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x26][&clk_reg_vote_bit]=0xa v.a \a_clock_data[&dbg_mux_gcc][0x26][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x26][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x27][&clk_str_name]="gcc_camera_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x27][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x27][&clk_str_regname]="GCC_CAMERA_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x27][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x27][&clk_reg_cbc]=0x10b008 v.a \a_clock_data[&dbg_mux_gcc][0x27][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x27][&clk_reg_tc_sel]=0x3f v.a \a_clock_data[&dbg_mux_gcc][0x27][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x27][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x27][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x27][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x28][&clk_str_name]="gcc_camera_hf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x28][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x28][&clk_str_regname]="GCC_CAMERA_HF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x28][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x28][&clk_reg_cbc]=0x10b028 v.a \a_clock_data[&dbg_mux_gcc][0x28][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x28][&clk_reg_tc_sel]=0x47 v.a \a_clock_data[&dbg_mux_gcc][0x28][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x28][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x28][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x28][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x29][&clk_str_name]="gcc_camera_sf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x29][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x29][&clk_str_regname]="GCC_CAMERA_SF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x29][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x29][&clk_reg_cbc]=0x10b02c v.a \a_clock_data[&dbg_mux_gcc][0x29][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x29][&clk_reg_tc_sel]=0x48 v.a \a_clock_data[&dbg_mux_gcc][0x29][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x29][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x29][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x29][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x2a][&clk_str_name]="gcc_camera_throttle_hf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x2a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x2a][&clk_str_regname]="GCC_CAMERA_THROTTLE_HF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x2a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x2a][&clk_reg_cbc]=0x10b074 v.a \a_clock_data[&dbg_mux_gcc][0x2a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x2a][&clk_reg_tc_sel]=0x57 v.a \a_clock_data[&dbg_mux_gcc][0x2a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x2a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x2a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x2a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x2b][&clk_str_name]="gcc_camera_throttle_sf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x2b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x2b][&clk_str_regname]="GCC_CAMERA_THROTTLE_SF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x2b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x2b][&clk_reg_cbc]=0x10b078 v.a \a_clock_data[&dbg_mux_gcc][0x2b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x2b][&clk_reg_tc_sel]=0x58 v.a \a_clock_data[&dbg_mux_gcc][0x2b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x2b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x2b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x2b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x2c][&clk_str_name]="gcc_camera_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x2c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x2c][&clk_str_regname]="GCC_CAMERA_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x2c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x2c][&clk_reg_cbc]=0x10b03c v.a \a_clock_data[&dbg_mux_gcc][0x2c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x2c][&clk_reg_tc_sel]=0x4c v.a \a_clock_data[&dbg_mux_gcc][0x2c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x2c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x2c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x2c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x2d][&clk_str_name]="gcc_ce1_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x2d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x2d][&clk_str_regname]="GCC_CE1_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x2d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x2d][&clk_reg_cbc]=0x14100c v.a \a_clock_data[&dbg_mux_gcc][0x2d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x2d][&clk_reg_tc_sel]=0xaf v.a \a_clock_data[&dbg_mux_gcc][0x2d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x2d][&clk_reg_vote_bit]=0x3 v.a \a_clock_data[&dbg_mux_gcc][0x2d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x2d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x2e][&clk_str_name]="gcc_ce1_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x2e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x2e][&clk_str_regname]="GCC_CE1_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x2e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x2e][&clk_reg_cbc]=0x141008 v.a \a_clock_data[&dbg_mux_gcc][0x2e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x2e][&clk_reg_tc_sel]=0xae v.a \a_clock_data[&dbg_mux_gcc][0x2e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x2e][&clk_reg_vote_bit]=0x4 v.a \a_clock_data[&dbg_mux_gcc][0x2e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x2e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x2f][&clk_str_name]="gcc_ce1_clk" v.a \a_clock_str[&dbg_mux_gcc][0x2f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x2f][&clk_str_regname]="GCC_CE1_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x2f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x2f][&clk_reg_cbc]=0x141004 v.a \a_clock_data[&dbg_mux_gcc][0x2f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x2f][&clk_reg_tc_sel]=0xad v.a \a_clock_data[&dbg_mux_gcc][0x2f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x2f][&clk_reg_vote_bit]=0x5 v.a \a_clock_data[&dbg_mux_gcc][0x2f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x2f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x30][&clk_str_name]="gcc_cfg_noc_ah2phy_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x30][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x30][&clk_str_regname]="GCC_CFG_NOC_AH2PHY_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x30][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x30][&clk_reg_cbc]=0x10503c v.a \a_clock_data[&dbg_mux_gcc][0x30][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x30][&clk_reg_tc_sel]=0x22 v.a \a_clock_data[&dbg_mux_gcc][0x30][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x30][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x30][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x30][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x31][&clk_str_name]="gcc_cfg_noc_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x31][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x31][&clk_str_regname]="GCC_CFG_NOC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x31][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x31][&clk_reg_cbc]=0x10500c v.a \a_clock_data[&dbg_mux_gcc][0x31][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x31][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_gcc][0x31][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x31][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x31][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x31][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x32][&clk_str_name]="gcc_cfg_noc_compute_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x32][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x32][&clk_str_regname]="GCC_CFG_NOC_COMPUTE_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x32][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x32][&clk_reg_cbc]=0x105024 v.a \a_clock_data[&dbg_mux_gcc][0x32][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x32][&clk_reg_tc_sel]=0x1b v.a \a_clock_data[&dbg_mux_gcc][0x32][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x32][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x32][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x32][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x33][&clk_str_name]="gcc_cfg_noc_east_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x33][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x33][&clk_str_regname]="GCC_CFG_NOC_EAST_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x33][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x33][&clk_reg_cbc]=0x1053f8 v.a \a_clock_data[&dbg_mux_gcc][0x33][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x33][&clk_reg_tc_sel]=0x28 v.a \a_clock_data[&dbg_mux_gcc][0x33][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x33][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x33][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x33][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x34][&clk_str_name]="gcc_cfg_noc_lpass_clk" v.a \a_clock_str[&dbg_mux_gcc][0x34][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x34][&clk_str_regname]="GCC_CFG_NOC_LPASS_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x34][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x34][&clk_reg_cbc]=0x147014 v.a \a_clock_data[&dbg_mux_gcc][0x34][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x34][&clk_reg_tc_sel]=0x27 v.a \a_clock_data[&dbg_mux_gcc][0x34][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x34][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x34][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x34][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x35][&clk_str_name]="gcc_cfg_noc_mmnoc_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x35][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x35][&clk_str_regname]="GCC_CFG_NOC_MMNOC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x35][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x35][&clk_reg_cbc]=0x105020 v.a \a_clock_data[&dbg_mux_gcc][0x35][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x35][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_gcc][0x35][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x35][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x35][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x35][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x36][&clk_str_name]="gcc_cfg_noc_monaq_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x36][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x36][&clk_str_regname]="GCC_CFG_NOC_MONAQ_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x36][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x36][&clk_reg_cbc]=0x10501c v.a \a_clock_data[&dbg_mux_gcc][0x36][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x36][&clk_reg_tc_sel]=0x19 v.a \a_clock_data[&dbg_mux_gcc][0x36][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x36][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x36][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x36][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x37][&clk_str_name]="gcc_cfg_noc_north_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x37][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x37][&clk_str_regname]="GCC_CFG_NOC_NORTH_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x37][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x37][&clk_reg_cbc]=0x105014 v.a \a_clock_data[&dbg_mux_gcc][0x37][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x37][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_gcc][0x37][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x37][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x37][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x37][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x38][&clk_str_name]="gcc_cfg_noc_southwest_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x38][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x38][&clk_str_regname]="GCC_CFG_NOC_SOUTHWEST_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x38][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x38][&clk_reg_cbc]=0x105018 v.a \a_clock_data[&dbg_mux_gcc][0x38][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x38][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_gcc][0x38][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x38][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x38][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x38][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x39][&clk_str_name]="gcc_cfg_noc_usb3_prim_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x39][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x39][&clk_str_regname]="GCC_CFG_NOC_USB3_PRIM_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x39][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x39][&clk_reg_cbc]=0x10f07c v.a \a_clock_data[&dbg_mux_gcc][0x39][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x39][&clk_reg_tc_sel]=0x1c v.a \a_clock_data[&dbg_mux_gcc][0x39][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x39][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x39][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x39][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x3a][&clk_str_name]="gcc_cfg_noc_west_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x3a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x3a][&clk_str_regname]="GCC_CFG_NOC_WEST_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x3a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x3a][&clk_reg_cbc]=0x105010 v.a \a_clock_data[&dbg_mux_gcc][0x3a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x3a][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_gcc][0x3a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x3a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x3a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x3a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x3b][&clk_str_name]="gcc_cm_phy_refgen1_clk" v.a \a_clock_str[&dbg_mux_gcc][0x3b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x3b][&clk_str_regname]="GCC_CM_PHY_REFGEN1_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x3b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x3b][&clk_reg_cbc]=0x122004 v.a \a_clock_data[&dbg_mux_gcc][0x3b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x3b][&clk_reg_tc_sel]=0x132 v.a \a_clock_data[&dbg_mux_gcc][0x3b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x3b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x3b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x3b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x3c][&clk_str_name]="gcc_cm_phy_refgen2_clk" v.a \a_clock_str[&dbg_mux_gcc][0x3c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x3c][&clk_str_regname]="GCC_CM_PHY_REFGEN2_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x3c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x3c][&clk_reg_cbc]=0x124004 v.a \a_clock_data[&dbg_mux_gcc][0x3c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x3c][&clk_reg_tc_sel]=0x133 v.a \a_clock_data[&dbg_mux_gcc][0x3c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x3c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x3c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x3c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x3d][&clk_str_name]="gcc_cnoc_periph_clk" v.a \a_clock_str[&dbg_mux_gcc][0x3d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x3d][&clk_str_regname]="GCC_CNOC_PERIPH_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x3d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x3d][&clk_reg_cbc]=0x10504c v.a \a_clock_data[&dbg_mux_gcc][0x3d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x3d][&clk_reg_tc_sel]=0x26 v.a \a_clock_data[&dbg_mux_gcc][0x3d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x3d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x3d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x3d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x3e][&clk_str_name]="gcc_cnoc_periph_north_clk" v.a \a_clock_str[&dbg_mux_gcc][0x3e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x3e][&clk_str_regname]="GCC_CNOC_PERIPH_NORTH_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x3e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x3e][&clk_reg_cbc]=0x105008 v.a \a_clock_data[&dbg_mux_gcc][0x3e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x3e][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_gcc][0x3e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x3e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x3e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x3e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x3f][&clk_str_name]="gcc_cnoc_periph_southwest_clk" v.a \a_clock_str[&dbg_mux_gcc][0x3f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x3f][&clk_str_regname]="GCC_CNOC_PERIPH_SOUTHWEST_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x3f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x3f][&clk_reg_cbc]=0x105004 v.a \a_clock_data[&dbg_mux_gcc][0x3f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x3f][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_gcc][0x3f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x3f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x3f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x3f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x40][&clk_str_name]="gcc_compute_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0x40][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x40][&clk_str_regname]="GCC_COMPUTE_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x40][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x40][&clk_reg_cbc]=0x10c014 v.a \a_clock_data[&dbg_mux_gcc][0x40][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x40][&clk_reg_tc_sel]=0x63 v.a \a_clock_data[&dbg_mux_gcc][0x40][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x40][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x40][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x40][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x41][&clk_str_name]="gcc_compute_trig_clk" v.a \a_clock_str[&dbg_mux_gcc][0x41][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x41][&clk_str_regname]="GCC_COMPUTE_TRIG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x41][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x41][&clk_reg_cbc]=0x10c040 v.a \a_clock_data[&dbg_mux_gcc][0x41][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x41][&clk_reg_tc_sel]=0x6e v.a \a_clock_data[&dbg_mux_gcc][0x41][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x41][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x41][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x41][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x42][&clk_str_name]="gcc_cpuss_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x42][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x42][&clk_str_regname]="GCC_CPUSS_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x42][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x42][&clk_reg_cbc]=0x148000 v.a \a_clock_data[&dbg_mux_gcc][0x42][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x42][&clk_reg_tc_sel]=0xd5 v.a \a_clock_data[&dbg_mux_gcc][0x42][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x42][&clk_reg_vote_bit]=0x15 v.a \a_clock_data[&dbg_mux_gcc][0x42][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x42][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x43][&clk_str_name]="gcc_cpuss_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0x43][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x43][&clk_str_regname]="GCC_CPUSS_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x43][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x43][&clk_reg_cbc]=0x14800c v.a \a_clock_data[&dbg_mux_gcc][0x43][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x43][&clk_reg_tc_sel]=0xd8 v.a \a_clock_data[&dbg_mux_gcc][0x43][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x43][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x43][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x43][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x44][&clk_str_name]="gcc_cpuss_gnoc_clk" v.a \a_clock_str[&dbg_mux_gcc][0x44][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x44][&clk_str_regname]="GCC_CPUSS_GNOC_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x44][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x44][&clk_reg_cbc]=0x148064 v.a \a_clock_data[&dbg_mux_gcc][0x44][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x44][&clk_reg_tc_sel]=0xdc v.a \a_clock_data[&dbg_mux_gcc][0x44][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x44][&clk_reg_vote_bit]=0x1d v.a \a_clock_data[&dbg_mux_gcc][0x44][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x44][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x45][&clk_str_name]="gcc_cpuss_rbcpr_clk" v.a \a_clock_str[&dbg_mux_gcc][0x45][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x45][&clk_str_regname]="GCC_CPUSS_RBCPR_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x45][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x45][&clk_reg_cbc]=0x148004 v.a \a_clock_data[&dbg_mux_gcc][0x45][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x45][&clk_reg_tc_sel]=0xd6 v.a \a_clock_data[&dbg_mux_gcc][0x45][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x45][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x45][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x45][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x46][&clk_str_name]="gcc_cpuss_trig_clk" v.a \a_clock_str[&dbg_mux_gcc][0x46][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x46][&clk_str_regname]="GCC_CPUSS_TRIG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x46][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x46][&clk_reg_cbc]=0x148008 v.a \a_clock_data[&dbg_mux_gcc][0x46][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x46][&clk_reg_tc_sel]=0xd7 v.a \a_clock_data[&dbg_mux_gcc][0x46][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x46][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x46][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x46][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x47][&clk_str_name]="gcc_dcc_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x47][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x47][&clk_str_regname]="GCC_DCC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x47][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x47][&clk_reg_cbc]=0x184004 v.a \a_clock_data[&dbg_mux_gcc][0x47][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x47][&clk_reg_tc_sel]=0x10e v.a \a_clock_data[&dbg_mux_gcc][0x47][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x47][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x47][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x47][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x48][&clk_str_name]="gcc_ddr_i_h_clk" v.a \a_clock_str[&dbg_mux_gcc][0x48][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x48][&clk_str_regname]="GCC_DDR_I_H_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x48][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x48][&clk_reg_cbc]=0x1444ec v.a \a_clock_data[&dbg_mux_gcc][0x48][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x48][&clk_reg_tc_sel]=0xc7 v.a \a_clock_data[&dbg_mux_gcc][0x48][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x48][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x48][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x48][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x49][&clk_str_name]="gcc_ddrmc_ch0_clk" v.a \a_clock_str[&dbg_mux_gcc][0x49][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x49][&clk_str_regname]="GCC_DDRMC_CH0_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x49][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x49][&clk_reg_cbc]=0x144284 v.a \a_clock_data[&dbg_mux_gcc][0x49][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x49][&clk_reg_tc_sel]=0xc3 v.a \a_clock_data[&dbg_mux_gcc][0x49][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x49][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x49][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x49][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x4a][&clk_str_name]="gcc_ddrmc_ch1_clk" v.a \a_clock_str[&dbg_mux_gcc][0x4a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x4a][&clk_str_regname]="GCC_DDRMC_CH1_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x4a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x4a][&clk_reg_cbc]=0x144288 v.a \a_clock_data[&dbg_mux_gcc][0x4a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x4a][&clk_reg_tc_sel]=0xc4 v.a \a_clock_data[&dbg_mux_gcc][0x4a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x4a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x4a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x4a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x4b][&clk_str_name]="gcc_ddrss_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0x4b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x4b][&clk_str_regname]="GCC_DDRSS_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x4b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x4b][&clk_reg_cbc]=0x144020 v.a \a_clock_data[&dbg_mux_gcc][0x4b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x4b][&clk_reg_tc_sel]=0xc2 v.a \a_clock_data[&dbg_mux_gcc][0x4b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x4b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x4b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x4b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x4c][&clk_str_name]="gcc_ddrss_cfg_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x4c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x4c][&clk_str_regname]="GCC_DDRSS_CFG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x4c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x4c][&clk_reg_cbc]=0x144014 v.a \a_clock_data[&dbg_mux_gcc][0x4c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x4c][&clk_reg_tc_sel]=0xbf v.a \a_clock_data[&dbg_mux_gcc][0x4c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x4c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x4c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x4c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x4d][&clk_str_name]="gcc_ddrss_gpu_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x4d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x4d][&clk_str_regname]="GCC_DDRSS_GPU_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x4d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x4d][&clk_reg_cbc]=0x171154 v.a \a_clock_data[&dbg_mux_gcc][0x4d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x4d][&clk_reg_tc_sel]=0xba v.a \a_clock_data[&dbg_mux_gcc][0x4d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x4d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x4d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x4d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x4e][&clk_str_name]="gcc_ddrss_mcdma_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x4e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x4e][&clk_str_regname]="GCC_DDRSS_MCDMA_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x4e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x4e][&clk_reg_cbc]=0x18a288 v.a \a_clock_data[&dbg_mux_gcc][0x4e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x4e][&clk_reg_tc_sel]=0xc6 v.a \a_clock_data[&dbg_mux_gcc][0x4e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x4e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x4e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x4e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x4f][&clk_str_name]="gcc_ddrss_mmnoc_hf_qx_clk" v.a \a_clock_str[&dbg_mux_gcc][0x4f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x4f][&clk_str_regname]="GCC_DDRSS_MMNOC_HF_QX_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x4f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x4f][&clk_reg_cbc]=0x1092a4 v.a \a_clock_data[&dbg_mux_gcc][0x4f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x4f][&clk_reg_tc_sel]=0xb6 v.a \a_clock_data[&dbg_mux_gcc][0x4f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x4f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x4f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x4f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x50][&clk_str_name]="gcc_ddrss_mmnoc_sf_qx_clk" v.a \a_clock_str[&dbg_mux_gcc][0x50][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x50][&clk_str_regname]="GCC_DDRSS_MMNOC_SF_QX_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x50][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x50][&clk_reg_cbc]=0x1092a0 v.a \a_clock_data[&dbg_mux_gcc][0x50][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x50][&clk_reg_tc_sel]=0xb5 v.a \a_clock_data[&dbg_mux_gcc][0x50][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x50][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x50][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x50][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x51][&clk_str_name]="gcc_ddrss_mss_q6_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x51][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x51][&clk_str_regname]="GCC_DDRSS_MSS_Q6_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x51][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x51][&clk_reg_cbc]=0x18a284 v.a \a_clock_data[&dbg_mux_gcc][0x51][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x51][&clk_reg_tc_sel]=0xb9 v.a \a_clock_data[&dbg_mux_gcc][0x51][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x51][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x51][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x51][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x52][&clk_str_name]="gcc_ddrss_sleep_clk" v.a \a_clock_str[&dbg_mux_gcc][0x52][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x52][&clk_str_regname]="GCC_DDRSS_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x52][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x52][&clk_reg_cbc]=0x144018 v.a \a_clock_data[&dbg_mux_gcc][0x52][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x52][&clk_reg_tc_sel]=0xc0 v.a \a_clock_data[&dbg_mux_gcc][0x52][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x52][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x52][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x52][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x53][&clk_str_name]="gcc_ddrss_sys_noc_gc_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x53][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x53][&clk_str_regname]="GCC_DDRSS_SYS_NOC_GC_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x53][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x53][&clk_reg_cbc]=0x144004 v.a \a_clock_data[&dbg_mux_gcc][0x53][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x53][&clk_reg_tc_sel]=0xbb v.a \a_clock_data[&dbg_mux_gcc][0x53][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x53][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x53][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x53][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x54][&clk_str_name]="gcc_ddrss_sys_noc_sf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x54][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x54][&clk_str_regname]="GCC_DDRSS_SYS_NOC_SF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x54][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x54][&clk_reg_cbc]=0x144008 v.a \a_clock_data[&dbg_mux_gcc][0x54][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x54][&clk_reg_tc_sel]=0xbc v.a \a_clock_data[&dbg_mux_gcc][0x54][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x54][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x54][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x54][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x55][&clk_str_name]="gcc_ddrss_sys_noc_slave_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x55][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x55][&clk_str_regname]="GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x55][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x55][&clk_reg_cbc]=0x14400c v.a \a_clock_data[&dbg_mux_gcc][0x55][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x55][&clk_reg_tc_sel]=0xbd v.a \a_clock_data[&dbg_mux_gcc][0x55][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x55][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x55][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x55][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x56][&clk_str_name]="gcc_ddrss_tcu_clk" v.a \a_clock_str[&dbg_mux_gcc][0x56][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x56][&clk_str_regname]="GCC_DDRSS_TCU_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x56][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x56][&clk_reg_cbc]=0x183140 v.a \a_clock_data[&dbg_mux_gcc][0x56][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x56][&clk_reg_tc_sel]=0xb7 v.a \a_clock_data[&dbg_mux_gcc][0x56][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x56][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x56][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x56][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x57][&clk_str_name]="gcc_ddrss_turing_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x57][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x57][&clk_str_regname]="GCC_DDRSS_TURING_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x57][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x57][&clk_reg_cbc]=0x145160 v.a \a_clock_data[&dbg_mux_gcc][0x57][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x57][&clk_reg_tc_sel]=0xb8 v.a \a_clock_data[&dbg_mux_gcc][0x57][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x57][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x57][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x57][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x58][&clk_str_name]="gcc_ddrss_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x58][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x58][&clk_str_regname]="GCC_DDRSS_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x58][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x58][&clk_reg_cbc]=0x144010 v.a \a_clock_data[&dbg_mux_gcc][0x58][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x58][&clk_reg_tc_sel]=0xbe v.a \a_clock_data[&dbg_mux_gcc][0x58][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x58][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x58][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x58][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x59][&clk_str_name]="gcc_disp_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x59][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x59][&clk_str_regname]="GCC_DISP_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x59][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x59][&clk_reg_cbc]=0x10b00c v.a \a_clock_data[&dbg_mux_gcc][0x59][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x59][&clk_reg_tc_sel]=0x40 v.a \a_clock_data[&dbg_mux_gcc][0x59][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x59][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x59][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x59][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x5a][&clk_str_name]="gcc_disp_gpll0_clk_src" v.a \a_clock_str[&dbg_mux_gcc][0x5a][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x5a][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x5a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x5a][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x5a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x5a][&clk_reg_tc_sel]=0x5b v.a \a_clock_data[&dbg_mux_gcc][0x5a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x5a][&clk_reg_vote_bit]=0x14 v.a \a_clock_data[&dbg_mux_gcc][0x5a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x5a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x5b][&clk_str_name]="gcc_disp_hf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x5b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x5b][&clk_str_regname]="GCC_DISP_HF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x5b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x5b][&clk_reg_cbc]=0x10b030 v.a \a_clock_data[&dbg_mux_gcc][0x5b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x5b][&clk_reg_tc_sel]=0x49 v.a \a_clock_data[&dbg_mux_gcc][0x5b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x5b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x5b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x5b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x5c][&clk_str_name]="gcc_disp_sf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x5c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x5c][&clk_str_regname]="GCC_DISP_SF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x5c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x5c][&clk_reg_cbc]=0x10b034 v.a \a_clock_data[&dbg_mux_gcc][0x5c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x5c][&clk_reg_tc_sel]=0x4a v.a \a_clock_data[&dbg_mux_gcc][0x5c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x5c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x5c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x5c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x5d][&clk_str_name]="gcc_disp_throttle_hf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x5d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x5d][&clk_str_regname]="GCC_DISP_THROTTLE_HF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x5d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x5d][&clk_reg_cbc]=0x10b06c v.a \a_clock_data[&dbg_mux_gcc][0x5d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x5d][&clk_reg_tc_sel]=0x55 v.a \a_clock_data[&dbg_mux_gcc][0x5d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x5d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x5d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x5d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x5e][&clk_str_name]="gcc_disp_throttle_sf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x5e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x5e][&clk_str_regname]="GCC_DISP_THROTTLE_SF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x5e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x5e][&clk_reg_cbc]=0x10b070 v.a \a_clock_data[&dbg_mux_gcc][0x5e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x5e][&clk_reg_tc_sel]=0x56 v.a \a_clock_data[&dbg_mux_gcc][0x5e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x5e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x5e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x5e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x5f][&clk_str_name]="gcc_disp_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x5f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x5f][&clk_str_regname]="GCC_DISP_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x5f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x5f][&clk_reg_cbc]=0x10b040 v.a \a_clock_data[&dbg_mux_gcc][0x5f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x5f][&clk_reg_tc_sel]=0x4d v.a \a_clock_data[&dbg_mux_gcc][0x5f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x5f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x5f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x5f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x60][&clk_str_name]="gcc_dpm_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x60][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x60][&clk_str_regname]="GCC_DPM_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x60][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x60][&clk_reg_cbc]=0x146008 v.a \a_clock_data[&dbg_mux_gcc][0x60][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x60][&clk_reg_tc_sel]=0x13f v.a \a_clock_data[&dbg_mux_gcc][0x60][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x60][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x60][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x60][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x61][&clk_str_name]="gcc_dpm_clk" v.a \a_clock_str[&dbg_mux_gcc][0x61][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x61][&clk_str_regname]="GCC_DPM_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x61][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x61][&clk_reg_cbc]=0x146004 v.a \a_clock_data[&dbg_mux_gcc][0x61][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x61][&clk_reg_tc_sel]=0x13e v.a \a_clock_data[&dbg_mux_gcc][0x61][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x61][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x61][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x61][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x62][&clk_str_name]="gcc_freq_measurement_ref_clk" v.a \a_clock_str[&dbg_mux_gcc][0x62][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x62][&clk_str_regname]="GCC_FREQ_MEASUREMENT_REF_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x62][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x62][&clk_reg_cbc]=0x14300c v.a \a_clock_data[&dbg_mux_gcc][0x62][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x62][&clk_reg_tc_sel]=0xb3 v.a \a_clock_data[&dbg_mux_gcc][0x62][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x62][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x62][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x62][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x63][&clk_str_name]="gcc_gp1_clk" v.a \a_clock_str[&dbg_mux_gcc][0x63][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x63][&clk_str_regname]="GCC_GP1_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x63][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x63][&clk_reg_cbc]=0x164000 v.a \a_clock_data[&dbg_mux_gcc][0x63][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x63][&clk_reg_tc_sel]=0xe4 v.a \a_clock_data[&dbg_mux_gcc][0x63][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x63][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x63][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x63][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x64][&clk_str_name]="gcc_gp2_clk" v.a \a_clock_str[&dbg_mux_gcc][0x64][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x64][&clk_str_regname]="GCC_GP2_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x64][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x64][&clk_reg_cbc]=0x165000 v.a \a_clock_data[&dbg_mux_gcc][0x64][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x64][&clk_reg_tc_sel]=0xe5 v.a \a_clock_data[&dbg_mux_gcc][0x64][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x64][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x64][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x64][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x65][&clk_str_name]="gcc_gp3_clk" v.a \a_clock_str[&dbg_mux_gcc][0x65][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x65][&clk_str_regname]="GCC_GP3_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x65][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x65][&clk_reg_cbc]=0x166000 v.a \a_clock_data[&dbg_mux_gcc][0x65][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x65][&clk_reg_tc_sel]=0xe6 v.a \a_clock_data[&dbg_mux_gcc][0x65][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x65][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x65][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x65][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x66][&clk_str_name]="gcc_gpu_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0x66][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x66][&clk_str_regname]="GCC_GPU_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x66][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x66][&clk_reg_cbc]=0x171008 v.a \a_clock_data[&dbg_mux_gcc][0x66][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x66][&clk_reg_tc_sel]=0x128 v.a \a_clock_data[&dbg_mux_gcc][0x66][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x66][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x66][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x66][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x67][&clk_str_name]="gcc_gpu_cfg_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x67][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x67][&clk_str_regname]="GCC_GPU_CFG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x67][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x67][&clk_reg_cbc]=0x171004 v.a \a_clock_data[&dbg_mux_gcc][0x67][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x67][&clk_reg_tc_sel]=0x127 v.a \a_clock_data[&dbg_mux_gcc][0x67][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x67][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x67][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x67][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x68][&clk_str_name]="gcc_gpu_gpll0_clk_src" v.a \a_clock_str[&dbg_mux_gcc][0x68][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x68][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x68][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x68][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x68][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x68][&clk_reg_tc_sel]=0x12d v.a \a_clock_data[&dbg_mux_gcc][0x68][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x68][&clk_reg_vote_bit]=0xf v.a \a_clock_data[&dbg_mux_gcc][0x68][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x68][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x69][&clk_str_name]="gcc_gpu_gpll0_div_clk_src" v.a \a_clock_str[&dbg_mux_gcc][0x69][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x69][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x69][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x69][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x69][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x69][&clk_reg_tc_sel]=0x12e v.a \a_clock_data[&dbg_mux_gcc][0x69][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x69][&clk_reg_vote_bit]=0x10 v.a \a_clock_data[&dbg_mux_gcc][0x69][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x69][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x6a][&clk_str_name]="gcc_gpu_memnoc_gfx_clk" v.a \a_clock_str[&dbg_mux_gcc][0x6a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x6a][&clk_str_regname]="GCC_GPU_MEMNOC_GFX_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x6a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x6a][&clk_reg_cbc]=0x17100c v.a \a_clock_data[&dbg_mux_gcc][0x6a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x6a][&clk_reg_tc_sel]=0x12a v.a \a_clock_data[&dbg_mux_gcc][0x6a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x6a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x6a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x6a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x6b][&clk_str_name]="gcc_gpu_snoc_dvm_gfx_clk" v.a \a_clock_str[&dbg_mux_gcc][0x6b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x6b][&clk_str_regname]="GCC_GPU_SNOC_DVM_GFX_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x6b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x6b][&clk_reg_cbc]=0x171018 v.a \a_clock_data[&dbg_mux_gcc][0x6b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x6b][&clk_reg_tc_sel]=0x12c v.a \a_clock_data[&dbg_mux_gcc][0x6b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x6b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x6b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x6b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x6c][&clk_str_name]="gcc_gpu_trig_clk" v.a \a_clock_str[&dbg_mux_gcc][0x6c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x6c][&clk_str_regname]="GCC_GPU_TRIG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x6c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x6c][&clk_reg_cbc]=0x171014 v.a \a_clock_data[&dbg_mux_gcc][0x6c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x6c][&clk_reg_tc_sel]=0x12b v.a \a_clock_data[&dbg_mux_gcc][0x6c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x6c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x6c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x6c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x6d][&clk_str_name]="gcc_gpu_vs_clk" v.a \a_clock_str[&dbg_mux_gcc][0x6d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x6d][&clk_str_regname]="GCC_GPU_VS_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x6d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x6d][&clk_reg_cbc]=0x17a04c v.a \a_clock_data[&dbg_mux_gcc][0x6d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x6d][&clk_reg_tc_sel]=0xf9 v.a \a_clock_data[&dbg_mux_gcc][0x6d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x6d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x6d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x6d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x6e][&clk_str_name]="gcc_imem_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x6e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x6e][&clk_str_regname]="GCC_IMEM_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x6e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x6e][&clk_reg_cbc]=0x108004 v.a \a_clock_data[&dbg_mux_gcc][0x6e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x6e][&clk_reg_tc_sel]=0x2d v.a \a_clock_data[&dbg_mux_gcc][0x6e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x6e][&clk_reg_vote_bit]=0x18 v.a \a_clock_data[&dbg_mux_gcc][0x6e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x6e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x6f][&clk_str_name]="gcc_imem_cfg_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x6f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x6f][&clk_str_regname]="GCC_IMEM_CFG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x6f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x6f][&clk_reg_cbc]=0x108008 v.a \a_clock_data[&dbg_mux_gcc][0x6f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x6f][&clk_reg_tc_sel]=0x2e v.a \a_clock_data[&dbg_mux_gcc][0x6f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x6f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x6f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x6f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x70][&clk_str_name]="gcc_ipa_2x_clk" v.a \a_clock_str[&dbg_mux_gcc][0x70][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x70][&clk_str_regname]="GCC_IPA_2X_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x70][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x70][&clk_reg_cbc]=0x189010 v.a \a_clock_data[&dbg_mux_gcc][0x70][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x70][&clk_reg_tc_sel]=0x10f v.a \a_clock_data[&dbg_mux_gcc][0x70][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x70][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x70][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x70][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x71][&clk_str_name]="gcc_ipa_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x71][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x71][&clk_str_regname]="GCC_IPA_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x71][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x71][&clk_reg_cbc]=0x189020 v.a \a_clock_data[&dbg_mux_gcc][0x71][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x71][&clk_reg_tc_sel]=0x111 v.a \a_clock_data[&dbg_mux_gcc][0x71][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x71][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x71][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x71][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x72][&clk_str_name]="gcc_ipa_apb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x72][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x72][&clk_str_regname]="GCC_IPA_APB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x72][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x72][&clk_reg_cbc]=0x189028 v.a \a_clock_data[&dbg_mux_gcc][0x72][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x72][&clk_reg_tc_sel]=0x113 v.a \a_clock_data[&dbg_mux_gcc][0x72][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x72][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x72][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x72][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x73][&clk_str_name]="gcc_ipa_clk" v.a \a_clock_str[&dbg_mux_gcc][0x73][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x73][&clk_str_regname]="GCC_IPA_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x73][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x73][&clk_reg_cbc]=0x189018 v.a \a_clock_data[&dbg_mux_gcc][0x73][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x73][&clk_reg_tc_sel]=0x110 v.a \a_clock_data[&dbg_mux_gcc][0x73][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x73][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x73][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x73][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x74][&clk_str_name]="gcc_ipa_sleep_clk" v.a \a_clock_str[&dbg_mux_gcc][0x74][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x74][&clk_str_regname]="GCC_IPA_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x74][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x74][&clk_reg_cbc]=0x189024 v.a \a_clock_data[&dbg_mux_gcc][0x74][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x74][&clk_reg_tc_sel]=0x112 v.a \a_clock_data[&dbg_mux_gcc][0x74][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x74][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x74][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x74][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x75][&clk_str_name]="gcc_ipa_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x75][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x75][&clk_str_regname]="GCC_IPA_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x75][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x75][&clk_reg_cbc]=0x18902c v.a \a_clock_data[&dbg_mux_gcc][0x75][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x75][&clk_reg_tc_sel]=0x114 v.a \a_clock_data[&dbg_mux_gcc][0x75][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x75][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x75][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x75][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x76][&clk_str_name]="gcc_ipcc_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x76][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x76][&clk_str_regname]="GCC_IPCC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x76][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x76][&clk_reg_cbc]=0x125008 v.a \a_clock_data[&dbg_mux_gcc][0x76][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x76][&clk_reg_tc_sel]=0x13d v.a \a_clock_data[&dbg_mux_gcc][0x76][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x76][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x76][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x76][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x77][&clk_str_name]="gcc_ipcc_core_clk" v.a \a_clock_str[&dbg_mux_gcc][0x77][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x77][&clk_str_regname]="GCC_IPCC_CORE_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x77][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x77][&clk_reg_cbc]=0x125004 v.a \a_clock_data[&dbg_mux_gcc][0x77][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x77][&clk_reg_tc_sel]=0x13c v.a \a_clock_data[&dbg_mux_gcc][0x77][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x77][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x77][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x77][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x78][&clk_str_name]="gcc_lpass_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0x78][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x78][&clk_str_regname]="GCC_LPASS_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x78][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x78][&clk_reg_cbc]=0x14700c v.a \a_clock_data[&dbg_mux_gcc][0x78][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x78][&clk_reg_tc_sel]=0xcb v.a \a_clock_data[&dbg_mux_gcc][0x78][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x78][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x78][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x78][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x79][&clk_str_name]="gcc_lpass_cfg_noc_sway_clk" v.a \a_clock_str[&dbg_mux_gcc][0x79][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x79][&clk_str_regname]="GCC_LPASS_CFG_NOC_SWAY_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x79][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x79][&clk_reg_cbc]=0x147004 v.a \a_clock_data[&dbg_mux_gcc][0x79][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x79][&clk_reg_tc_sel]=0xc9 v.a \a_clock_data[&dbg_mux_gcc][0x79][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x79][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x79][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x79][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x7a][&clk_str_name]="gcc_lpass_core_axim_clk" v.a \a_clock_str[&dbg_mux_gcc][0x7a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x7a][&clk_str_regname]="GCC_LPASS_CORE_AXIM_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x7a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x7a][&clk_reg_cbc]=0x147000 v.a \a_clock_data[&dbg_mux_gcc][0x7a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x7a][&clk_reg_tc_sel]=0xc8 v.a \a_clock_data[&dbg_mux_gcc][0x7a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x7a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x7a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x7a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x7b][&clk_str_name]="gcc_lpass_trig_clk" v.a \a_clock_str[&dbg_mux_gcc][0x7b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x7b][&clk_str_regname]="GCC_LPASS_TRIG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x7b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x7b][&clk_reg_cbc]=0x147008 v.a \a_clock_data[&dbg_mux_gcc][0x7b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x7b][&clk_reg_tc_sel]=0xca v.a \a_clock_data[&dbg_mux_gcc][0x7b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x7b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x7b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x7b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x7c][&clk_str_name]="gcc_memnoc_clk" v.a \a_clock_str[&dbg_mux_gcc][0x7c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x7c][&clk_str_regname]="GCC_MEMNOC_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x7c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x7c][&clk_reg_cbc]=0x14401c v.a \a_clock_data[&dbg_mux_gcc][0x7c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x7c][&clk_reg_tc_sel]=0xc1 v.a \a_clock_data[&dbg_mux_gcc][0x7c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x7c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x7c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x7c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x7d][&clk_str_name]="gcc_mmnoc_ahb_cfg_clk" v.a \a_clock_str[&dbg_mux_gcc][0x7d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x7d][&clk_str_regname]="GCC_MMNOC_AHB_CFG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x7d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x7d][&clk_reg_cbc]=0x10902c v.a \a_clock_data[&dbg_mux_gcc][0x7d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x7d][&clk_reg_tc_sel]=0x39 v.a \a_clock_data[&dbg_mux_gcc][0x7d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x7d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x7d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x7d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x7e][&clk_str_name]="gcc_mmnoc_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0x7e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x7e][&clk_str_regname]="GCC_MMNOC_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x7e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x7e][&clk_reg_cbc]=0x109028 v.a \a_clock_data[&dbg_mux_gcc][0x7e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x7e][&clk_reg_tc_sel]=0x38 v.a \a_clock_data[&dbg_mux_gcc][0x7e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x7e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x7e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x7e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x7f][&clk_str_name]="gcc_mmnoc_hf_qx_clk" v.a \a_clock_str[&dbg_mux_gcc][0x7f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x7f][&clk_str_regname]="GCC_MMNOC_HF_QX_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x7f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x7f][&clk_reg_cbc]=0x109034 v.a \a_clock_data[&dbg_mux_gcc][0x7f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x7f][&clk_reg_tc_sel]=0x3b v.a \a_clock_data[&dbg_mux_gcc][0x7f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x7f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x7f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x7f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x80][&clk_str_name]="gcc_mmnoc_qosgen_extref_clk" v.a \a_clock_str[&dbg_mux_gcc][0x80][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x80][&clk_str_regname]="GCC_MMNOC_QOSGEN_EXTREF_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x80][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x80][&clk_reg_cbc]=0x10929c v.a \a_clock_data[&dbg_mux_gcc][0x80][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x80][&clk_reg_tc_sel]=0x3d v.a \a_clock_data[&dbg_mux_gcc][0x80][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x80][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x80][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x80][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x81][&clk_str_name]="gcc_mmnoc_sf_qx_clk" v.a \a_clock_str[&dbg_mux_gcc][0x81][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x81][&clk_str_regname]="GCC_MMNOC_SF_QX_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x81][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x81][&clk_reg_cbc]=0x109168 v.a \a_clock_data[&dbg_mux_gcc][0x81][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x81][&clk_reg_tc_sel]=0x3c v.a \a_clock_data[&dbg_mux_gcc][0x81][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x81][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x81][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x81][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x82][&clk_str_name]="gcc_mmnoc_tbu_hf0_clk" v.a \a_clock_str[&dbg_mux_gcc][0x82][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x82][&clk_str_regname]="GCC_MMNOC_TBU_HF0_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x82][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x82][&clk_reg_cbc]=0x109018 v.a \a_clock_data[&dbg_mux_gcc][0x82][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x82][&clk_reg_tc_sel]=0x36 v.a \a_clock_data[&dbg_mux_gcc][0x82][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x82][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x82][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x82][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x83][&clk_str_name]="gcc_mmnoc_tbu_hf1_clk" v.a \a_clock_str[&dbg_mux_gcc][0x83][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x83][&clk_str_regname]="GCC_MMNOC_TBU_HF1_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x83][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x83][&clk_reg_cbc]=0x109020 v.a \a_clock_data[&dbg_mux_gcc][0x83][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x83][&clk_reg_tc_sel]=0x37 v.a \a_clock_data[&dbg_mux_gcc][0x83][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x83][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x83][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x83][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x84][&clk_str_name]="gcc_mmnoc_tbu_sf0_clk" v.a \a_clock_str[&dbg_mux_gcc][0x84][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x84][&clk_str_regname]="GCC_MMNOC_TBU_SF0_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x84][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x84][&clk_reg_cbc]=0x109010 v.a \a_clock_data[&dbg_mux_gcc][0x84][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x84][&clk_reg_tc_sel]=0x35 v.a \a_clock_data[&dbg_mux_gcc][0x84][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x84][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x84][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x84][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x85][&clk_str_name]="gcc_mmss_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0x85][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x85][&clk_str_regname]="GCC_MMSS_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x85][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x85][&clk_reg_cbc]=0x10b044 v.a \a_clock_data[&dbg_mux_gcc][0x85][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x85][&clk_reg_tc_sel]=0x4e v.a \a_clock_data[&dbg_mux_gcc][0x85][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x85][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x85][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x85][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x86][&clk_str_name]="gcc_mmss_qm_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x86][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x86][&clk_str_regname]="GCC_MMSS_QM_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x86][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x86][&clk_reg_cbc]=0x10b068 v.a \a_clock_data[&dbg_mux_gcc][0x86][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x86][&clk_reg_tc_sel]=0x54 v.a \a_clock_data[&dbg_mux_gcc][0x86][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x86][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x86][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x86][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x87][&clk_str_name]="gcc_mmss_qm_core_clk" v.a \a_clock_str[&dbg_mux_gcc][0x87][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x87][&clk_str_regname]="GCC_MMSS_QM_CORE_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x87][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x87][&clk_reg_cbc]=0x10b048 v.a \a_clock_data[&dbg_mux_gcc][0x87][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x87][&clk_reg_tc_sel]=0x52 v.a \a_clock_data[&dbg_mux_gcc][0x87][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x87][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x87][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x87][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x88][&clk_str_name]="gcc_mmss_trig_clk" v.a \a_clock_str[&dbg_mux_gcc][0x88][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x88][&clk_str_regname]="GCC_MMSS_TRIG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x88][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x88][&clk_reg_cbc]=0x10b04c v.a \a_clock_data[&dbg_mux_gcc][0x88][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x88][&clk_reg_tc_sel]=0x53 v.a \a_clock_data[&dbg_mux_gcc][0x88][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x88][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x88][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x88][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x89][&clk_str_name]="gcc_mmu_tcu_clk" v.a \a_clock_str[&dbg_mux_gcc][0x89][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x89][&clk_str_regname]="GCC_MMU_TCU_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x89][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x89][&clk_reg_cbc]=0x183008 v.a \a_clock_data[&dbg_mux_gcc][0x89][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x89][&clk_reg_tc_sel]=0x30 v.a \a_clock_data[&dbg_mux_gcc][0x89][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x89][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x89][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x89][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x8a][&clk_str_name]="gcc_mmu_tcu_slp_stg_clk" v.a \a_clock_str[&dbg_mux_gcc][0x8a][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x8a][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x8a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x8a][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x8a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x8a][&clk_reg_tc_sel]=0x31 v.a \a_clock_data[&dbg_mux_gcc][0x8a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x8a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x8a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x8a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x8b][&clk_str_name]="gcc_mss_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0x8b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x8b][&clk_str_regname]="GCC_MSS_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x8b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x8b][&clk_reg_cbc]=0x18a00c v.a \a_clock_data[&dbg_mux_gcc][0x8b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x8b][&clk_reg_tc_sel]=0x118 v.a \a_clock_data[&dbg_mux_gcc][0x8b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x8b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x8b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x8b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x8c][&clk_str_name]="gcc_mss_axis2_clk" v.a \a_clock_str[&dbg_mux_gcc][0x8c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x8c][&clk_str_regname]="GCC_MSS_AXIS2_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x8c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x8c][&clk_reg_cbc]=0x18a004 v.a \a_clock_data[&dbg_mux_gcc][0x8c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x8c][&clk_reg_tc_sel]=0x116 v.a \a_clock_data[&dbg_mux_gcc][0x8c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x8c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x8c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x8c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x8d][&clk_str_name]="gcc_mss_cfg_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x8d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x8d][&clk_str_regname]="GCC_MSS_CFG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x8d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x8d][&clk_reg_cbc]=0x18a000 v.a \a_clock_data[&dbg_mux_gcc][0x8d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x8d][&clk_reg_tc_sel]=0x115 v.a \a_clock_data[&dbg_mux_gcc][0x8d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x8d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x8d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x8d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x8e][&clk_str_name]="gcc_mss_gpll0_div_clk_src" v.a \a_clock_str[&dbg_mux_gcc][0x8e][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x8e][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x8e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x8e][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x8e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x8e][&clk_reg_tc_sel]=0x119 v.a \a_clock_data[&dbg_mux_gcc][0x8e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x8e][&clk_reg_vote_bit]=0x11 v.a \a_clock_data[&dbg_mux_gcc][0x8e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x8e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x8f][&clk_str_name]="gcc_mss_offline_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x8f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x8f][&clk_str_regname]="GCC_MSS_OFFLINE_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x8f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x8f][&clk_reg_cbc]=0x18a280 v.a \a_clock_data[&dbg_mux_gcc][0x8f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x8f][&clk_reg_tc_sel]=0x11d v.a \a_clock_data[&dbg_mux_gcc][0x8f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x8f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x8f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x8f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x90][&clk_str_name]="gcc_mss_q6_memnoc_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x90][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x90][&clk_str_regname]="GCC_MSS_Q6_MEMNOC_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x90][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x90][&clk_reg_cbc]=0x18a14c v.a \a_clock_data[&dbg_mux_gcc][0x90][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x90][&clk_reg_tc_sel]=0x11b v.a \a_clock_data[&dbg_mux_gcc][0x90][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x90][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x90][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x90][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x91][&clk_str_name]="gcc_mss_snoc_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x91][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x91][&clk_str_regname]="GCC_MSS_SNOC_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x91][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x91][&clk_reg_cbc]=0x18a148 v.a \a_clock_data[&dbg_mux_gcc][0x91][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x91][&clk_reg_tc_sel]=0x11a v.a \a_clock_data[&dbg_mux_gcc][0x91][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x91][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x91][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x91][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x92][&clk_str_name]="gcc_mss_trig_clk" v.a \a_clock_str[&dbg_mux_gcc][0x92][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x92][&clk_str_regname]="GCC_MSS_TRIG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x92][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x92][&clk_reg_cbc]=0x18a008 v.a \a_clock_data[&dbg_mux_gcc][0x92][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x92][&clk_reg_tc_sel]=0x117 v.a \a_clock_data[&dbg_mux_gcc][0x92][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x92][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x92][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x92][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x93][&clk_str_name]="gcc_mss_vs_clk" v.a \a_clock_str[&dbg_mux_gcc][0x93][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x93][&clk_str_regname]="GCC_MSS_VS_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x93][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x93][&clk_reg_cbc]=0x17a048 v.a \a_clock_data[&dbg_mux_gcc][0x93][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x93][&clk_reg_tc_sel]=0xf8 v.a \a_clock_data[&dbg_mux_gcc][0x93][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x93][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x93][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x93][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x94][&clk_str_name]="gcc_nav_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x94][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x94][&clk_str_regname]="GCC_NAV_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x94][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x94][&clk_reg_cbc]=0x115004 v.a \a_clock_data[&dbg_mux_gcc][0x94][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x94][&clk_reg_tc_sel]=0x12f v.a \a_clock_data[&dbg_mux_gcc][0x94][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x94][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x94][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x94][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x95][&clk_str_name]="gcc_noc_bus_timeout_extref_clk" v.a \a_clock_str[&dbg_mux_gcc][0x95][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x95][&clk_str_regname]="GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x95][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x95][&clk_reg_cbc]=0x149004 v.a \a_clock_data[&dbg_mux_gcc][0x95][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x95][&clk_reg_tc_sel]=0xdd v.a \a_clock_data[&dbg_mux_gcc][0x95][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x95][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x95][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x95][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x96][&clk_str_name]="gcc_noc_center_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x96][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x96][&clk_str_regname]="GCC_NOC_CENTER_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x96][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x96][&clk_reg_cbc]=0x105034 v.a \a_clock_data[&dbg_mux_gcc][0x96][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x96][&clk_reg_tc_sel]=0x20 v.a \a_clock_data[&dbg_mux_gcc][0x96][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x96][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x96][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x96][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x97][&clk_str_name]="gcc_noc_compute_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x97][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x97][&clk_str_regname]="GCC_NOC_COMPUTE_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x97][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x97][&clk_reg_cbc]=0x105044 v.a \a_clock_data[&dbg_mux_gcc][0x97][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x97][&clk_reg_tc_sel]=0x24 v.a \a_clock_data[&dbg_mux_gcc][0x97][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x97][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x97][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x97][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x98][&clk_str_name]="gcc_noc_east_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x98][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x98][&clk_str_regname]="GCC_NOC_EAST_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x98][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x98][&clk_reg_cbc]=0x1053fc v.a \a_clock_data[&dbg_mux_gcc][0x98][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x98][&clk_reg_tc_sel]=0x29 v.a \a_clock_data[&dbg_mux_gcc][0x98][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x98][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x98][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x98][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x99][&clk_str_name]="gcc_noc_lpass_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x99][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x99][&clk_str_regname]="GCC_NOC_LPASS_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x99][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x99][&clk_reg_cbc]=0x105040 v.a \a_clock_data[&dbg_mux_gcc][0x99][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x99][&clk_reg_tc_sel]=0x23 v.a \a_clock_data[&dbg_mux_gcc][0x99][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x99][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x99][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x99][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x9a][&clk_str_name]="gcc_noc_mmnoc_cnoc_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x9a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x9a][&clk_str_regname]="GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x9a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x9a][&clk_reg_cbc]=0x105048 v.a \a_clock_data[&dbg_mux_gcc][0x9a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x9a][&clk_reg_tc_sel]=0x25 v.a \a_clock_data[&dbg_mux_gcc][0x9a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x9a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x9a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x9a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x9b][&clk_str_name]="gcc_noc_mmnoc_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x9b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x9b][&clk_str_regname]="GCC_NOC_MMNOC_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x9b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x9b][&clk_reg_cbc]=0x109030 v.a \a_clock_data[&dbg_mux_gcc][0x9b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x9b][&clk_reg_tc_sel]=0x3a v.a \a_clock_data[&dbg_mux_gcc][0x9b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x9b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x9b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x9b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x9c][&clk_str_name]="gcc_noc_monaq_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x9c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x9c][&clk_str_regname]="GCC_NOC_MONAQ_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x9c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x9c][&clk_reg_cbc]=0x105038 v.a \a_clock_data[&dbg_mux_gcc][0x9c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x9c][&clk_reg_tc_sel]=0x21 v.a \a_clock_data[&dbg_mux_gcc][0x9c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x9c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x9c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x9c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x9d][&clk_str_name]="gcc_noc_north_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x9d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x9d][&clk_str_regname]="GCC_NOC_NORTH_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x9d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x9d][&clk_reg_cbc]=0x10502c v.a \a_clock_data[&dbg_mux_gcc][0x9d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x9d][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_gcc][0x9d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x9d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x9d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x9d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x9e][&clk_str_name]="gcc_noc_south_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x9e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x9e][&clk_str_regname]="GCC_NOC_SOUTH_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x9e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x9e][&clk_reg_cbc]=0x105030 v.a \a_clock_data[&dbg_mux_gcc][0x9e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x9e][&clk_reg_tc_sel]=0x1f v.a \a_clock_data[&dbg_mux_gcc][0x9e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x9e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x9e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x9e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x9f][&clk_str_name]="gcc_noc_west_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x9f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x9f][&clk_str_regname]="GCC_NOC_WEST_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x9f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x9f][&clk_reg_cbc]=0x105028 v.a \a_clock_data[&dbg_mux_gcc][0x9f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x9f][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_gcc][0x9f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x9f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x9f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x9f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xa0][&clk_str_name]="gcc_noc_wlan_dcd_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0xa0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xa0][&clk_str_regname]="GCC_NOC_WLAN_DCD_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xa0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xa0][&clk_reg_cbc]=0x105400 v.a \a_clock_data[&dbg_mux_gcc][0xa0][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xa0][&clk_reg_tc_sel]=0x2a v.a \a_clock_data[&dbg_mux_gcc][0xa0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xa0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xa0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xa1][&clk_str_name]="gcc_north_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0xa1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xa1][&clk_str_regname]="GCC_NORTH_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xa1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xa1][&clk_reg_cbc]=0x10c018 v.a \a_clock_data[&dbg_mux_gcc][0xa1][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xa1][&clk_reg_tc_sel]=0x64 v.a \a_clock_data[&dbg_mux_gcc][0xa1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xa1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xa1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xa2][&clk_str_name]="gcc_npu_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0xa2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xa2][&clk_str_regname]="GCC_NPU_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xa2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xa2][&clk_reg_cbc]=0x14d014 v.a \a_clock_data[&dbg_mux_gcc][0xa2][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xa2][&clk_reg_tc_sel]=0x138 v.a \a_clock_data[&dbg_mux_gcc][0xa2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xa2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xa2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xa3][&clk_str_name]="gcc_npu_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xa3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xa3][&clk_str_regname]="GCC_NPU_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xa3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xa3][&clk_reg_cbc]=0x14d008 v.a \a_clock_data[&dbg_mux_gcc][0xa3][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xa3][&clk_reg_tc_sel]=0x135 v.a \a_clock_data[&dbg_mux_gcc][0xa3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xa3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xa3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xa4][&clk_str_name]="gcc_npu_bwmon2_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xa4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xa4][&clk_str_regname]="GCC_NPU_BWMON2_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xa4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xa4][&clk_reg_cbc]=0x17000c v.a \a_clock_data[&dbg_mux_gcc][0xa4][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xa4][&clk_reg_tc_sel]=0x142 v.a \a_clock_data[&dbg_mux_gcc][0xa4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xa4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xa4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xa5][&clk_str_name]="gcc_npu_bwmon_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xa5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xa5][&clk_str_regname]="GCC_NPU_BWMON_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xa5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xa5][&clk_reg_cbc]=0x170008 v.a \a_clock_data[&dbg_mux_gcc][0xa5][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xa5][&clk_reg_tc_sel]=0x141 v.a \a_clock_data[&dbg_mux_gcc][0xa5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xa5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xa5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xa6][&clk_str_name]="gcc_npu_bwmon_cfg_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xa6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xa6][&clk_str_regname]="GCC_NPU_BWMON_CFG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xa6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xa6][&clk_reg_cbc]=0x170004 v.a \a_clock_data[&dbg_mux_gcc][0xa6][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xa6][&clk_reg_tc_sel]=0x140 v.a \a_clock_data[&dbg_mux_gcc][0xa6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xa6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xa6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xa7][&clk_str_name]="gcc_npu_cfg_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xa7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xa7][&clk_str_regname]="GCC_NPU_CFG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xa7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xa7][&clk_reg_cbc]=0x14d004 v.a \a_clock_data[&dbg_mux_gcc][0xa7][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xa7][&clk_reg_tc_sel]=0x134 v.a \a_clock_data[&dbg_mux_gcc][0xa7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xa7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xa7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xa8][&clk_str_name]="gcc_npu_dma_clk" v.a \a_clock_str[&dbg_mux_gcc][0xa8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xa8][&clk_str_regname]="GCC_NPU_DMA_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xa8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xa8][&clk_reg_cbc]=0x14d00c v.a \a_clock_data[&dbg_mux_gcc][0xa8][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xa8][&clk_reg_tc_sel]=0x136 v.a \a_clock_data[&dbg_mux_gcc][0xa8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xa8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xa8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xa9][&clk_str_name]="gcc_npu_gpll0_clk_src" v.a \a_clock_str[&dbg_mux_gcc][0xa9][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0xa9][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0xa9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xa9][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa9][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xa9][&clk_reg_tc_sel]=0x139 v.a \a_clock_data[&dbg_mux_gcc][0xa9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xa9][&clk_reg_vote_bit]=0x12 v.a \a_clock_data[&dbg_mux_gcc][0xa9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xa9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xaa][&clk_str_name]="gcc_npu_gpll0_div_clk_src" v.a \a_clock_str[&dbg_mux_gcc][0xaa][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0xaa][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0xaa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xaa][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xaa][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xaa][&clk_reg_tc_sel]=0x13a v.a \a_clock_data[&dbg_mux_gcc][0xaa][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xaa][&clk_reg_vote_bit]=0x13 v.a \a_clock_data[&dbg_mux_gcc][0xaa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xaa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xab][&clk_str_name]="gcc_npu_trig_clk" v.a \a_clock_str[&dbg_mux_gcc][0xab][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xab][&clk_str_regname]="GCC_NPU_TRIG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xab][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xab][&clk_reg_cbc]=0x14d010 v.a \a_clock_data[&dbg_mux_gcc][0xab][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xab][&clk_reg_tc_sel]=0x137 v.a \a_clock_data[&dbg_mux_gcc][0xab][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xab][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xab][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xab][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xac][&clk_str_name]="gcc_pdm2_clk" v.a \a_clock_str[&dbg_mux_gcc][0xac][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xac][&clk_str_regname]="GCC_PDM2_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xac][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xac][&clk_reg_cbc]=0x13300c v.a \a_clock_data[&dbg_mux_gcc][0xac][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xac][&clk_reg_tc_sel]=0x96 v.a \a_clock_data[&dbg_mux_gcc][0xac][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xac][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xac][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xac][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xad][&clk_str_name]="gcc_pdm_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xad][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xad][&clk_str_regname]="GCC_PDM_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xad][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xad][&clk_reg_cbc]=0x133004 v.a \a_clock_data[&dbg_mux_gcc][0xad][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xad][&clk_reg_tc_sel]=0x94 v.a \a_clock_data[&dbg_mux_gcc][0xad][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xad][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xad][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xad][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xae][&clk_str_name]="gcc_pdm_xo4_clk" v.a \a_clock_str[&dbg_mux_gcc][0xae][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xae][&clk_str_regname]="GCC_PDM_XO4_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xae][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xae][&clk_reg_cbc]=0x133008 v.a \a_clock_data[&dbg_mux_gcc][0xae][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xae][&clk_reg_tc_sel]=0x95 v.a \a_clock_data[&dbg_mux_gcc][0xae][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xae][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xae][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xae][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xaf][&clk_str_name]="gcc_phy_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0xaf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xaf][&clk_str_regname]="GCC_PHY_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xaf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xaf][&clk_reg_cbc]=0x10c01c v.a \a_clock_data[&dbg_mux_gcc][0xaf][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xaf][&clk_reg_tc_sel]=0x65 v.a \a_clock_data[&dbg_mux_gcc][0xaf][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xaf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xaf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xaf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xb0][&clk_str_name]="gcc_pimem_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xb0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xb0][&clk_str_regname]="GCC_PIMEM_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xb0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xb0][&clk_reg_cbc]=0x10a008 v.a \a_clock_data[&dbg_mux_gcc][0xb0][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xb0][&clk_reg_tc_sel]=0x5e v.a \a_clock_data[&dbg_mux_gcc][0xb0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xb0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xb0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xb0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xb1][&clk_str_name]="gcc_pimem_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0xb1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xb1][&clk_str_regname]="GCC_PIMEM_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xb1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xb1][&clk_reg_cbc]=0x10c020 v.a \a_clock_data[&dbg_mux_gcc][0xb1][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xb1][&clk_reg_tc_sel]=0x66 v.a \a_clock_data[&dbg_mux_gcc][0xb1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xb1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xb1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xb1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xb2][&clk_str_name]="gcc_pimem_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xb2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xb2][&clk_str_regname]="GCC_PIMEM_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xb2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xb2][&clk_reg_cbc]=0x10a004 v.a \a_clock_data[&dbg_mux_gcc][0xb2][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xb2][&clk_reg_tc_sel]=0x5d v.a \a_clock_data[&dbg_mux_gcc][0xb2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xb2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xb2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xb2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xb3][&clk_str_name]="gcc_prng_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xb3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xb3][&clk_str_regname]="GCC_PRNG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xb3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xb3][&clk_reg_cbc]=0x134004 v.a \a_clock_data[&dbg_mux_gcc][0xb3][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xb3][&clk_reg_tc_sel]=0x97 v.a \a_clock_data[&dbg_mux_gcc][0xb3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xb3][&clk_reg_vote_bit]=0xd v.a \a_clock_data[&dbg_mux_gcc][0xb3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xb3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xb4][&clk_str_name]="gcc_qdss_center_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0xb4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xb4][&clk_str_regname]="GCC_QDSS_CENTER_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xb4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xb4][&clk_reg_cbc]=0x10c00c v.a \a_clock_data[&dbg_mux_gcc][0xb4][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xb4][&clk_reg_tc_sel]=0x61 v.a \a_clock_data[&dbg_mux_gcc][0xb4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xb4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xb4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xb4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xb5][&clk_str_name]="gcc_qdss_cfg_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xb5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xb5][&clk_str_regname]="GCC_QDSS_CFG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xb5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xb5][&clk_reg_cbc]=0x10c008 v.a \a_clock_data[&dbg_mux_gcc][0xb5][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xb5][&clk_reg_tc_sel]=0x60 v.a \a_clock_data[&dbg_mux_gcc][0xb5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xb5][&clk_reg_vote_bit]=0x2 v.a \a_clock_data[&dbg_mux_gcc][0xb5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xb5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xb6][&clk_str_name]="gcc_qdss_dap_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xb6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xb6][&clk_str_regname]="GCC_QDSS_DAP_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xb6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xb6][&clk_reg_cbc]=0x10c004 v.a \a_clock_data[&dbg_mux_gcc][0xb6][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xb6][&clk_reg_tc_sel]=0x5f v.a \a_clock_data[&dbg_mux_gcc][0xb6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xb6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xb6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xb6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xb7][&clk_str_name]="gcc_qdss_dap_clk" v.a \a_clock_str[&dbg_mux_gcc][0xb7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xb7][&clk_str_regname]="GCC_QDSS_DAP_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xb7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xb7][&clk_reg_cbc]=0x10c038 v.a \a_clock_data[&dbg_mux_gcc][0xb7][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xb7][&clk_reg_tc_sel]=0x6c v.a \a_clock_data[&dbg_mux_gcc][0xb7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xb7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xb7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xb7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xb8][&clk_str_name]="gcc_qdss_etr_usb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xb8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xb8][&clk_str_regname]="GCC_QDSS_ETR_USB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xb8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xb8][&clk_reg_cbc]=0x10c024 v.a \a_clock_data[&dbg_mux_gcc][0xb8][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xb8][&clk_reg_tc_sel]=0x67 v.a \a_clock_data[&dbg_mux_gcc][0xb8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xb8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xb8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xb8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xb9][&clk_str_name]="gcc_qdss_stm_clk" v.a \a_clock_str[&dbg_mux_gcc][0xb9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xb9][&clk_str_regname]="GCC_QDSS_STM_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xb9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xb9][&clk_reg_cbc]=0x10c028 v.a \a_clock_data[&dbg_mux_gcc][0xb9][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xb9][&clk_reg_tc_sel]=0x68 v.a \a_clock_data[&dbg_mux_gcc][0xb9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xb9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xb9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xb9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xba][&clk_str_name]="gcc_qdss_traceclkin_clk" v.a \a_clock_str[&dbg_mux_gcc][0xba][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xba][&clk_str_regname]="GCC_QDSS_TRACECLKIN_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xba][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xba][&clk_reg_cbc]=0x10c02c v.a \a_clock_data[&dbg_mux_gcc][0xba][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xba][&clk_reg_tc_sel]=0x69 v.a \a_clock_data[&dbg_mux_gcc][0xba][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xba][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xba][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xba][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xbb][&clk_str_name]="gcc_qdss_trig_clk" v.a \a_clock_str[&dbg_mux_gcc][0xbb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xbb][&clk_str_regname]="GCC_QDSS_TRIG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xbb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xbb][&clk_reg_cbc]=0x10c034 v.a \a_clock_data[&dbg_mux_gcc][0xbb][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xbb][&clk_reg_tc_sel]=0x6b v.a \a_clock_data[&dbg_mux_gcc][0xbb][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xbb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xbb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xbb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xbc][&clk_str_name]="gcc_qdss_tsctr_clk" v.a \a_clock_str[&dbg_mux_gcc][0xbc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xbc][&clk_str_regname]="GCC_QDSS_TSCTR_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xbc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xbc][&clk_reg_cbc]=0x10c030 v.a \a_clock_data[&dbg_mux_gcc][0xbc][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xbc][&clk_reg_tc_sel]=0x6a v.a \a_clock_data[&dbg_mux_gcc][0xbc][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xbc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xbc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xbc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xbd][&clk_str_name]="gcc_qdss_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0xbd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xbd][&clk_str_regname]="GCC_QDSS_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xbd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xbd][&clk_reg_cbc]=0x10c044 v.a \a_clock_data[&dbg_mux_gcc][0xbd][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xbd][&clk_reg_tc_sel]=0x6f v.a \a_clock_data[&dbg_mux_gcc][0xbd][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xbd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xbd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xbd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xbe][&clk_str_name]="gcc_qmip_camera_nrt_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xbe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xbe][&clk_str_regname]="GCC_QMIP_CAMERA_NRT_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xbe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xbe][&clk_reg_cbc]=0x10b018 v.a \a_clock_data[&dbg_mux_gcc][0xbe][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xbe][&clk_reg_tc_sel]=0x43 v.a \a_clock_data[&dbg_mux_gcc][0xbe][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xbe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xbe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xbe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xbf][&clk_str_name]="gcc_qmip_camera_rt_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xbf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xbf][&clk_str_regname]="GCC_QMIP_CAMERA_RT_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xbf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xbf][&clk_reg_cbc]=0x10b01c v.a \a_clock_data[&dbg_mux_gcc][0xbf][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xbf][&clk_reg_tc_sel]=0x44 v.a \a_clock_data[&dbg_mux_gcc][0xbf][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xbf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xbf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xbf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xc0][&clk_str_name]="gcc_qmip_disp_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xc0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xc0][&clk_str_regname]="GCC_QMIP_DISP_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xc0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xc0][&clk_reg_cbc]=0x10b020 v.a \a_clock_data[&dbg_mux_gcc][0xc0][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xc0][&clk_reg_tc_sel]=0x45 v.a \a_clock_data[&dbg_mux_gcc][0xc0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xc0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xc0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xc0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xc1][&clk_str_name]="gcc_qmip_rt_disp_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xc1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xc1][&clk_str_regname]="GCC_QMIP_RT_DISP_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xc1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xc1][&clk_reg_cbc]=0x10b07c v.a \a_clock_data[&dbg_mux_gcc][0xc1][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xc1][&clk_reg_tc_sel]=0x59 v.a \a_clock_data[&dbg_mux_gcc][0xc1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xc1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xc1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xc1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xc2][&clk_str_name]="gcc_qmip_video_cvp_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xc2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xc2][&clk_str_regname]="GCC_QMIP_VIDEO_CVP_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xc2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xc2][&clk_reg_cbc]=0x10b010 v.a \a_clock_data[&dbg_mux_gcc][0xc2][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xc2][&clk_reg_tc_sel]=0x41 v.a \a_clock_data[&dbg_mux_gcc][0xc2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xc2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xc2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xc2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xc3][&clk_str_name]="gcc_qmip_video_vcodec_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xc3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xc3][&clk_str_regname]="GCC_QMIP_VIDEO_VCODEC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xc3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xc3][&clk_reg_cbc]=0x10b014 v.a \a_clock_data[&dbg_mux_gcc][0xc3][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xc3][&clk_reg_tc_sel]=0x42 v.a \a_clock_data[&dbg_mux_gcc][0xc3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xc3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xc3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xc3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xc4][&clk_str_name]="gcc_qrefs_vbg_cal_clk" v.a \a_clock_str[&dbg_mux_gcc][0xc4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xc4][&clk_str_regname]="GCC_QREFS_VBG_CAL_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xc4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xc4][&clk_reg_cbc]=0x188004 v.a \a_clock_data[&dbg_mux_gcc][0xc4][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xc4][&clk_reg_tc_sel]=0x11e v.a \a_clock_data[&dbg_mux_gcc][0xc4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xc4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xc4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xc4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xc5][&clk_str_name]="gcc_qupv3_wrap0_core_2x_clk" v.a \a_clock_str[&dbg_mux_gcc][0xc5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xc5][&clk_str_regname]="GCC_QUPV3_WRAP0_CORE_2X_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xc5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xc5][&clk_reg_cbc]=0x123008 v.a \a_clock_data[&dbg_mux_gcc][0xc5][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xc5][&clk_reg_tc_sel]=0x83 v.a \a_clock_data[&dbg_mux_gcc][0xc5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xc5][&clk_reg_vote_bit]=0x29 v.a \a_clock_data[&dbg_mux_gcc][0xc5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xc5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xc6][&clk_str_name]="gcc_qupv3_wrap0_core_clk" v.a \a_clock_str[&dbg_mux_gcc][0xc6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xc6][&clk_str_regname]="GCC_QUPV3_WRAP0_CORE_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xc6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xc6][&clk_reg_cbc]=0x123000 v.a \a_clock_data[&dbg_mux_gcc][0xc6][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xc6][&clk_reg_tc_sel]=0x82 v.a \a_clock_data[&dbg_mux_gcc][0xc6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xc6][&clk_reg_vote_bit]=0x28 v.a \a_clock_data[&dbg_mux_gcc][0xc6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xc6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xc7][&clk_str_name]="gcc_qupv3_wrap0_s0_clk" v.a \a_clock_str[&dbg_mux_gcc][0xc7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xc7][&clk_str_regname]="GCC_QUPV3_WRAP0_S0_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xc7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xc7][&clk_reg_cbc]=0x11700c v.a \a_clock_data[&dbg_mux_gcc][0xc7][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xc7][&clk_reg_tc_sel]=0x84 v.a \a_clock_data[&dbg_mux_gcc][0xc7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xc7][&clk_reg_vote_bit]=0x2a v.a \a_clock_data[&dbg_mux_gcc][0xc7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xc7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xc8][&clk_str_name]="gcc_qupv3_wrap0_s1_clk" v.a \a_clock_str[&dbg_mux_gcc][0xc8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xc8][&clk_str_regname]="GCC_QUPV3_WRAP0_S1_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xc8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xc8][&clk_reg_cbc]=0x11713c v.a \a_clock_data[&dbg_mux_gcc][0xc8][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xc8][&clk_reg_tc_sel]=0x85 v.a \a_clock_data[&dbg_mux_gcc][0xc8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xc8][&clk_reg_vote_bit]=0x2b v.a \a_clock_data[&dbg_mux_gcc][0xc8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xc8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xc9][&clk_str_name]="gcc_qupv3_wrap0_s2_clk" v.a \a_clock_str[&dbg_mux_gcc][0xc9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xc9][&clk_str_regname]="GCC_QUPV3_WRAP0_S2_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xc9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xc9][&clk_reg_cbc]=0x11726c v.a \a_clock_data[&dbg_mux_gcc][0xc9][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xc9][&clk_reg_tc_sel]=0x86 v.a \a_clock_data[&dbg_mux_gcc][0xc9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xc9][&clk_reg_vote_bit]=0x2c v.a \a_clock_data[&dbg_mux_gcc][0xc9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xc9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xca][&clk_str_name]="gcc_qupv3_wrap0_s3_clk" v.a \a_clock_str[&dbg_mux_gcc][0xca][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xca][&clk_str_regname]="GCC_QUPV3_WRAP0_S3_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xca][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xca][&clk_reg_cbc]=0x11739c v.a \a_clock_data[&dbg_mux_gcc][0xca][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xca][&clk_reg_tc_sel]=0x87 v.a \a_clock_data[&dbg_mux_gcc][0xca][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xca][&clk_reg_vote_bit]=0x2d v.a \a_clock_data[&dbg_mux_gcc][0xca][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xca][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xcb][&clk_str_name]="gcc_qupv3_wrap0_s4_clk" v.a \a_clock_str[&dbg_mux_gcc][0xcb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xcb][&clk_str_regname]="GCC_QUPV3_WRAP0_S4_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xcb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xcb][&clk_reg_cbc]=0x1174cc v.a \a_clock_data[&dbg_mux_gcc][0xcb][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xcb][&clk_reg_tc_sel]=0x88 v.a \a_clock_data[&dbg_mux_gcc][0xcb][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xcb][&clk_reg_vote_bit]=0x2e v.a \a_clock_data[&dbg_mux_gcc][0xcb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xcb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xcc][&clk_str_name]="gcc_qupv3_wrap0_s5_clk" v.a \a_clock_str[&dbg_mux_gcc][0xcc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xcc][&clk_str_regname]="GCC_QUPV3_WRAP0_S5_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xcc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xcc][&clk_reg_cbc]=0x1175fc v.a \a_clock_data[&dbg_mux_gcc][0xcc][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xcc][&clk_reg_tc_sel]=0x89 v.a \a_clock_data[&dbg_mux_gcc][0xcc][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xcc][&clk_reg_vote_bit]=0x2f v.a \a_clock_data[&dbg_mux_gcc][0xcc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xcc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xcd][&clk_str_name]="gcc_qupv3_wrap1_core_2x_clk" v.a \a_clock_str[&dbg_mux_gcc][0xcd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xcd][&clk_str_regname]="GCC_QUPV3_WRAP1_CORE_2X_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xcd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xcd][&clk_reg_cbc]=0x123140 v.a \a_clock_data[&dbg_mux_gcc][0xcd][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xcd][&clk_reg_tc_sel]=0x8d v.a \a_clock_data[&dbg_mux_gcc][0xcd][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xcd][&clk_reg_vote_bit]=0x32 v.a \a_clock_data[&dbg_mux_gcc][0xcd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xcd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xce][&clk_str_name]="gcc_qupv3_wrap1_core_clk" v.a \a_clock_str[&dbg_mux_gcc][0xce][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xce][&clk_str_regname]="GCC_QUPV3_WRAP1_CORE_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xce][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xce][&clk_reg_cbc]=0x123138 v.a \a_clock_data[&dbg_mux_gcc][0xce][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xce][&clk_reg_tc_sel]=0x8c v.a \a_clock_data[&dbg_mux_gcc][0xce][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xce][&clk_reg_vote_bit]=0x33 v.a \a_clock_data[&dbg_mux_gcc][0xce][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xce][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xcf][&clk_str_name]="gcc_qupv3_wrap1_s0_clk" v.a \a_clock_str[&dbg_mux_gcc][0xcf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xcf][&clk_str_regname]="GCC_QUPV3_WRAP1_S0_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xcf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xcf][&clk_reg_cbc]=0x11800c v.a \a_clock_data[&dbg_mux_gcc][0xcf][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xcf][&clk_reg_tc_sel]=0x8e v.a \a_clock_data[&dbg_mux_gcc][0xcf][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xcf][&clk_reg_vote_bit]=0x36 v.a \a_clock_data[&dbg_mux_gcc][0xcf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xcf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xd0][&clk_str_name]="gcc_qupv3_wrap1_s1_clk" v.a \a_clock_str[&dbg_mux_gcc][0xd0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xd0][&clk_str_regname]="GCC_QUPV3_WRAP1_S1_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xd0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xd0][&clk_reg_cbc]=0x11813c v.a \a_clock_data[&dbg_mux_gcc][0xd0][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xd0][&clk_reg_tc_sel]=0x8f v.a \a_clock_data[&dbg_mux_gcc][0xd0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xd0][&clk_reg_vote_bit]=0x37 v.a \a_clock_data[&dbg_mux_gcc][0xd0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xd0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xd1][&clk_str_name]="gcc_qupv3_wrap1_s2_clk" v.a \a_clock_str[&dbg_mux_gcc][0xd1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xd1][&clk_str_regname]="GCC_QUPV3_WRAP1_S2_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xd1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xd1][&clk_reg_cbc]=0x11826c v.a \a_clock_data[&dbg_mux_gcc][0xd1][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xd1][&clk_reg_tc_sel]=0x90 v.a \a_clock_data[&dbg_mux_gcc][0xd1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xd1][&clk_reg_vote_bit]=0x38 v.a \a_clock_data[&dbg_mux_gcc][0xd1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xd1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xd2][&clk_str_name]="gcc_qupv3_wrap1_s3_clk" v.a \a_clock_str[&dbg_mux_gcc][0xd2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xd2][&clk_str_regname]="GCC_QUPV3_WRAP1_S3_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xd2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xd2][&clk_reg_cbc]=0x11839c v.a \a_clock_data[&dbg_mux_gcc][0xd2][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xd2][&clk_reg_tc_sel]=0x91 v.a \a_clock_data[&dbg_mux_gcc][0xd2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xd2][&clk_reg_vote_bit]=0x39 v.a \a_clock_data[&dbg_mux_gcc][0xd2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xd2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xd3][&clk_str_name]="gcc_qupv3_wrap1_s4_clk" v.a \a_clock_str[&dbg_mux_gcc][0xd3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xd3][&clk_str_regname]="GCC_QUPV3_WRAP1_S4_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xd3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xd3][&clk_reg_cbc]=0x1184cc v.a \a_clock_data[&dbg_mux_gcc][0xd3][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xd3][&clk_reg_tc_sel]=0x92 v.a \a_clock_data[&dbg_mux_gcc][0xd3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xd3][&clk_reg_vote_bit]=0x3a v.a \a_clock_data[&dbg_mux_gcc][0xd3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xd3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xd4][&clk_str_name]="gcc_qupv3_wrap1_s5_clk" v.a \a_clock_str[&dbg_mux_gcc][0xd4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xd4][&clk_str_regname]="GCC_QUPV3_WRAP1_S5_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xd4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xd4][&clk_reg_cbc]=0x1185fc v.a \a_clock_data[&dbg_mux_gcc][0xd4][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xd4][&clk_reg_tc_sel]=0x93 v.a \a_clock_data[&dbg_mux_gcc][0xd4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xd4][&clk_reg_vote_bit]=0x3b v.a \a_clock_data[&dbg_mux_gcc][0xd4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xd4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xd5][&clk_str_name]="gcc_qupv3_wrap_0_m_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xd5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xd5][&clk_str_regname]="GCC_QUPV3_WRAP_0_M_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xd5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xd5][&clk_reg_cbc]=0x117004 v.a \a_clock_data[&dbg_mux_gcc][0xd5][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xd5][&clk_reg_tc_sel]=0x80 v.a \a_clock_data[&dbg_mux_gcc][0xd5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xd5][&clk_reg_vote_bit]=0x26 v.a \a_clock_data[&dbg_mux_gcc][0xd5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xd5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xd6][&clk_str_name]="gcc_qupv3_wrap_0_s_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xd6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xd6][&clk_str_regname]="GCC_QUPV3_WRAP_0_S_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xd6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xd6][&clk_reg_cbc]=0x117008 v.a \a_clock_data[&dbg_mux_gcc][0xd6][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xd6][&clk_reg_tc_sel]=0x81 v.a \a_clock_data[&dbg_mux_gcc][0xd6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xd6][&clk_reg_vote_bit]=0x27 v.a \a_clock_data[&dbg_mux_gcc][0xd6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xd6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xd7][&clk_str_name]="gcc_qupv3_wrap_1_m_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xd7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xd7][&clk_str_regname]="GCC_QUPV3_WRAP_1_M_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xd7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xd7][&clk_reg_cbc]=0x118004 v.a \a_clock_data[&dbg_mux_gcc][0xd7][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xd7][&clk_reg_tc_sel]=0x8a v.a \a_clock_data[&dbg_mux_gcc][0xd7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xd7][&clk_reg_vote_bit]=0x34 v.a \a_clock_data[&dbg_mux_gcc][0xd7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xd7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xd8][&clk_str_name]="gcc_qupv3_wrap_1_s_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xd8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xd8][&clk_str_regname]="GCC_QUPV3_WRAP_1_S_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xd8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xd8][&clk_reg_cbc]=0x118008 v.a \a_clock_data[&dbg_mux_gcc][0xd8][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xd8][&clk_reg_tc_sel]=0x8b v.a \a_clock_data[&dbg_mux_gcc][0xd8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xd8][&clk_reg_vote_bit]=0x35 v.a \a_clock_data[&dbg_mux_gcc][0xd8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xd8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xd9][&clk_str_name]="gcc_rbcpr_cx_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xd9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xd9][&clk_str_regname]="GCC_RBCPR_CX_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xd9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xd9][&clk_reg_cbc]=0x14e008 v.a \a_clock_data[&dbg_mux_gcc][0xd9][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xd9][&clk_reg_tc_sel]=0xdf v.a \a_clock_data[&dbg_mux_gcc][0xd9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xd9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xd9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xd9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xda][&clk_str_name]="gcc_rbcpr_cx_clk" v.a \a_clock_str[&dbg_mux_gcc][0xda][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xda][&clk_str_regname]="GCC_RBCPR_CX_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xda][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xda][&clk_reg_cbc]=0x14e004 v.a \a_clock_data[&dbg_mux_gcc][0xda][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xda][&clk_reg_tc_sel]=0xde v.a \a_clock_data[&dbg_mux_gcc][0xda][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xda][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xda][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xda][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xdb][&clk_str_name]="gcc_rbcpr_mx_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xdb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xdb][&clk_str_regname]="GCC_RBCPR_MX_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xdb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xdb][&clk_reg_cbc]=0x14f008 v.a \a_clock_data[&dbg_mux_gcc][0xdb][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xdb][&clk_reg_tc_sel]=0xe1 v.a \a_clock_data[&dbg_mux_gcc][0xdb][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xdb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xdb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xdb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xdc][&clk_str_name]="gcc_rbcpr_mx_clk" v.a \a_clock_str[&dbg_mux_gcc][0xdc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xdc][&clk_str_regname]="GCC_RBCPR_MX_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xdc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xdc][&clk_reg_cbc]=0x14f004 v.a \a_clock_data[&dbg_mux_gcc][0xdc][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xdc][&clk_reg_tc_sel]=0xe0 v.a \a_clock_data[&dbg_mux_gcc][0xdc][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xdc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xdc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xdc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xdd][&clk_str_name]="gcc_sdcc1_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xdd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xdd][&clk_str_regname]="GCC_SDCC1_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xdd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xdd][&clk_reg_cbc]=0x126004 v.a \a_clock_data[&dbg_mux_gcc][0xdd][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xdd][&clk_reg_tc_sel]=0x148 v.a \a_clock_data[&dbg_mux_gcc][0xdd][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xdd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xdd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xdd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xde][&clk_str_name]="gcc_sdcc1_apps_clk" v.a \a_clock_str[&dbg_mux_gcc][0xde][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xde][&clk_str_regname]="GCC_SDCC1_APPS_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xde][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xde][&clk_reg_cbc]=0x126008 v.a \a_clock_data[&dbg_mux_gcc][0xde][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xde][&clk_reg_tc_sel]=0x149 v.a \a_clock_data[&dbg_mux_gcc][0xde][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xde][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xde][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xde][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xdf][&clk_str_name]="gcc_sdcc1_ice_core_clk" v.a \a_clock_str[&dbg_mux_gcc][0xdf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xdf][&clk_str_regname]="GCC_SDCC1_ICE_CORE_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xdf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xdf][&clk_reg_cbc]=0x12603c v.a \a_clock_data[&dbg_mux_gcc][0xdf][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xdf][&clk_reg_tc_sel]=0x14a v.a \a_clock_data[&dbg_mux_gcc][0xdf][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xdf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xdf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xdf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xe0][&clk_str_name]="gcc_sdcc2_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xe0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xe0][&clk_str_regname]="GCC_SDCC2_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xe0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xe0][&clk_reg_cbc]=0x114008 v.a \a_clock_data[&dbg_mux_gcc][0xe0][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xe0][&clk_reg_tc_sel]=0x7d v.a \a_clock_data[&dbg_mux_gcc][0xe0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xe0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xe0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xe0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xe1][&clk_str_name]="gcc_sdcc2_apps_clk" v.a \a_clock_str[&dbg_mux_gcc][0xe1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xe1][&clk_str_regname]="GCC_SDCC2_APPS_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xe1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xe1][&clk_reg_cbc]=0x114004 v.a \a_clock_data[&dbg_mux_gcc][0xe1][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xe1][&clk_reg_tc_sel]=0x7c v.a \a_clock_data[&dbg_mux_gcc][0xe1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xe1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xe1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xe1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xe2][&clk_str_name]="gcc_sdcc4_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xe2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xe2][&clk_str_regname]="GCC_SDCC4_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xe2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xe2][&clk_reg_cbc]=0x116008 v.a \a_clock_data[&dbg_mux_gcc][0xe2][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xe2][&clk_reg_tc_sel]=0x7f v.a \a_clock_data[&dbg_mux_gcc][0xe2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xe2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xe2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xe2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xe3][&clk_str_name]="gcc_sdcc4_apps_clk" v.a \a_clock_str[&dbg_mux_gcc][0xe3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xe3][&clk_str_regname]="GCC_SDCC4_APPS_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xe3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xe3][&clk_reg_cbc]=0x116004 v.a \a_clock_data[&dbg_mux_gcc][0xe3][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xe3][&clk_reg_tc_sel]=0x7e v.a \a_clock_data[&dbg_mux_gcc][0xe3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xe3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xe3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xe3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xe4][&clk_str_name]="gcc_sec_ctrl_acc_clk" v.a \a_clock_str[&dbg_mux_gcc][0xe4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xe4][&clk_str_regname]="GCC_SEC_CTRL_ACC_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xe4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xe4][&clk_reg_cbc]=0x13d004 v.a \a_clock_data[&dbg_mux_gcc][0xe4][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xe4][&clk_reg_tc_sel]=0xa3 v.a \a_clock_data[&dbg_mux_gcc][0xe4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xe4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xe4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xe4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xe5][&clk_str_name]="gcc_sec_ctrl_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xe5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xe5][&clk_str_regname]="GCC_SEC_CTRL_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xe5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xe5][&clk_reg_cbc]=0x13d008 v.a \a_clock_data[&dbg_mux_gcc][0xe5][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xe5][&clk_reg_tc_sel]=0xa4 v.a \a_clock_data[&dbg_mux_gcc][0xe5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xe5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xe5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xe5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xe6][&clk_str_name]="gcc_sec_ctrl_boot_rom_patch_clk" v.a \a_clock_str[&dbg_mux_gcc][0xe6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xe6][&clk_str_regname]="GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xe6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xe6][&clk_reg_cbc]=0x13d014 v.a \a_clock_data[&dbg_mux_gcc][0xe6][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xe6][&clk_reg_tc_sel]=0xa7 v.a \a_clock_data[&dbg_mux_gcc][0xe6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xe6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xe6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xe6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xe7][&clk_str_name]="gcc_sec_ctrl_clk" v.a \a_clock_str[&dbg_mux_gcc][0xe7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xe7][&clk_str_regname]="GCC_SEC_CTRL_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xe7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xe7][&clk_reg_cbc]=0x13d00c v.a \a_clock_data[&dbg_mux_gcc][0xe7][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xe7][&clk_reg_tc_sel]=0xa5 v.a \a_clock_data[&dbg_mux_gcc][0xe7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xe7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xe7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xe7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xe8][&clk_str_name]="gcc_sec_ctrl_sense_clk" v.a \a_clock_str[&dbg_mux_gcc][0xe8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xe8][&clk_str_regname]="GCC_SEC_CTRL_SENSE_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xe8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xe8][&clk_reg_cbc]=0x13d010 v.a \a_clock_data[&dbg_mux_gcc][0xe8][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xe8][&clk_reg_tc_sel]=0xa6 v.a \a_clock_data[&dbg_mux_gcc][0xe8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xe8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xe8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xe8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xe9][&clk_str_name]="gcc_sleep_clk" v.a \a_clock_str[&dbg_mux_gcc][0xe9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xe9][&clk_str_regname]="GCC_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xe9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xe9][&clk_reg_cbc]=0x143010 v.a \a_clock_data[&dbg_mux_gcc][0xe9][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xe9][&clk_reg_tc_sel]=0xb4 v.a \a_clock_data[&dbg_mux_gcc][0xe9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xe9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xe9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xe9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xea][&clk_str_name]="gcc_snoc_qosgen_extref_clk" v.a \a_clock_str[&dbg_mux_gcc][0xea][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xea][&clk_str_regname]="GCC_SNOC_QOSGEN_EXTREF_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xea][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xea][&clk_reg_cbc]=0x104280 v.a \a_clock_data[&dbg_mux_gcc][0xea][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xea][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_gcc][0xea][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xea][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xea][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xea][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xeb][&clk_str_name]="gcc_south_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0xeb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xeb][&clk_str_regname]="GCC_SOUTH_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xeb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xeb][&clk_reg_cbc]=0x10c010 v.a \a_clock_data[&dbg_mux_gcc][0xeb][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xeb][&clk_reg_tc_sel]=0x62 v.a \a_clock_data[&dbg_mux_gcc][0xeb][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xeb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xeb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xeb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xec][&clk_str_name]="gcc_spdm_ff_clk" v.a \a_clock_str[&dbg_mux_gcc][0xec][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xec][&clk_str_regname]="GCC_SPDM_FF_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xec][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xec][&clk_reg_cbc]=0x140008 v.a \a_clock_data[&dbg_mux_gcc][0xec][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xec][&clk_reg_tc_sel]=0xa9 v.a \a_clock_data[&dbg_mux_gcc][0xec][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xec][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xec][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xec][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xed][&clk_str_name]="gcc_spdm_memnoc_cy_clk" v.a \a_clock_str[&dbg_mux_gcc][0xed][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xed][&clk_str_regname]="GCC_SPDM_MEMNOC_CY_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xed][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xed][&clk_reg_cbc]=0x14000c v.a \a_clock_data[&dbg_mux_gcc][0xed][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xed][&clk_reg_tc_sel]=0xaa v.a \a_clock_data[&dbg_mux_gcc][0xed][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xed][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xed][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xed][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xee][&clk_str_name]="gcc_spdm_mstr_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xee][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xee][&clk_str_regname]="GCC_SPDM_MSTR_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xee][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xee][&clk_reg_cbc]=0x140004 v.a \a_clock_data[&dbg_mux_gcc][0xee][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xee][&clk_reg_tc_sel]=0xa8 v.a \a_clock_data[&dbg_mux_gcc][0xee][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xee][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xee][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xee][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xef][&clk_str_name]="gcc_spdm_pnoc_cy_clk" v.a \a_clock_str[&dbg_mux_gcc][0xef][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xef][&clk_str_regname]="GCC_SPDM_PNOC_CY_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xef][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xef][&clk_reg_cbc]=0x140018 v.a \a_clock_data[&dbg_mux_gcc][0xef][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xef][&clk_reg_tc_sel]=0xac v.a \a_clock_data[&dbg_mux_gcc][0xef][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xef][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xef][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xef][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xf0][&clk_str_name]="gcc_spdm_snoc_cy_clk" v.a \a_clock_str[&dbg_mux_gcc][0xf0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xf0][&clk_str_regname]="GCC_SPDM_SNOC_CY_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xf0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xf0][&clk_reg_cbc]=0x140010 v.a \a_clock_data[&dbg_mux_gcc][0xf0][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xf0][&clk_reg_tc_sel]=0xab v.a \a_clock_data[&dbg_mux_gcc][0xf0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xf0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xf0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xf1][&clk_str_name]="gcc_sys_noc_ahb_cfg_clk" v.a \a_clock_str[&dbg_mux_gcc][0xf1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xf1][&clk_str_regname]="GCC_SYS_NOC_AHB_CFG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xf1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xf1][&clk_reg_cbc]=0x104144 v.a \a_clock_data[&dbg_mux_gcc][0xf1][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xf1][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_gcc][0xf1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xf1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xf1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xf2][&clk_str_name]="gcc_sys_noc_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0xf2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xf2][&clk_str_regname]="GCC_SYS_NOC_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xf2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xf2][&clk_reg_cbc]=0x104148 v.a \a_clock_data[&dbg_mux_gcc][0xf2][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xf2][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_gcc][0xf2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xf2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xf2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xf3][&clk_str_name]="gcc_sys_noc_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xf3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xf3][&clk_str_regname]="GCC_SYS_NOC_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xf3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xf3][&clk_reg_cbc]=0x104138 v.a \a_clock_data[&dbg_mux_gcc][0xf3][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xf3][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_gcc][0xf3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xf3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xf3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xf4][&clk_str_name]="gcc_sys_noc_cpuss_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xf4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xf4][&clk_str_regname]="GCC_SYS_NOC_CPUSS_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xf4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xf4][&clk_reg_cbc]=0x148068 v.a \a_clock_data[&dbg_mux_gcc][0xf4][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xf4][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_gcc][0xf4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xf4][&clk_reg_vote_bit]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xf5][&clk_str_name]="gcc_sys_noc_gc_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xf5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xf5][&clk_str_regname]="GCC_SYS_NOC_GC_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xf5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xf5][&clk_reg_cbc]=0x104004 v.a \a_clock_data[&dbg_mux_gcc][0xf5][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xf5][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_gcc][0xf5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xf5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xf5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xf6][&clk_str_name]="gcc_sys_noc_lpass_sf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xf6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xf6][&clk_str_regname]="GCC_SYS_NOC_LPASS_SF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xf6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xf6][&clk_reg_cbc]=0x147010 v.a \a_clock_data[&dbg_mux_gcc][0xf6][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xf6][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_gcc][0xf6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xf6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xf6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xf7][&clk_str_name]="gcc_sys_noc_monaq_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xf7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xf7][&clk_str_regname]="GCC_SYS_NOC_MONAQ_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xf7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xf7][&clk_reg_cbc]=0x104288 v.a \a_clock_data[&dbg_mux_gcc][0xf7][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xf7][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_gcc][0xf7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xf7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xf7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xf8][&clk_str_name]="gcc_sys_noc_monaq_sf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xf8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xf8][&clk_str_regname]="GCC_SYS_NOC_MONAQ_SF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xf8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xf8][&clk_reg_cbc]=0x10428c v.a \a_clock_data[&dbg_mux_gcc][0xf8][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xf8][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_gcc][0xf8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xf8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xf8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xf9][&clk_str_name]="gcc_sys_noc_qdss_stm_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xf9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xf9][&clk_str_regname]="GCC_SYS_NOC_QDSS_STM_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xf9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xf9][&clk_reg_cbc]=0x104140 v.a \a_clock_data[&dbg_mux_gcc][0xf9][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xf9][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_gcc][0xf9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xf9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xf9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xf9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xfa][&clk_str_name]="gcc_sys_noc_sf_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xfa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xfa][&clk_str_regname]="GCC_SYS_NOC_SF_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xfa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xfa][&clk_reg_cbc]=0x104284 v.a \a_clock_data[&dbg_mux_gcc][0xfa][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xfa][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_gcc][0xfa][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xfa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xfa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xfa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xfb][&clk_str_name]="gcc_sys_noc_sf_tcu_clk" v.a \a_clock_str[&dbg_mux_gcc][0xfb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xfb][&clk_str_regname]="GCC_SYS_NOC_SF_TCU_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xfb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xfb][&clk_reg_cbc]=0x183004 v.a \a_clock_data[&dbg_mux_gcc][0xfb][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xfb][&clk_reg_tc_sel]=0x2f v.a \a_clock_data[&dbg_mux_gcc][0xfb][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xfb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xfb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xfb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xfc][&clk_str_name]="gcc_sys_noc_south_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xfc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xfc][&clk_str_regname]="GCC_SYS_NOC_SOUTH_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xfc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xfc][&clk_reg_cbc]=0x10413c v.a \a_clock_data[&dbg_mux_gcc][0xfc][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xfc][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_gcc][0xfc][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xfc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xfc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xfc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xfd][&clk_str_name]="gcc_sys_noc_wlan_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0xfd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xfd][&clk_str_regname]="GCC_SYS_NOC_WLAN_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xfd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xfd][&clk_reg_cbc]=0x1044fc v.a \a_clock_data[&dbg_mux_gcc][0xfd][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xfd][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_gcc][0xfd][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xfd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xfd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xfd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xfe][&clk_str_name]="gcc_tcsr_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xfe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xfe][&clk_str_regname]="GCC_TCSR_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xfe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xfe][&clk_reg_cbc]=0x137004 v.a \a_clock_data[&dbg_mux_gcc][0xfe][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xfe][&clk_reg_tc_sel]=0x98 v.a \a_clock_data[&dbg_mux_gcc][0xfe][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xfe][&clk_reg_vote_bit]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xfe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xfe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0xff][&clk_str_name]="gcc_tic_cfg_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0xff][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0xff][&clk_str_regname]="GCC_TIC_CFG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0xff][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0xff][&clk_reg_cbc]=0x10e000 v.a \a_clock_data[&dbg_mux_gcc][0xff][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0xff][&clk_reg_tc_sel]=0x2c v.a \a_clock_data[&dbg_mux_gcc][0xff][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0xff][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0xff][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0xff][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x100][&clk_str_name]="gcc_tic_clk" v.a \a_clock_str[&dbg_mux_gcc][0x100][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x100][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x100][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x100][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x100][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x100][&clk_reg_tc_sel]=0x2b v.a \a_clock_data[&dbg_mux_gcc][0x100][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x100][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x100][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x100][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x101][&clk_str_name]="gcc_tlmm_clk" v.a \a_clock_str[&dbg_mux_gcc][0x101][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x101][&clk_str_regname]="GCC_TLMM_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x101][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x101][&clk_reg_cbc]=0x13a010 v.a \a_clock_data[&dbg_mux_gcc][0x101][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x101][&clk_reg_tc_sel]=0x9d v.a \a_clock_data[&dbg_mux_gcc][0x101][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x101][&clk_reg_vote_bit]=0x6 v.a \a_clock_data[&dbg_mux_gcc][0x101][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x101][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x102][&clk_str_name]="gcc_tlmm_east_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x102][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x102][&clk_str_regname]="GCC_TLMM_EAST_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x102][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x102][&clk_reg_cbc]=0x13a014 v.a \a_clock_data[&dbg_mux_gcc][0x102][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x102][&clk_reg_tc_sel]=0x9e v.a \a_clock_data[&dbg_mux_gcc][0x102][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x102][&clk_reg_vote_bit]=0xc v.a \a_clock_data[&dbg_mux_gcc][0x102][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x102][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x103][&clk_str_name]="gcc_tlmm_north_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x103][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x103][&clk_str_regname]="GCC_TLMM_NORTH_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x103][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x103][&clk_reg_cbc]=0x13a004 v.a \a_clock_data[&dbg_mux_gcc][0x103][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x103][&clk_reg_tc_sel]=0x9a v.a \a_clock_data[&dbg_mux_gcc][0x103][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x103][&clk_reg_vote_bit]=0x8 v.a \a_clock_data[&dbg_mux_gcc][0x103][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x103][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x104][&clk_str_name]="gcc_tlmm_south_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x104][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x104][&clk_str_regname]="GCC_TLMM_SOUTH_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x104][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x104][&clk_reg_cbc]=0x13a008 v.a \a_clock_data[&dbg_mux_gcc][0x104][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x104][&clk_reg_tc_sel]=0x9b v.a \a_clock_data[&dbg_mux_gcc][0x104][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x104][&clk_reg_vote_bit]=0xb v.a \a_clock_data[&dbg_mux_gcc][0x104][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x104][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x105][&clk_str_name]="gcc_tlmm_west_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x105][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x105][&clk_str_regname]="GCC_TLMM_WEST_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x105][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x105][&clk_reg_cbc]=0x13a00c v.a \a_clock_data[&dbg_mux_gcc][0x105][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x105][&clk_reg_tc_sel]=0x9c v.a \a_clock_data[&dbg_mux_gcc][0x105][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x105][&clk_reg_vote_bit]=0xe v.a \a_clock_data[&dbg_mux_gcc][0x105][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x105][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x106][&clk_str_name]="gcc_turing_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0x106][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x106][&clk_str_regname]="GCC_TURING_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x106][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x106][&clk_reg_cbc]=0x145028 v.a \a_clock_data[&dbg_mux_gcc][0x106][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x106][&clk_reg_tc_sel]=0xd2 v.a \a_clock_data[&dbg_mux_gcc][0x106][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x106][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x106][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x106][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x107][&clk_str_name]="gcc_turing_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x107][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x107][&clk_str_regname]="GCC_TURING_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x107][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x107][&clk_reg_cbc]=0x145020 v.a \a_clock_data[&dbg_mux_gcc][0x107][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x107][&clk_reg_tc_sel]=0xd0 v.a \a_clock_data[&dbg_mux_gcc][0x107][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x107][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x107][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x107][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x108][&clk_str_name]="gcc_turing_cfg_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x108][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x108][&clk_str_regname]="GCC_TURING_CFG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x108][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x108][&clk_reg_cbc]=0x145024 v.a \a_clock_data[&dbg_mux_gcc][0x108][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x108][&clk_reg_tc_sel]=0xd1 v.a \a_clock_data[&dbg_mux_gcc][0x108][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x108][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x108][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x108][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x109][&clk_str_name]="gcc_turing_q6_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x109][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x109][&clk_str_regname]="GCC_TURING_Q6_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x109][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x109][&clk_reg_cbc]=0x14501c v.a \a_clock_data[&dbg_mux_gcc][0x109][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x109][&clk_reg_tc_sel]=0xcf v.a \a_clock_data[&dbg_mux_gcc][0x109][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x109][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x109][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x109][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x10a][&clk_str_name]="gcc_turing_tbu0_clk" v.a \a_clock_str[&dbg_mux_gcc][0x10a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x10a][&clk_str_regname]="GCC_TURING_TBU0_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x10a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x10a][&clk_reg_cbc]=0x14500c v.a \a_clock_data[&dbg_mux_gcc][0x10a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x10a][&clk_reg_tc_sel]=0xcd v.a \a_clock_data[&dbg_mux_gcc][0x10a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x10a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x10a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x10a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x10b][&clk_str_name]="gcc_turing_tbu1_clk" v.a \a_clock_str[&dbg_mux_gcc][0x10b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x10b][&clk_str_regname]="GCC_TURING_TBU1_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x10b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x10b][&clk_reg_cbc]=0x145014 v.a \a_clock_data[&dbg_mux_gcc][0x10b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x10b][&clk_reg_tc_sel]=0xce v.a \a_clock_data[&dbg_mux_gcc][0x10b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x10b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x10b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x10b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x10c][&clk_str_name]="gcc_turing_trig_clk" v.a \a_clock_str[&dbg_mux_gcc][0x10c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x10c][&clk_str_regname]="GCC_TURING_TRIG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x10c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x10c][&clk_reg_cbc]=0x14502c v.a \a_clock_data[&dbg_mux_gcc][0x10c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x10c][&clk_reg_tc_sel]=0xd3 v.a \a_clock_data[&dbg_mux_gcc][0x10c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x10c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x10c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x10c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x10d][&clk_str_name]="gcc_ufs_phy_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x10d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x10d][&clk_str_regname]="GCC_UFS_PHY_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x10d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x10d][&clk_reg_cbc]=0x177018 v.a \a_clock_data[&dbg_mux_gcc][0x10d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x10d][&clk_reg_tc_sel]=0xe8 v.a \a_clock_data[&dbg_mux_gcc][0x10d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x10d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x10d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x10d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x10e][&clk_str_name]="gcc_ufs_phy_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x10e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x10e][&clk_str_regname]="GCC_UFS_PHY_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x10e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x10e][&clk_reg_cbc]=0x177010 v.a \a_clock_data[&dbg_mux_gcc][0x10e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x10e][&clk_reg_tc_sel]=0xe7 v.a \a_clock_data[&dbg_mux_gcc][0x10e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x10e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x10e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x10e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x10f][&clk_str_name]="gcc_ufs_phy_ice_core_clk" v.a \a_clock_str[&dbg_mux_gcc][0x10f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x10f][&clk_str_regname]="GCC_UFS_PHY_ICE_CORE_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x10f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x10f][&clk_reg_cbc]=0x177064 v.a \a_clock_data[&dbg_mux_gcc][0x10f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x10f][&clk_reg_tc_sel]=0xee v.a \a_clock_data[&dbg_mux_gcc][0x10f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x10f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x10f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x10f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x110][&clk_str_name]="gcc_ufs_phy_phy_aux_clk" v.a \a_clock_str[&dbg_mux_gcc][0x110][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x110][&clk_str_regname]="GCC_UFS_PHY_PHY_AUX_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x110][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x110][&clk_reg_cbc]=0x17709c v.a \a_clock_data[&dbg_mux_gcc][0x110][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x110][&clk_reg_tc_sel]=0xef v.a \a_clock_data[&dbg_mux_gcc][0x110][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x110][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x110][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x110][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x111][&clk_str_name]="gcc_ufs_phy_rx_symbol_0_clk" v.a \a_clock_str[&dbg_mux_gcc][0x111][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x111][&clk_str_regname]="GCC_UFS_PHY_RX_SYMBOL_0_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x111][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x111][&clk_reg_cbc]=0x177020 v.a \a_clock_data[&dbg_mux_gcc][0x111][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x111][&clk_reg_tc_sel]=0xea v.a \a_clock_data[&dbg_mux_gcc][0x111][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x111][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x111][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x111][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x112][&clk_str_name]="gcc_ufs_phy_rx_symbol_1_clk" v.a \a_clock_str[&dbg_mux_gcc][0x112][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x112][&clk_str_regname]="GCC_UFS_PHY_RX_SYMBOL_1_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x112][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x112][&clk_reg_cbc]=0x1770b8 v.a \a_clock_data[&dbg_mux_gcc][0x112][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x112][&clk_reg_tc_sel]=0xf0 v.a \a_clock_data[&dbg_mux_gcc][0x112][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x112][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x112][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x112][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x113][&clk_str_name]="gcc_ufs_phy_tx_symbol_0_clk" v.a \a_clock_str[&dbg_mux_gcc][0x113][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x113][&clk_str_regname]="GCC_UFS_PHY_TX_SYMBOL_0_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x113][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x113][&clk_reg_cbc]=0x17701c v.a \a_clock_data[&dbg_mux_gcc][0x113][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x113][&clk_reg_tc_sel]=0xe9 v.a \a_clock_data[&dbg_mux_gcc][0x113][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x113][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x113][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x113][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x114][&clk_str_name]="gcc_ufs_phy_unipro_core_clk" v.a \a_clock_str[&dbg_mux_gcc][0x114][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x114][&clk_str_regname]="GCC_UFS_PHY_UNIPRO_CORE_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x114][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x114][&clk_reg_cbc]=0x17705c v.a \a_clock_data[&dbg_mux_gcc][0x114][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x114][&clk_reg_tc_sel]=0xed v.a \a_clock_data[&dbg_mux_gcc][0x114][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x114][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x114][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x114][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x115][&clk_str_name]="gcc_usb30_prim_master_clk" v.a \a_clock_str[&dbg_mux_gcc][0x115][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x115][&clk_str_regname]="GCC_USB30_PRIM_MASTER_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x115][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x115][&clk_reg_cbc]=0x10f010 v.a \a_clock_data[&dbg_mux_gcc][0x115][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x115][&clk_reg_tc_sel]=0x70 v.a \a_clock_data[&dbg_mux_gcc][0x115][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x115][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x115][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x115][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x116][&clk_str_name]="gcc_usb30_prim_mock_utmi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x116][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x116][&clk_str_regname]="GCC_USB30_PRIM_MOCK_UTMI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x116][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x116][&clk_reg_cbc]=0x10f01c v.a \a_clock_data[&dbg_mux_gcc][0x116][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x116][&clk_reg_tc_sel]=0x72 v.a \a_clock_data[&dbg_mux_gcc][0x116][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x116][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x116][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x116][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x117][&clk_str_name]="gcc_usb30_prim_sleep_clk" v.a \a_clock_str[&dbg_mux_gcc][0x117][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x117][&clk_str_regname]="GCC_USB30_PRIM_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x117][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x117][&clk_reg_cbc]=0x10f018 v.a \a_clock_data[&dbg_mux_gcc][0x117][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x117][&clk_reg_tc_sel]=0x71 v.a \a_clock_data[&dbg_mux_gcc][0x117][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x117][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x117][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x117][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x118][&clk_str_name]="gcc_usb3_prim_phy_aux_clk" v.a \a_clock_str[&dbg_mux_gcc][0x118][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x118][&clk_str_regname]="GCC_USB3_PRIM_PHY_AUX_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x118][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x118][&clk_reg_cbc]=0x10f054 v.a \a_clock_data[&dbg_mux_gcc][0x118][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x118][&clk_reg_tc_sel]=0x73 v.a \a_clock_data[&dbg_mux_gcc][0x118][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x118][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x118][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x118][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x119][&clk_str_name]="gcc_usb3_prim_phy_com_aux_clk" v.a \a_clock_str[&dbg_mux_gcc][0x119][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x119][&clk_str_regname]="GCC_USB3_PRIM_PHY_COM_AUX_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x119][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x119][&clk_reg_cbc]=0x10f058 v.a \a_clock_data[&dbg_mux_gcc][0x119][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x119][&clk_reg_tc_sel]=0x74 v.a \a_clock_data[&dbg_mux_gcc][0x119][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x119][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x119][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x119][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x11a][&clk_str_name]="gcc_usb3_prim_phy_pipe_clk" v.a \a_clock_str[&dbg_mux_gcc][0x11a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x11a][&clk_str_regname]="GCC_USB3_PRIM_PHY_PIPE_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x11a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x11a][&clk_reg_cbc]=0x10f05c v.a \a_clock_data[&dbg_mux_gcc][0x11a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x11a][&clk_reg_tc_sel]=0x75 v.a \a_clock_data[&dbg_mux_gcc][0x11a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x11a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x11a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x11a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x11b][&clk_str_name]="gcc_vdda_vs_clk" v.a \a_clock_str[&dbg_mux_gcc][0x11b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x11b][&clk_str_regname]="GCC_VDDA_VS_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x11b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x11b][&clk_reg_cbc]=0x17a00c v.a \a_clock_data[&dbg_mux_gcc][0x11b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x11b][&clk_reg_tc_sel]=0xf5 v.a \a_clock_data[&dbg_mux_gcc][0x11b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x11b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x11b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x11b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x11c][&clk_str_name]="gcc_vddcx_vs_clk" v.a \a_clock_str[&dbg_mux_gcc][0x11c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x11c][&clk_str_regname]="GCC_VDDCX_VS_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x11c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x11c][&clk_reg_cbc]=0x17a004 v.a \a_clock_data[&dbg_mux_gcc][0x11c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x11c][&clk_reg_tc_sel]=0xf3 v.a \a_clock_data[&dbg_mux_gcc][0x11c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x11c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x11c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x11c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x11d][&clk_str_name]="gcc_vddmx_vs_clk" v.a \a_clock_str[&dbg_mux_gcc][0x11d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x11d][&clk_str_regname]="GCC_VDDMX_VS_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x11d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x11d][&clk_reg_cbc]=0x17a008 v.a \a_clock_data[&dbg_mux_gcc][0x11d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x11d][&clk_reg_tc_sel]=0xf4 v.a \a_clock_data[&dbg_mux_gcc][0x11d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x11d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x11d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x11d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x11e][&clk_str_name]="gcc_video_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x11e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x11e][&clk_str_regname]="GCC_VIDEO_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x11e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x11e][&clk_reg_cbc]=0x10b004 v.a \a_clock_data[&dbg_mux_gcc][0x11e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x11e][&clk_reg_tc_sel]=0x3e v.a \a_clock_data[&dbg_mux_gcc][0x11e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x11e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x11e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x11e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x11f][&clk_str_name]="gcc_video_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x11f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x11f][&clk_str_regname]="GCC_VIDEO_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x11f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x11f][&clk_reg_cbc]=0x10b080 v.a \a_clock_data[&dbg_mux_gcc][0x11f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x11f][&clk_reg_tc_sel]=0x5a v.a \a_clock_data[&dbg_mux_gcc][0x11f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x11f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x11f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x11f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x120][&clk_str_name]="gcc_video_throttle1_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x120][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x120][&clk_str_regname]="GCC_VIDEO_THROTTLE1_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x120][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x120][&clk_reg_cbc]=0x10b084 v.a \a_clock_data[&dbg_mux_gcc][0x120][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x120][&clk_reg_tc_sel]=0x5c v.a \a_clock_data[&dbg_mux_gcc][0x120][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x120][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x120][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x120][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x121][&clk_str_name]="gcc_video_throttle_axi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x121][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x121][&clk_str_regname]="GCC_VIDEO_THROTTLE_AXI_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x121][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x121][&clk_reg_cbc]=0x10b024 v.a \a_clock_data[&dbg_mux_gcc][0x121][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x121][&clk_reg_tc_sel]=0x46 v.a \a_clock_data[&dbg_mux_gcc][0x121][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x121][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x121][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x121][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x122][&clk_str_name]="gcc_video_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x122][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x122][&clk_str_regname]="GCC_VIDEO_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x122][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x122][&clk_reg_cbc]=0x10b038 v.a \a_clock_data[&dbg_mux_gcc][0x122][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x122][&clk_reg_tc_sel]=0x4b v.a \a_clock_data[&dbg_mux_gcc][0x122][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x122][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x122][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x122][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x123][&clk_str_name]="gcc_vs_ctrl_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x123][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x123][&clk_str_regname]="GCC_VS_CTRL_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x123][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x123][&clk_reg_cbc]=0x17a014 v.a \a_clock_data[&dbg_mux_gcc][0x123][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x123][&clk_reg_tc_sel]=0xf7 v.a \a_clock_data[&dbg_mux_gcc][0x123][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x123][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x123][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x123][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x124][&clk_str_name]="gcc_vs_ctrl_clk" v.a \a_clock_str[&dbg_mux_gcc][0x124][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x124][&clk_str_regname]="GCC_VS_CTRL_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x124][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x124][&clk_reg_cbc]=0x17a010 v.a \a_clock_data[&dbg_mux_gcc][0x124][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x124][&clk_reg_tc_sel]=0xf6 v.a \a_clock_data[&dbg_mux_gcc][0x124][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x124][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x124][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x124][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x125][&clk_str_name]="gcc_wcss_ahb_s0_clk" v.a \a_clock_str[&dbg_mux_gcc][0x125][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x125][&clk_str_regname]="GCC_WCSS_AHB_S0_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x125][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x125][&clk_reg_cbc]=0x111000 v.a \a_clock_data[&dbg_mux_gcc][0x125][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x125][&clk_reg_tc_sel]=0x11f v.a \a_clock_data[&dbg_mux_gcc][0x125][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x125][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x125][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x125][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x126][&clk_str_name]="gcc_wcss_apb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x126][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x126][&clk_str_regname]="GCC_WCSS_APB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x126][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x126][&clk_reg_cbc]=0x111014 v.a \a_clock_data[&dbg_mux_gcc][0x126][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x126][&clk_reg_tc_sel]=0x124 v.a \a_clock_data[&dbg_mux_gcc][0x126][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x126][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x126][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x126][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x127][&clk_str_name]="gcc_wcss_at_clk" v.a \a_clock_str[&dbg_mux_gcc][0x127][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x127][&clk_str_regname]="GCC_WCSS_AT_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x127][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x127][&clk_reg_cbc]=0x111010 v.a \a_clock_data[&dbg_mux_gcc][0x127][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x127][&clk_reg_tc_sel]=0x123 v.a \a_clock_data[&dbg_mux_gcc][0x127][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x127][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x127][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x127][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x128][&clk_str_name]="gcc_wcss_axi_m_clk" v.a \a_clock_str[&dbg_mux_gcc][0x128][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x128][&clk_str_regname]="GCC_WCSS_AXI_M_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x128][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x128][&clk_reg_cbc]=0x111004 v.a \a_clock_data[&dbg_mux_gcc][0x128][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x128][&clk_reg_tc_sel]=0x120 v.a \a_clock_data[&dbg_mux_gcc][0x128][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x128][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x128][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x128][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x129][&clk_str_name]="gcc_wcss_ecahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x129][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x129][&clk_str_regname]="GCC_WCSS_ECAHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x129][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x129][&clk_reg_cbc]=0x111008 v.a \a_clock_data[&dbg_mux_gcc][0x129][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x129][&clk_reg_tc_sel]=0x121 v.a \a_clock_data[&dbg_mux_gcc][0x129][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x129][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x129][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x129][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x12a][&clk_str_name]="gcc_wcss_shdreg_ahb_clk" v.a \a_clock_str[&dbg_mux_gcc][0x12a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x12a][&clk_str_regname]="GCC_WCSS_SHDREG_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x12a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x12a][&clk_reg_cbc]=0x11100c v.a \a_clock_data[&dbg_mux_gcc][0x12a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x12a][&clk_reg_tc_sel]=0x122 v.a \a_clock_data[&dbg_mux_gcc][0x12a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x12a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x12a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x12a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x12b][&clk_str_name]="gcc_wcss_sleep_clk" v.a \a_clock_str[&dbg_mux_gcc][0x12b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x12b][&clk_str_regname]="GCC_WCSS_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x12b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x12b][&clk_reg_cbc]=0x111018 v.a \a_clock_data[&dbg_mux_gcc][0x12b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x12b][&clk_reg_tc_sel]=0x126 v.a \a_clock_data[&dbg_mux_gcc][0x12b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x12b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x12b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x12b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x12c][&clk_str_name]="gcc_wcss_vs_clk" v.a \a_clock_str[&dbg_mux_gcc][0x12c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x12c][&clk_str_regname]="GCC_WCSS_VS_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x12c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x12c][&clk_reg_cbc]=0x17a054 v.a \a_clock_data[&dbg_mux_gcc][0x12c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x12c][&clk_reg_tc_sel]=0xfb v.a \a_clock_data[&dbg_mux_gcc][0x12c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x12c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x12c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x12c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x12d][&clk_str_name]="gcc_xo_clk" v.a \a_clock_str[&dbg_mux_gcc][0x12d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x12d][&clk_str_regname]="GCC_XO_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x12d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x12d][&clk_reg_cbc]=0x143004 v.a \a_clock_data[&dbg_mux_gcc][0x12d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x12d][&clk_reg_tc_sel]=0xb1 v.a \a_clock_data[&dbg_mux_gcc][0x12d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x12d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x12d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x12d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x12e][&clk_str_name]="gcc_xo_div4_clk" v.a \a_clock_str[&dbg_mux_gcc][0x12e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x12e][&clk_str_regname]="GCC_XO_DIV4_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x12e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x12e][&clk_reg_cbc]=0x143008 v.a \a_clock_data[&dbg_mux_gcc][0x12e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x12e][&clk_reg_tc_sel]=0xb2 v.a \a_clock_data[&dbg_mux_gcc][0x12e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x12e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x12e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x12e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x12f][&clk_str_name]="gpu_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x12f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x12f][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x12f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x12f][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x12f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x12f][&clk_reg_tc_sel]=0x129 v.a \a_clock_data[&dbg_mux_gcc][0x12f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x12f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x12f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x12f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x130][&clk_str_name]="lpass_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x130][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x130][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x130][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x130][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x130][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x130][&clk_reg_tc_sel]=0xcc v.a \a_clock_data[&dbg_mux_gcc][0x130][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x130][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x130][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x130][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x131][&clk_str_name]="mdss_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x131][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x131][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x131][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x131][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x131][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x131][&clk_reg_tc_sel]=0x50 v.a \a_clock_data[&dbg_mux_gcc][0x131][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x131][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x131][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x131][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x132][&clk_str_name]="mss_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x132][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x132][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x132][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x132][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x132][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x132][&clk_reg_tc_sel]=0x11c v.a \a_clock_data[&dbg_mux_gcc][0x132][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x132][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x132][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x132][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x133][&clk_str_name]="nav_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x133][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x133][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x133][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x133][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x133][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x133][&clk_reg_tc_sel]=0x130 v.a \a_clock_data[&dbg_mux_gcc][0x133][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x133][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x133][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x133][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x134][&clk_str_name]="npu_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x134][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x134][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x134][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x134][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x134][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x134][&clk_reg_tc_sel]=0x13b v.a \a_clock_data[&dbg_mux_gcc][0x134][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x134][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x134][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x134][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x135][&clk_str_name]="qusb2phy_gcc_clk_test_prim" v.a \a_clock_str[&dbg_mux_gcc][0x135][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x135][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x135][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x135][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x135][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x135][&clk_reg_tc_sel]=0xe2 v.a \a_clock_data[&dbg_mux_gcc][0x135][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x135][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x135][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x135][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x136][&clk_str_name]="qusb2phy_gcc_clk_test_sec" v.a \a_clock_str[&dbg_mux_gcc][0x136][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x136][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x136][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x136][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x136][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x136][&clk_reg_tc_sel]=0xe3 v.a \a_clock_data[&dbg_mux_gcc][0x136][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x136][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x136][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x136][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x137][&clk_str_name]="qusb2phy_prim_gcc_usb30_utmi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x137][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x137][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x137][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x137][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x137][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x137][&clk_reg_tc_sel]=0x79 v.a \a_clock_data[&dbg_mux_gcc][0x137][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x137][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x137][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x137][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x138][&clk_str_name]="qusb2phy_sec_gcc_usb30_utmi_clk" v.a \a_clock_str[&dbg_mux_gcc][0x138][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x138][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x138][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x138][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x138][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x138][&clk_reg_tc_sel]=0x78 v.a \a_clock_data[&dbg_mux_gcc][0x138][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x138][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x138][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x138][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x139][&clk_str_name]="sleep_clk" v.a \a_clock_str[&dbg_mux_gcc][0x139][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x139][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x139][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x139][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x139][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x139][&clk_reg_tc_sel]=0xfc v.a \a_clock_data[&dbg_mux_gcc][0x139][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x139][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x139][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x139][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x13a][&clk_str_name]="tic_clk" v.a \a_clock_str[&dbg_mux_gcc][0x13a][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x13a][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x13a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x13a][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x13a][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x13a][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_gcc][0x13a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x13a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x13a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x13a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x13b][&clk_str_name]="turing_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x13b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x13b][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x13b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x13b][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x13b][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x13b][&clk_reg_tc_sel]=0xd4 v.a \a_clock_data[&dbg_mux_gcc][0x13b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x13b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x13b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x13b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x13c][&clk_str_name]="ufs_phy_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x13c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x13c][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x13c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x13c][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x13c][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x13c][&clk_reg_tc_sel]=0xf2 v.a \a_clock_data[&dbg_mux_gcc][0x13c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x13c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x13c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x13c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x13d][&clk_str_name]="ufs_phy_rx_symbol_0_clk" v.a \a_clock_str[&dbg_mux_gcc][0x13d][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x13d][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x13d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x13d][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x13d][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x13d][&clk_reg_tc_sel]=0xec v.a \a_clock_data[&dbg_mux_gcc][0x13d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x13d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x13d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x13d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x13e][&clk_str_name]="ufs_phy_rx_symbol_1_clk" v.a \a_clock_str[&dbg_mux_gcc][0x13e][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x13e][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x13e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x13e][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x13e][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x13e][&clk_reg_tc_sel]=0xf1 v.a \a_clock_data[&dbg_mux_gcc][0x13e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x13e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x13e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x13e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x13f][&clk_str_name]="ufs_phy_tx_symbol_0_clk" v.a \a_clock_str[&dbg_mux_gcc][0x13f][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x13f][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x13f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x13f][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x13f][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x13f][&clk_reg_tc_sel]=0xeb v.a \a_clock_data[&dbg_mux_gcc][0x13f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x13f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x13f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x13f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x140][&clk_str_name]="usb3_phy_wrapper_gcc_usb30_pipe_clk" v.a \a_clock_str[&dbg_mux_gcc][0x140][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gcc][0x140][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gcc][0x140][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x140][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x140][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x140][&clk_reg_tc_sel]=0x77 v.a \a_clock_data[&dbg_mux_gcc][0x140][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x140][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x140][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x140][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x141][&clk_str_name]="usb3dpphy_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x141][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x141][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x141][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x141][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x141][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x141][&clk_reg_tc_sel]=0x76 v.a \a_clock_data[&dbg_mux_gcc][0x141][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x141][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x141][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x141][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x142][&clk_str_name]="usb3phy_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x142][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x142][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x142][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x142][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x142][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x142][&clk_reg_tc_sel]=0x7a v.a \a_clock_data[&dbg_mux_gcc][0x142][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x142][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x142][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x142][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x143][&clk_str_name]="video_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x143][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x143][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x143][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x143][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x143][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x143][&clk_reg_tc_sel]=0x51 v.a \a_clock_data[&dbg_mux_gcc][0x143][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x143][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x143][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x143][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gcc][0x144][&clk_str_name]="wcss_gcc_debug_clk" v.a \a_clock_str[&dbg_mux_gcc][0x144][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gcc][0x144][&clk_str_regname]="GCC_DEBUG_CBCR" v.a \a_clock_str[&dbg_mux_gcc][0x144][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gcc][0x144][&clk_reg_cbc]=0x162008 v.a \a_clock_data[&dbg_mux_gcc][0x144][&clk_reg_tc_mux]=&dbg_mux_gcc v.a \a_clock_data[&dbg_mux_gcc][0x144][&clk_reg_tc_sel]=0x125 v.a \a_clock_data[&dbg_mux_gcc][0x144][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_gcc][0x144][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gcc][0x144][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gcc][0x144][&clk_reg_mux_input_en_mask]=0x0 ; GPU_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_gpu_cc][0x0][&clk_str_name]="gcc_gpu_apb_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x0][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_gpu_cc][0x0][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x1][&clk_str_name]="gcc_gpu_at_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x1][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x1][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x2][&clk_str_name]="gcc_gpu_cc_xo_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x2][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x2][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x2][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x2][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_gpu_cc][0x2][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x3][&clk_str_name]="gcc_gpu_cfg_ahb_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x3][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x3][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x3][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x3][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_gpu_cc][0x3][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x4][&clk_str_name]="gcc_gpu_sleep_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x4][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x4][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x4][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x4][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_gpu_cc][0x4][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x5][&clk_str_name]="gcc_gpu_snoc_dvm_gfx_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x5][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x5][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x5][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x5][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x5][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x6][&clk_str_name]="gcc_gpu_trig_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x6][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x6][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x6][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x6][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_gpu_cc][0x6][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x7][&clk_str_name]="gcc_gpu_vs_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x7][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x7][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x7][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x7][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_gpu_cc][0x7][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x8][&clk_str_name]="gcc_qdss_tsctr_div16_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x8][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x8][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_gpu_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x8][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x8][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_gpu_cc][0x8][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x9][&clk_str_name]="gpu_cc_acd_ahb_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x9][&clk_str_regname]="GPUCC_GPU_CC_ACD_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x9][&clk_reg_cbc]=0x3d91168 v.a \a_clock_data[&dbg_mux_gpu_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x9][&clk_reg_tc_sel]=0x20 v.a \a_clock_data[&dbg_mux_gpu_cc][0x9][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0xa][&clk_str_name]="gpu_cc_acd_cxo_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0xa][&clk_str_regname]="GPUCC_GPU_CC_ACD_CXO_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0xa][&clk_reg_cbc]=0x3d91164 v.a \a_clock_data[&dbg_mux_gpu_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0xa][&clk_reg_tc_sel]=0x1f v.a \a_clock_data[&dbg_mux_gpu_cc][0xa][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0xb][&clk_str_name]="gpu_cc_ahb_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0xb][&clk_str_regname]="GPUCC_GPU_CC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0xb][&clk_reg_cbc]=0x3d91078 v.a \a_clock_data[&dbg_mux_gpu_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0xb][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_gpu_cc][0xb][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0xc][&clk_str_name]="gpu_cc_crc_ahb_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0xc][&clk_str_regname]="GPUCC_GPU_CC_CRC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0xc][&clk_reg_cbc]=0x3d9107c v.a \a_clock_data[&dbg_mux_gpu_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0xc][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_gpu_cc][0xc][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0xd][&clk_str_name]="gpu_cc_cx_apb_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0xd][&clk_str_regname]="GPUCC_GPU_CC_CX_APB_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0xd][&clk_reg_cbc]=0x3d91088 v.a \a_clock_data[&dbg_mux_gpu_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0xd][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_gpu_cc][0xd][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0xe][&clk_str_name]="gpu_cc_cx_gfx3d_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0xe][&clk_str_regname]="GPUCC_GPU_CC_CX_GFX3D_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0xe][&clk_reg_cbc]=0x3d910a4 v.a \a_clock_data[&dbg_mux_gpu_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0xe][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_gpu_cc][0xe][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0xf][&clk_str_name]="gpu_cc_cx_gfx3d_slv_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0xf][&clk_str_regname]="GPUCC_GPU_CC_CX_GFX3D_SLV_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0xf][&clk_reg_cbc]=0x3d910a8 v.a \a_clock_data[&dbg_mux_gpu_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0xf][&clk_reg_tc_sel]=0x1b v.a \a_clock_data[&dbg_mux_gpu_cc][0xf][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x10][&clk_str_name]="gpu_cc_cx_gmu_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x10][&clk_str_regname]="GPUCC_GPU_CC_CX_GMU_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x10][&clk_reg_cbc]=0x3d91098 v.a \a_clock_data[&dbg_mux_gpu_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x10][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_gpu_cc][0x10][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x11][&clk_str_name]="gpu_cc_cx_qdss_at_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x11][&clk_str_regname]="GPUCC_GPU_CC_CX_QDSS_AT_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x11][&clk_reg_cbc]=0x3d91080 v.a \a_clock_data[&dbg_mux_gpu_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x11][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_gpu_cc][0x11][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x12][&clk_str_name]="gpu_cc_cx_qdss_trig_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x12][&clk_str_regname]="GPUCC_GPU_CC_CX_QDSS_TRIG_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x12][&clk_reg_cbc]=0x3d91094 v.a \a_clock_data[&dbg_mux_gpu_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x12][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_gpu_cc][0x12][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x13][&clk_str_name]="gpu_cc_cx_qdss_tsctr_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x13][&clk_str_regname]="GPUCC_GPU_CC_CX_QDSS_TSCTR_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x13][&clk_reg_cbc]=0x3d91084 v.a \a_clock_data[&dbg_mux_gpu_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x13][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_gpu_cc][0x13][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x14][&clk_str_name]="gpu_cc_cx_snoc_dvm_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x14][&clk_str_regname]="GPUCC_GPU_CC_CX_SNOC_DVM_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x14][&clk_reg_cbc]=0x3d9108c v.a \a_clock_data[&dbg_mux_gpu_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x14][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_gpu_cc][0x14][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x15][&clk_str_name]="gpu_cc_cxo_aon_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x15][&clk_str_regname]="GPUCC_GPU_CC_CXO_AON_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x15][&clk_reg_cbc]=0x3d91004 v.a \a_clock_data[&dbg_mux_gpu_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x15][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_gpu_cc][0x15][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x16][&clk_str_name]="gpu_cc_cxo_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x16][&clk_str_regname]="GPUCC_GPU_CC_CXO_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x16][&clk_reg_cbc]=0x3d9109c v.a \a_clock_data[&dbg_mux_gpu_cc][0x16][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x16][&clk_reg_tc_sel]=0x19 v.a \a_clock_data[&dbg_mux_gpu_cc][0x16][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x17][&clk_str_name]="gpu_cc_gx_cxo_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x17][&clk_str_regname]="GPUCC_GPU_CC_GX_CXO_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x17][&clk_reg_cbc]=0x3d91060 v.a \a_clock_data[&dbg_mux_gpu_cc][0x17][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x17][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_gpu_cc][0x17][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x18][&clk_str_name]="gpu_cc_gx_gfx3d_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x18][&clk_str_regname]="GPUCC_GPU_CC_GX_GFX3D_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x18][&clk_reg_cbc]=0x3d91054 v.a \a_clock_data[&dbg_mux_gpu_cc][0x18][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x18][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_gpu_cc][0x18][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x19][&clk_str_name]="gpu_cc_gx_gmu_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x19][&clk_str_regname]="GPUCC_GPU_CC_GX_GMU_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x19][&clk_reg_cbc]=0x3d91064 v.a \a_clock_data[&dbg_mux_gpu_cc][0x19][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x19][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_gpu_cc][0x19][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x1a][&clk_str_name]="gpu_cc_gx_qdss_tsctr_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1a][&clk_str_regname]="GPUCC_GPU_CC_GX_QDSS_TSCTR_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x1a][&clk_reg_cbc]=0x3d9105c v.a \a_clock_data[&dbg_mux_gpu_cc][0x1a][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x1a][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_gpu_cc][0x1a][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x1b][&clk_str_name]="gpu_cc_gx_vsense_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1b][&clk_str_regname]="GPUCC_GPU_CC_GX_VSENSE_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x1b][&clk_reg_cbc]=0x3d91058 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1b][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x1b][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_gpu_cc][0x1b][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x1c][&clk_str_name]="gpu_cc_rbcpr_ahb_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1c][&clk_str_regname]="GPUCC_GPU_CC_RBCPR_AHB_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x1c][&clk_reg_cbc]=0x3d910f4 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1c][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x1c][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_gpu_cc][0x1c][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x1d][&clk_str_name]="gpu_cc_rbcpr_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1d][&clk_str_regname]="GPUCC_GPU_CC_RBCPR_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x1d][&clk_reg_cbc]=0x3d910f0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1d][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x1d][&clk_reg_tc_sel]=0x1c v.a \a_clock_data[&dbg_mux_gpu_cc][0x1d][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x1e][&clk_str_name]="gpu_cc_sleep_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1e][&clk_str_regname]="GPUCC_GPU_CC_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x1e][&clk_reg_cbc]=0x3d91090 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1e][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x1e][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1e][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_gpu_cc][0x1f][&clk_str_name]="gpu_cc_spdm_gx_gfx3d_div_clk" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1f][&clk_str_regname]="GPUCC_GPU_CC_SPDM_GX_GFX3D_DIV_CBCR" v.a \a_clock_str[&dbg_mux_gpu_cc][0x1f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_gpu_cc][0x1f][&clk_reg_cbc]=0x3d91118 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1f][&clk_reg_tc_mux]=&dbg_mux_gpu_cc v.a \a_clock_data[&dbg_mux_gpu_cc][0x1f][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_gpu_cc][0x1f][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_gpu_cc][0x1f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_gpu_cc][0x1f][&clk_reg_mux_input_en_mask]=0x0 ; LPASS_AON_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x0][&clk_str_name]="lpass_aon_cc_ahb_timeout_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x0][&clk_str_regname]="LPASS_AHB_TIMEOUT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x0][&clk_reg_cbc]=0x3389030 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x0][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x0][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1][&clk_str_name]="lpass_aon_cc_aon_h_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1][&clk_str_regname]="LPASS_AON_H_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1][&clk_reg_cbc]=0x338903c v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x2][&clk_str_name]="lpass_aon_cc_at_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x2][&clk_str_regname]="LPASS_AT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x2][&clk_reg_cbc]=0x338a00c v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x2][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x2][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x3][&clk_str_name]="lpass_aon_cc_audio_hm_h_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x3][&clk_str_regname]="LPASS_AUDIO_HM_H_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x3][&clk_reg_cbc]=0x3389014 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x3][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x3][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x4][&clk_str_name]="lpass_aon_cc_audio_hm_sleep_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x4][&clk_str_regname]="LPASS_AUDIO_HM_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x4][&clk_reg_cbc]=0x3390010 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x4][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x4][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x5][&clk_str_name]="lpass_aon_cc_bus_alt_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x5][&clk_str_regname]="LPASS_BUS_ALT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x5][&clk_reg_cbc]=0x3389048 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x5][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x5][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x6][&clk_str_name]="lpass_aon_cc_cpr_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x6][&clk_str_regname]="LPASS_CPR_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x6][&clk_reg_cbc]=0x338200c v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x6][&clk_reg_tc_sel]=0x1b v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x6][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x7][&clk_str_name]="lpass_aon_cc_csr_h_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x7][&clk_str_regname]="LPASS_CSR_H_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x7][&clk_reg_cbc]=0x3389010 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x7][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x7][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x8][&clk_str_name]="lpass_aon_cc_dbg_tsctr_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x8][&clk_str_regname]="LPASS_DBG_TSCTR_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x8][&clk_reg_cbc]=0x338a058 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x8][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x8][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x9][&clk_str_name]="lpass_aon_cc_debug_h_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x9][&clk_str_regname]="LPASS_DEBUG_H_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x9][&clk_reg_cbc]=0x3389034 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x9][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x9][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xa][&clk_str_name]="lpass_aon_cc_mcc_access_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xa][&clk_str_regname]="LPASS_MCC_ACCESS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xa][&clk_reg_cbc]=0x338904c v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xa][&clk_reg_tc_sel]=0x24 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xa][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xb][&clk_str_name]="lpass_aon_cc_pclkdbg_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xb][&clk_str_regname]="LPASS_PCLKDBG_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xb][&clk_reg_cbc]=0x338a014 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xb][&clk_reg_tc_sel]=0x19 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xb][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xc][&clk_str_name]="lpass_aon_cc_pdc_gds_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xc][&clk_str_regname]="LPASS_PDC_GDS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xc][&clk_reg_cbc]=0x3383004 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xc][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xc][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xd][&clk_str_name]="lpass_aon_cc_pdc_h_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xd][&clk_str_regname]="LPASS_PDC_H_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xd][&clk_reg_cbc]=0x338900c v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xd][&clk_reg_tc_sel]=0x2f v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xd][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xe][&clk_str_name]="lpass_aon_cc_q6_ahbm_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xe][&clk_str_regname]="LPASS_Q6_AHBM_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xe][&clk_reg_cbc]=0x338901c v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xe][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xe][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xf][&clk_str_name]="lpass_aon_cc_q6_ahbs_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xf][&clk_str_regname]="LPASS_Q6_AHBS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xf][&clk_reg_cbc]=0x3389020 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xf][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xf][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x10][&clk_str_name]="lpass_aon_cc_q6_atbm_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x10][&clk_str_regname]="LPASS_Q6_ATBM_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x10][&clk_reg_cbc]=0x338a010 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x10][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x10][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x11][&clk_str_name]="lpass_aon_cc_q6_xo_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x11][&clk_str_regname]="LPASS_Q6_XO_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x11][&clk_reg_cbc]=0x338801c v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x11][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x11][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x12][&clk_str_name]="lpass_aon_cc_q6_xpu2_client_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x12][&clk_str_regname]="LPASS_Q6_XPU2_CLIENT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x12][&clk_reg_cbc]=0x338f000 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x12][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x12][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x13][&clk_str_name]="lpass_aon_cc_q6_xpu2_config_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x13][&clk_str_regname]="LPASS_Q6_XPU2_CONFIG_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x13][&clk_reg_cbc]=0x338f008 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x13][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x13][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x14][&clk_str_name]="lpass_aon_cc_qsm_xo_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x14][&clk_str_regname]="LPASS_QSM_XO_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x14][&clk_reg_cbc]=0x3386000 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x14][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x14][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x15][&clk_str_name]="lpass_aon_cc_ro_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x15][&clk_str_regname]="LPASS_RO_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x15][&clk_reg_cbc]=0x339000c v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x15][&clk_reg_tc_sel]=0x37 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x15][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x16][&clk_str_name]="lpass_aon_cc_rsc_hclk_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x16][&clk_str_regname]="LPASS_RSC_HCLK_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x16][&clk_reg_cbc]=0x3389078 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x16][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x16][&clk_reg_tc_sel]=0x21 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x16][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x17][&clk_str_name]="lpass_aon_cc_sleep_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x17][&clk_str_regname]="LPASS_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x17][&clk_reg_cbc]=0x3390004 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x17][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x17][&clk_reg_tc_sel]=0x2e v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x17][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x18][&clk_str_name]="lpass_aon_cc_ssc_h_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x18][&clk_str_regname]="LPASS_SSC_H_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x18][&clk_reg_cbc]=0x3389040 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x18][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x18][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x18][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x19][&clk_str_name]="lpass_aon_cc_t32_apb_access_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x19][&clk_str_regname]="LPASS_T32_APB_ACCESS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x19][&clk_reg_cbc]=0x3389038 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x19][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x19][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x19][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1a][&clk_str_name]="lpass_aon_cc_tx_mclk_2x_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1a][&clk_str_regname]="LPASS_TX_MCLK_2X_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1a][&clk_reg_cbc]=0x339300c v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1a][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1a][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1a][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1b][&clk_str_name]="lpass_aon_cc_tx_mclk_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1b][&clk_str_regname]="LPASS_TX_MCLK_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1b][&clk_reg_cbc]=0x3393014 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1b][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1b][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1b][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1c][&clk_str_name]="lpass_aon_cc_va_2x_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1c][&clk_str_regname]="LPASS_VA_2X_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1c][&clk_reg_cbc]=0x339200c v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1c][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1c][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1c][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1d][&clk_str_name]="lpass_aon_cc_va_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1d][&clk_str_regname]="LPASS_VA_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1d][&clk_reg_cbc]=0x3392014 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1d][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1d][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1d][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1e][&clk_str_name]="lpass_aon_cc_va_mem0_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1e][&clk_str_regname]="LPASS_VA_MEM0_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1e][&clk_reg_cbc]=0x3389028 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1e][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1e][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1e][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1f][&clk_str_name]="lpass_aon_cc_va_xpu2_client_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1f][&clk_str_regname]="LPASS_VA_XPU2_CLIENT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x1f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1f][&clk_reg_cbc]=0x338e000 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1f][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1f][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1f][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x1f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x20][&clk_str_name]="lpass_aon_cc_vs_vddcx_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x20][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x20][&clk_str_regname]="LPASS_VS_VDDCX_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x20][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x20][&clk_reg_cbc]=0x3395018 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x20][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x20][&clk_reg_tc_sel]=0x23 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x20][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x20][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x20][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x20][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x21][&clk_str_name]="lpass_aon_cc_vs_vddmx_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x21][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x21][&clk_str_regname]="LPASS_VS_VDDMX_CBCR" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x21][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x21][&clk_reg_cbc]=0x3395008 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x21][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x21][&clk_reg_tc_sel]=0x22 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x21][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x21][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x21][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x21][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x22][&clk_str_name]="lpass_audio_cc_dbg_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x22][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x22][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x22][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x22][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x22][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x22][&clk_reg_tc_sel]=0x3f v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x22][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x22][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x22][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x22][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x23][&clk_str_name]="lpass_audio_cc_pll_dtest" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x23][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x23][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x23][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x23][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x23][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x23][&clk_reg_tc_sel]=0x1f v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x23][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x23][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x23][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x23][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x24][&clk_str_name]="lpass_ssc_dbg_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x24][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x24][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x24][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x24][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x24][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x24][&clk_reg_tc_sel]=0x3e v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x24][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x24][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x24][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x24][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x25][&clk_str_name]="q6_pll_dtest" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x25][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x25][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x25][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x25][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x25][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x25][&clk_reg_tc_sel]=0x1c v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x25][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x25][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x25][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x25][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x26][&clk_str_name]="q6ss_dbg_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x26][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x26][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc][0x26][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x26][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x26][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x26][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x26][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x26][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x26][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc][0x26][&clk_reg_mux_input_en_mask]=0x0 ; LPASS_AON_CC_Q6 Controller Clock Names v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x0][&clk_str_name]="lpass_qdsp6ss_ahb_m_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x0][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc_q6 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x0][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x0][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x1][&clk_str_name]="lpass_qdsp6ss_ahb_s_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x1][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x1][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x1][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x1][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc_q6 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x1][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x1][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x2][&clk_str_name]="lpass_qdsp6ss_apb_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x2][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x2][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x2][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x2][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc_q6 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x2][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x2][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x3][&clk_str_name]="lpass_qdsp6ss_axi_m_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x3][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x3][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x3][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x3][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc_q6 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x3][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x3][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x4][&clk_str_name]="lpass_qdsp6ss_q6_core_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x4][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x4][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x4][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x4][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc_q6 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x4][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x4][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x5][&clk_str_name]="lpass_qdsp6ss_q6_core_div8_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x5][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x5][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x5][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x5][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc_q6 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x5][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x5][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x6][&clk_str_name]="lpass_qdsp6ss_sleep_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x6][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x6][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x6][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x6][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc_q6 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x6][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x6][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x7][&clk_str_name]="lpass_qdsp6ss_timestamp_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x7][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x7][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x7][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x7][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc_q6 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x7][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x7][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x8][&clk_str_name]="lpass_qdsp6ss_xo_clk" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x8][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x8][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_aon_cc_q6][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x8][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x8][&clk_reg_tc_mux]=&dbg_mux_lpass_aon_cc_q6 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x8][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x8][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_aon_cc_q6][0x8][&clk_reg_mux_input_en_mask]=0x0 ; LPASS_AUDIO_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x0][&clk_str_name]="lpass_audio_cc_bus_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x0][&clk_str_regname]="LPASS_AUDIO_CC_BUS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x0][&clk_reg_cbc]=0x331f000 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x0][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x0][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x1][&clk_str_name]="lpass_audio_cc_bus_timeout_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x1][&clk_str_regname]="LPASS_AUDIO_CC_BUS_TIMEOUT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x1][&clk_reg_cbc]=0x331e014 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x1][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x1][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x2][&clk_str_name]="lpass_audio_cc_codec_mem0_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x2][&clk_str_regname]="LPASS_AUDIO_CC_CODEC_MEM0_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x2][&clk_reg_cbc]=0x331e004 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x2][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x2][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x3][&clk_str_name]="lpass_audio_cc_codec_mem1_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x3][&clk_str_regname]="LPASS_AUDIO_CC_CODEC_MEM1_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x3][&clk_reg_cbc]=0x331e008 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x3][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x3][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x4][&clk_str_name]="lpass_audio_cc_codec_mem2_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x4][&clk_str_regname]="LPASS_AUDIO_CC_CODEC_MEM2_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x4][&clk_reg_cbc]=0x331e00c v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x4][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x4][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x5][&clk_str_name]="lpass_audio_cc_codec_mem_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x5][&clk_str_regname]="LPASS_AUDIO_CC_CODEC_MEM_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x5][&clk_reg_cbc]=0x331e000 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x5][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x5][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x6][&clk_str_name]="lpass_audio_cc_ext_if1_ebit_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x6][&clk_str_regname]="LPASS_AUDIO_CC_EXT_IF1_EBIT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x6][&clk_reg_cbc]=0x3310020 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x6][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x6][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x7][&clk_str_name]="lpass_audio_cc_ext_if1_ibit_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x7][&clk_str_regname]="LPASS_AUDIO_CC_EXT_IF1_IBIT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x7][&clk_reg_cbc]=0x331001c v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x7][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x7][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x8][&clk_str_name]="lpass_audio_cc_ext_if2_ebit_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x8][&clk_str_regname]="LPASS_AUDIO_CC_EXT_IF2_EBIT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x8][&clk_reg_cbc]=0x3311020 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x8][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x8][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x9][&clk_str_name]="lpass_audio_cc_ext_if2_ibit_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x9][&clk_str_regname]="LPASS_AUDIO_CC_EXT_IF2_IBIT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x9][&clk_reg_cbc]=0x331101c v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x9][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x9][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xa][&clk_str_name]="lpass_audio_cc_ext_if3_ebit_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xa][&clk_str_regname]="LPASS_AUDIO_CC_EXT_IF3_EBIT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xa][&clk_reg_cbc]=0x3312020 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xa][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xa][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xb][&clk_str_name]="lpass_audio_cc_ext_if3_ibit_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xb][&clk_str_regname]="LPASS_AUDIO_CC_EXT_IF3_IBIT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xb][&clk_reg_cbc]=0x331201c v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xb][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xb][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xc][&clk_str_name]="lpass_audio_cc_ext_mclk0_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xc][&clk_str_regname]="LPASS_AUDIO_CC_EXT_MCLK0_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xc][&clk_reg_cbc]=0x3320018 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xc][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xc][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xd][&clk_str_name]="lpass_audio_cc_ext_mclk1_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xd][&clk_str_regname]="LPASS_AUDIO_CC_EXT_MCLK1_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xd][&clk_reg_cbc]=0x3321018 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xd][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xd][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xe][&clk_str_name]="lpass_audio_cc_lpaif_pcmoe_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xe][&clk_str_regname]="LPASS_AUDIO_CC_LPAIF_PCMOE_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xe][&clk_reg_cbc]=0x3319018 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xe][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xe][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xf][&clk_str_name]="lpass_audio_cc_rx_mclk_2x_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xf][&clk_str_regname]="LPASS_AUDIO_CC_RX_MCLK_2X_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xf][&clk_reg_cbc]=0x33240cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xf][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xf][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x10][&clk_str_name]="lpass_audio_cc_rx_mclk_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x10][&clk_str_regname]="LPASS_AUDIO_CC_RX_MCLK_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x10][&clk_reg_cbc]=0x33240d4 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x10][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x10][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x11][&clk_str_name]="lpass_audio_cc_sampling_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x11][&clk_str_regname]="LPASS_AUDIO_CC_SAMPLING_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x11][&clk_reg_cbc]=0x3313000 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x11][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x11][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x12][&clk_str_name]="lpass_audio_cc_va_tx_mclk_mux_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x12][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x12][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x12][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x12][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x12][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x13][&clk_str_name]="lpass_audio_cc_wsa_mclk_2x_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x13][&clk_str_regname]="LPASS_AUDIO_CC_WSA_MCLK_2X_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x13][&clk_reg_cbc]=0x33220cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x13][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x13][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x14][&clk_str_name]="lpass_audio_cc_wsa_mclk_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x14][&clk_str_regname]="LPASS_AUDIO_CC_WSA_MCLK_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x14][&clk_reg_cbc]=0x33220d4 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x14][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x14][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x15][&clk_str_name]="lpass_audio_cc_xpu2_client_clk" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x15][&clk_str_regname]="LPASS_AUDIO_CC_XPU2_CLIENT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_audio_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x15][&clk_reg_cbc]=0x3301000 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_lpass_audio_cc v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x15][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x15][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_audio_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 ; LPASS_CORE_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x0][&clk_str_name]="atime_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x0][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x0][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1][&clk_str_name]="aud_slimbus_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x2][&clk_str_name]="bto_slp_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x2][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x2][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x2][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x2][&clk_reg_tc_sel]=0x21 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x2][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x3][&clk_str_name]="core_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x3][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x3][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x3][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x3][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x3][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x4][&clk_str_name]="ext_mclk0_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x4][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x4][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x4][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x4][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x4][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x5][&clk_str_name]="ext_mclk1_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x5][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x5][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x5][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x5][&clk_reg_tc_sel]=0x19 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x5][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x6][&clk_str_name]="ext_mclk2_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x6][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x6][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x6][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x6][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x6][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x7][&clk_str_name]="lpaif_pcmoe_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x7][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x7][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x7][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x7][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x7][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x8][&clk_str_name]="lpaif_pri_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x8][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x8][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x8][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x8][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x8][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x9][&clk_str_name]="lpaif_sec_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x9][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x9][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x9][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x9][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x9][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xa][&clk_str_name]="lpaif_ter_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xa][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xa][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xa][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xa][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xa][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xb][&clk_str_name]="lpass_audio_core_aud_slimbus_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xb][&clk_str_regname]="LPASS_AUDIO_CORE_AUD_SLIMBUS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xb][&clk_reg_cbc]=0x3917014 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xb][&clk_reg_tc_sel]=0x32 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xb][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xc][&clk_str_name]="lpass_audio_core_aud_slimbus_core_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xc][&clk_str_regname]="LPASS_AUDIO_CORE_AUD_SLIMBUS_CORE_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xc][&clk_reg_cbc]=0x3917018 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xc][&clk_reg_tc_sel]=0x36 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xc][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xd][&clk_str_name]="lpass_audio_core_aud_slimbus_npl_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xd][&clk_str_regname]="LPASS_AUDIO_CORE_AUD_SLIMBUS_NPL_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xd][&clk_reg_cbc]=0x391701c v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xd][&clk_reg_tc_sel]=0x58 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xd][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xe][&clk_str_name]="lpass_audio_core_avsync_atime_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xe][&clk_str_regname]="LPASS_AUDIO_CORE_AVSYNC_ATIME_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xe][&clk_reg_cbc]=0x3915014 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xe][&clk_reg_tc_sel]=0x2f v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xe][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xf][&clk_str_name]="lpass_audio_core_avsync_stc_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xf][&clk_str_regname]="LPASS_AUDIO_CORE_AVSYNC_STC_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xf][&clk_reg_cbc]=0x391c000 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xf][&clk_reg_tc_sel]=0x30 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xf][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x10][&clk_str_name]="lpass_audio_core_bus_timeout_core_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x10][&clk_str_regname]="LPASS_AUDIO_CORE_BUS_TIMEOUT_CORE_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x10][&clk_reg_cbc]=0x393b000 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x10][&clk_reg_tc_sel]=0x56 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x10][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x11][&clk_str_name]="lpass_audio_core_core_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x11][&clk_str_regname]="LPASS_AUDIO_CORE_CORE_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x11][&clk_reg_cbc]=0x391f000 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x11][&clk_reg_tc_sel]=0x34 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x11][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x12][&clk_str_name]="lpass_audio_core_ext_mclk0_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x12][&clk_str_regname]="LPASS_AUDIO_CORE_EXT_MCLK0_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x12][&clk_reg_cbc]=0x3920014 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x12][&clk_reg_tc_sel]=0x46 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x12][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x13][&clk_str_name]="lpass_audio_core_ext_mclk1_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x13][&clk_str_regname]="LPASS_AUDIO_CORE_EXT_MCLK1_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x13][&clk_reg_cbc]=0x3921014 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x13][&clk_reg_tc_sel]=0x47 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x13][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x14][&clk_str_name]="lpass_audio_core_ext_mclk2_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x14][&clk_str_regname]="LPASS_AUDIO_CORE_EXT_MCLK2_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x14][&clk_reg_cbc]=0x3922014 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x14][&clk_reg_tc_sel]=0x48 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x14][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x15][&clk_str_name]="lpass_audio_core_hw_af_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x15][&clk_str_regname]="LPASS_AUDIO_CORE_HW_AF_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x15][&clk_reg_cbc]=0x3940014 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x15][&clk_reg_tc_sel]=0x49 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x15][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x16][&clk_str_name]="lpass_audio_core_hw_af_noc_anoc_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x16][&clk_str_regname]="LPASS_AUDIO_CORE_HW_AF_NOC_ANOC_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x16][&clk_reg_cbc]=0x3940018 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x16][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x16][&clk_reg_tc_sel]=0x4a v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x16][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x17][&clk_str_name]="lpass_audio_core_hw_af_noc_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x17][&clk_str_regname]="LPASS_AUDIO_CORE_HW_AF_NOC_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x17][&clk_reg_cbc]=0x394001c v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x17][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x17][&clk_reg_tc_sel]=0x4b v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x17][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x18][&clk_str_name]="lpass_audio_core_lpaif_pcm_data_oe_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x18][&clk_str_regname]="LPASS_AUDIO_CORE_LPAIF_PCM_DATA_OE_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x18][&clk_reg_cbc]=0x3919014 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x18][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x18][&clk_reg_tc_sel]=0x2e v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x18][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x19][&clk_str_name]="lpass_audio_core_lpaif_pri_ibit_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x19][&clk_str_regname]="LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x19][&clk_reg_cbc]=0x3910018 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x19][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x19][&clk_reg_tc_sel]=0x27 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x19][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1a][&clk_str_name]="lpass_audio_core_lpaif_sec_ibit_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1a][&clk_str_regname]="LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1a][&clk_reg_cbc]=0x3911018 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1a][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1a][&clk_reg_tc_sel]=0x29 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1a][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1b][&clk_str_name]="lpass_audio_core_lpaif_ter_ibit_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1b][&clk_str_regname]="LPASS_AUDIO_CORE_LPAIF_TER_IBIT_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1b][&clk_reg_cbc]=0x3912018 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1b][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1b][&clk_reg_tc_sel]=0x2b v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1b][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1c][&clk_str_name]="lpass_audio_core_lpm_core_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1c][&clk_str_regname]="LPASS_AUDIO_CORE_LPM_CORE_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1c][&clk_reg_cbc]=0x391e000 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1c][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1c][&clk_reg_tc_sel]=0x57 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1c][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1d][&clk_str_name]="lpass_audio_core_lpm_mem0_core_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1d][&clk_str_regname]="LPASS_AUDIO_CORE_LPM_MEM0_CORE_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1d][&clk_reg_cbc]=0x391e004 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1d][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1d][&clk_reg_tc_sel]=0x38 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1d][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1e][&clk_str_name]="lpass_audio_core_q6ss_axim2_core_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1e][&clk_str_regname]="LPASS_AUDIO_CORE_Q6SS_AXIM2_CORE_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1e][&clk_reg_cbc]=0x3925000 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1e][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1e][&clk_reg_tc_sel]=0x3e v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1e][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1f][&clk_str_name]="lpass_audio_core_resampler_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1f][&clk_str_regname]="LPASS_AUDIO_CORE_RESAMPLER_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x1f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1f][&clk_reg_cbc]=0x3916098 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1f][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1f][&clk_reg_tc_sel]=0x31 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1f][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x1f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x20][&clk_str_name]="lpass_audio_core_sampling_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x20][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x20][&clk_str_regname]="LPASS_AUDIO_CORE_SAMPLING_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x20][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x20][&clk_reg_cbc]=0x390b008 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x20][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x20][&clk_reg_tc_sel]=0x23 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x20][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x20][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x20][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x20][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x21][&clk_str_name]="lpass_audio_core_sysnoc_mport_core_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x21][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x21][&clk_str_regname]="LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x21][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x21][&clk_reg_cbc]=0x3923000 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x21][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x21][&clk_reg_tc_sel]=0x35 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x21][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x21][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x21][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x21][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x22][&clk_str_name]="lpass_audio_core_sysnoc_sway_core_clk" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x22][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x22][&clk_str_regname]="LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CBCR" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x22][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x22][&clk_reg_cbc]=0x3924000 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x22][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x22][&clk_reg_tc_sel]=0x3f v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x22][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x22][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x22][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x22][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x23][&clk_str_name]="resampler_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x23][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x23][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x23][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x23][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x23][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x23][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x23][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x23][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x23][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x23][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x24][&clk_str_name]="sleep_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x24][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x24][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x24][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x24][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x24][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x24][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x24][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x24][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x24][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x24][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x25][&clk_str_name]="stc_xo_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x25][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x25][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x25][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x25][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x25][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x25][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x25][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x25][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x25][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x25][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x26][&clk_str_name]="xo_clk_src" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x26][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x26][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_lpass_core_cc][0x26][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x26][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x26][&clk_reg_tc_mux]=&dbg_mux_lpass_core_cc v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x26][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x26][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x26][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x26][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_core_cc][0x26][&clk_reg_mux_input_en_mask]=0x0 ; LPASS_TOP_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x0][&clk_str_name]="lpass_top_cc_aggnoc_hs_clk" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x0][&clk_str_regname]="LPASS_LPASS_TOP_CC_AGGNOC_HS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x0][&clk_reg_cbc]=0x3c03000 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_lpass_top_cc v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x0][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x1][&clk_str_name]="lpass_top_cc_aggnoc_ls_clk" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x1][&clk_str_regname]="LPASS_LPASS_TOP_CC_AGGNOC_LS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x1][&clk_reg_cbc]=0x3c06000 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_lpass_top_cc v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x1][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x2][&clk_str_name]="lpass_top_cc_aggnoc_mpu_ls_clk" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x2][&clk_str_regname]="LPASS_LPASS_TOP_CC_AGGNOC_MPU_LS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x2][&clk_reg_cbc]=0x3c07000 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_lpass_top_cc v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x2][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x3][&clk_str_name]="lpass_top_cc_lpass_core_sway_ahb_ls_clk" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x3][&clk_str_regname]="LPASS_LPASS_TOP_CC_LPASS_CORE_SWAY_AHB_LS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x3][&clk_reg_cbc]=0x3c09000 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_lpass_top_cc v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x3][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x4][&clk_str_name]="lpass_top_cc_lpi_q6_axim_hs_clk" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x4][&clk_str_regname]="LPASS_LPASS_TOP_CC_LPI_Q6_AXIM_HS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x4][&clk_reg_cbc]=0x3c04000 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_lpass_top_cc v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x4][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x5][&clk_str_name]="lpass_top_cc_lpi_sway_ahb_ls_clk" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x5][&clk_str_regname]="LPASS_LPASS_TOP_CC_LPI_SWAY_AHB_LS_CBCR" v.a \a_clock_str[&dbg_mux_lpass_top_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x5][&clk_reg_cbc]=0x3c08000 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_lpass_top_cc v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x5][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_lpass_top_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 ; MSS_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_mss_cc][0x0][&clk_str_name]="clk_timeout_slp" v.a \a_clock_str[&dbg_mux_mss_cc][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x0][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_mss_cc][0x0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x1][&clk_str_name]="mss_cc_axi_crypto_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x1][&clk_str_regname]="MSS_CC_AXI_CRYPTO_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x1][&clk_reg_cbc]=0x41ae410 v.a \a_clock_data[&dbg_mux_mss_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x1][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_mss_cc][0x1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x2][&clk_str_name]="mss_cc_axi_offline2_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x2][&clk_str_regname]="MSS_CC_AXI_OFFLINE2_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x2][&clk_reg_cbc]=0x41ae40c v.a \a_clock_data[&dbg_mux_mss_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x2][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_mss_cc][0x2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x3][&clk_str_name]="mss_cc_axi_offline_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x3][&clk_str_regname]="MSS_CC_AXI_OFFLINE_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x3][&clk_reg_cbc]=0x41ae408 v.a \a_clock_data[&dbg_mux_mss_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x3][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_mss_cc][0x3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x4][&clk_str_name]="mss_cc_bit_coxm2_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x4][&clk_str_regname]="MSS_CC_BIT_COXM2_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x4][&clk_reg_cbc]=0x41ae500 v.a \a_clock_data[&dbg_mux_mss_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x4][&clk_reg_tc_sel]=0x26 v.a \a_clock_data[&dbg_mux_mss_cc][0x4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x5][&clk_str_name]="mss_cc_bit_coxm2_mnd_clk_src" v.a \a_clock_str[&dbg_mux_mss_cc][0x5][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x5][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x5][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x5][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_mss_cc][0x5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x6][&clk_str_name]="mss_cc_bit_coxm_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x6][&clk_str_regname]="MSS_CC_BIT_COXM_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x6][&clk_reg_cbc]=0x41ae518 v.a \a_clock_data[&dbg_mux_mss_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x6][&clk_reg_tc_sel]=0x25 v.a \a_clock_data[&dbg_mux_mss_cc][0x6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x7][&clk_str_name]="mss_cc_bit_coxm_mnd_clk_src" v.a \a_clock_str[&dbg_mux_mss_cc][0x7][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x7][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x7][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x7][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x8][&clk_str_name]="mss_cc_bus_config_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x8][&clk_str_regname]="MSS_CC_BUS_CONFIG_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x8][&clk_reg_cbc]=0x41ae420 v.a \a_clock_data[&dbg_mux_mss_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x8][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_mss_cc][0x8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x9][&clk_str_name]="mss_cc_bus_coxm2_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x9][&clk_str_regname]="MSS_CC_BUS_COXM2_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x9][&clk_reg_cbc]=0x41ae42c v.a \a_clock_data[&dbg_mux_mss_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x9][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_mss_cc][0x9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0xa][&clk_str_name]="mss_cc_bus_coxm_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0xa][&clk_str_regname]="MSS_CC_BUS_COXM_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0xa][&clk_reg_cbc]=0x41ae428 v.a \a_clock_data[&dbg_mux_mss_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0xa][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_mss_cc][0xa][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0xb][&clk_str_name]="mss_cc_bus_crypto_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0xb][&clk_str_regname]="MSS_CC_BUS_CRYPTO_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0xb][&clk_reg_cbc]=0x41ae460 v.a \a_clock_data[&dbg_mux_mss_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0xb][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_mss_cc][0xb][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0xc][&clk_str_name]="mss_cc_bus_geran_encrypt_acc_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0xc][&clk_str_regname]="MSS_CC_BUS_GERAN_ENCRYPT_ACC_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0xc][&clk_reg_cbc]=0x41ae464 v.a \a_clock_data[&dbg_mux_mss_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0xc][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_mss_cc][0xc][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0xd][&clk_str_name]="mss_cc_bus_mgpi_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0xd][&clk_str_regname]="MSS_CC_BUS_MGPI_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0xd][&clk_reg_cbc]=0x41ae448 v.a \a_clock_data[&dbg_mux_mss_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0xd][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_mss_cc][0xd][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0xe][&clk_str_name]="mss_cc_bus_nav_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0xe][&clk_str_regname]="MSS_CC_BUS_NAV_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0xe][&clk_reg_cbc]=0x41ae468 v.a \a_clock_data[&dbg_mux_mss_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0xe][&clk_reg_tc_sel]=0x3e v.a \a_clock_data[&dbg_mux_mss_cc][0xe][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0xf][&clk_str_name]="mss_cc_bus_offline_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0xf][&clk_str_regname]="MSS_CC_BUS_OFFLINE_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0xf][&clk_reg_cbc]=0x41ae458 v.a \a_clock_data[&dbg_mux_mss_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0xf][&clk_reg_tc_sel]=0x3b v.a \a_clock_data[&dbg_mux_mss_cc][0xf][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x10][&clk_str_name]="mss_cc_bus_q6_alt_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x10][&clk_str_regname]="MSS_CC_BUS_Q6_ALT_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x10][&clk_reg_cbc]=0x41ae46c v.a \a_clock_data[&dbg_mux_mss_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x10][&clk_reg_tc_sel]=0x27 v.a \a_clock_data[&dbg_mux_mss_cc][0x10][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x11][&clk_str_name]="mss_cc_bus_q6_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x11][&clk_str_regname]="MSS_CC_BUS_Q6_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x11][&clk_reg_cbc]=0x41ae44c v.a \a_clock_data[&dbg_mux_mss_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x11][&clk_reg_tc_sel]=0x39 v.a \a_clock_data[&dbg_mux_mss_cc][0x11][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x12][&clk_str_name]="mss_cc_bus_rfc_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x12][&clk_str_regname]="MSS_CC_BUS_RFC_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x12][&clk_reg_cbc]=0x41ae424 v.a \a_clock_data[&dbg_mux_mss_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x12][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_mss_cc][0x12][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x13][&clk_str_name]="mss_cc_bus_rscc_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x13][&clk_str_regname]="MSS_CC_BUS_RSCC_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x13][&clk_reg_cbc]=0x41ae470 v.a \a_clock_data[&dbg_mux_mss_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x13][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_mss_cc][0x13][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x14][&clk_str_name]="mss_cc_bus_stmr_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x14][&clk_str_regname]="MSS_CC_BUS_STMR_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x14][&clk_reg_cbc]=0x41ae45c v.a \a_clock_data[&dbg_mux_mss_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x14][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_mss_cc][0x14][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x15][&clk_str_name]="mss_cc_bus_timeout_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x15][&clk_str_regname]="MSS_CC_BUS_TIMEOUT_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x15][&clk_reg_cbc]=0x41ae450 v.a \a_clock_data[&dbg_mux_mss_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x15][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_mss_cc][0x15][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x16][&clk_str_name]="mss_cc_bus_uim0_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x16][&clk_str_regname]="MSS_CC_BUS_UIM0_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x16][&clk_reg_cbc]=0x41ae430 v.a \a_clock_data[&dbg_mux_mss_cc][0x16][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x16][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_mss_cc][0x16][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x17][&clk_str_name]="mss_cc_bus_uim1_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x17][&clk_str_regname]="MSS_CC_BUS_UIM1_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x17][&clk_reg_cbc]=0x41ae434 v.a \a_clock_data[&dbg_mux_mss_cc][0x17][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x17][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_mss_cc][0x17][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x18][&clk_str_name]="mss_cc_bus_vq6ss_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x18][&clk_str_regname]="MSS_CC_BUS_VQ6SS_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x18][&clk_reg_cbc]=0x41ae454 v.a \a_clock_data[&dbg_mux_mss_cc][0x18][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x18][&clk_reg_tc_sel]=0x3a v.a \a_clock_data[&dbg_mux_mss_cc][0x18][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x19][&clk_str_name]="mss_cc_card_src_uim0_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x19][&clk_str_regname]="MSS_CC_CARD_SRC_UIM0_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x19][&clk_reg_cbc]=0x41ae4b4 v.a \a_clock_data[&dbg_mux_mss_cc][0x19][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x19][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_mss_cc][0x19][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x1a][&clk_str_name]="mss_cc_card_src_uim1_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x1a][&clk_str_regname]="MSS_CC_CARD_SRC_UIM1_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x1a][&clk_reg_cbc]=0x41ae4b8 v.a \a_clock_data[&dbg_mux_mss_cc][0x1a][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x1a][&clk_reg_tc_sel]=0x1f v.a \a_clock_data[&dbg_mux_mss_cc][0x1a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x1b][&clk_str_name]="mss_cc_dragon_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x1b][&clk_str_regname]="MSS_CC_DRAGON_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x1b][&clk_reg_cbc]=0x41ae47c v.a \a_clock_data[&dbg_mux_mss_cc][0x1b][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x1b][&clk_reg_tc_sel]=0x2d v.a \a_clock_data[&dbg_mux_mss_cc][0x1b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x1c][&clk_str_name]="mss_cc_q6vq6_axim1_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x1c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x1c][&clk_str_regname]="MSS_CC_Q6VQ6_AXIM1_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x1c][&clk_reg_cbc]=0x41ae414 v.a \a_clock_data[&dbg_mux_mss_cc][0x1c][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x1c][&clk_reg_tc_sel]=0x37 v.a \a_clock_data[&dbg_mux_mss_cc][0x1c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x1d][&clk_str_name]="mss_cc_rffe_2xo_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x1d][&clk_str_regname]="MSS_CC_RFFE_2XO_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x1d][&clk_reg_cbc]=0x41ae49c v.a \a_clock_data[&dbg_mux_mss_cc][0x1d][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x1d][&clk_reg_tc_sel]=0x1c v.a \a_clock_data[&dbg_mux_mss_cc][0x1d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x1e][&clk_str_name]="mss_cc_rffe_4xo_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x1e][&clk_str_regname]="MSS_CC_RFFE_4XO_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x1e][&clk_reg_cbc]=0x41ae498 v.a \a_clock_data[&dbg_mux_mss_cc][0x1e][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x1e][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_mss_cc][0x1e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x1e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x1f][&clk_str_name]="mss_cc_rffe_xo_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x1f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x1f][&clk_str_regname]="MSS_CC_RFFE_XO_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x1f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x1f][&clk_reg_cbc]=0x41ae4a0 v.a \a_clock_data[&dbg_mux_mss_cc][0x1f][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x1f][&clk_reg_tc_sel]=0x19 v.a \a_clock_data[&dbg_mux_mss_cc][0x1f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x1f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x1f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x1f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x20][&clk_str_name]="mss_cc_src_uim0_clk_src" v.a \a_clock_str[&dbg_mux_mss_cc][0x20][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x20][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x20][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x20][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x20][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x20][&clk_reg_tc_sel]=0x3c v.a \a_clock_data[&dbg_mux_mss_cc][0x20][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x20][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x20][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x20][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x21][&clk_str_name]="mss_cc_src_uim0_mnd_clk_src" v.a \a_clock_str[&dbg_mux_mss_cc][0x21][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x21][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x21][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x21][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x21][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x21][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_mss_cc][0x21][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x21][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x21][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x21][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x22][&clk_str_name]="mss_cc_src_uim1_clk_src" v.a \a_clock_str[&dbg_mux_mss_cc][0x22][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x22][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x22][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x22][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x22][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x22][&clk_reg_tc_sel]=0x3d v.a \a_clock_data[&dbg_mux_mss_cc][0x22][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x22][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x22][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x22][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x23][&clk_str_name]="mss_cc_src_uim1_mnd_clk_src" v.a \a_clock_str[&dbg_mux_mss_cc][0x23][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x23][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc][0x23][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x23][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x23][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x23][&clk_reg_tc_sel]=0x1b v.a \a_clock_data[&dbg_mux_mss_cc][0x23][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x23][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x23][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x23][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x24][&clk_str_name]="mss_cc_tcm_offline_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x24][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x24][&clk_str_regname]="MSS_CC_TCM_OFFLINE_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x24][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x24][&clk_reg_cbc]=0x41ae48c v.a \a_clock_data[&dbg_mux_mss_cc][0x24][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x24][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_mss_cc][0x24][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x24][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x24][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x24][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x25][&clk_str_name]="mss_cc_tcm_q6_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x25][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x25][&clk_str_regname]="MSS_CC_TCM_Q6_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x25][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x25][&clk_reg_cbc]=0x41ae488 v.a \a_clock_data[&dbg_mux_mss_cc][0x25][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x25][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_mss_cc][0x25][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x25][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x25][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x25][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x26][&clk_str_name]="mss_cc_uart_bit_uim0_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x26][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x26][&clk_str_regname]="MSS_CC_UART_BIT_UIM0_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x26][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x26][&clk_reg_cbc]=0x41ae4d0 v.a \a_clock_data[&dbg_mux_mss_cc][0x26][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x26][&clk_reg_tc_sel]=0x23 v.a \a_clock_data[&dbg_mux_mss_cc][0x26][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x26][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x26][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x26][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x27][&clk_str_name]="mss_cc_uart_bit_uim1_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x27][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x27][&clk_str_regname]="MSS_CC_UART_BIT_UIM1_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x27][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x27][&clk_reg_cbc]=0x41ae4e8 v.a \a_clock_data[&dbg_mux_mss_cc][0x27][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x27][&clk_reg_tc_sel]=0x24 v.a \a_clock_data[&dbg_mux_mss_cc][0x27][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x27][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x27][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x27][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x28][&clk_str_name]="mss_cc_xo_cx_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x28][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x28][&clk_str_regname]="MSS_CC_XO_CX_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x28][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x28][&clk_reg_cbc]=0x41ae400 v.a \a_clock_data[&dbg_mux_mss_cc][0x28][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x28][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_mss_cc][0x28][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x28][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x28][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x28][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc][0x29][&clk_str_name]="mss_cc_xo_rscc_clk" v.a \a_clock_str[&dbg_mux_mss_cc][0x29][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_mss_cc][0x29][&clk_str_regname]="MSS_CC_XO_RSCC_CBCR" v.a \a_clock_str[&dbg_mux_mss_cc][0x29][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc][0x29][&clk_reg_cbc]=0x41ae404 v.a \a_clock_data[&dbg_mux_mss_cc][0x29][&clk_reg_tc_mux]=&dbg_mux_mss_cc v.a \a_clock_data[&dbg_mux_mss_cc][0x29][&clk_reg_tc_sel]=0x2c v.a \a_clock_data[&dbg_mux_mss_cc][0x29][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc][0x29][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc][0x29][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc][0x29][&clk_reg_mux_input_en_mask]=0x0 ; MSS_CC_Q6 Controller Clock Names v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x0][&clk_str_name]="mss_qdsp6ss_ahb_m_clk" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x0][&clk_reg_tc_mux]=&dbg_mux_mss_cc_q6 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x0][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x1][&clk_str_name]="mss_qdsp6ss_ahb_s_clk" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x1][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x1][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x1][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x1][&clk_reg_tc_mux]=&dbg_mux_mss_cc_q6 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x1][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x2][&clk_str_name]="mss_qdsp6ss_apb_clk" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x2][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x2][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x2][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x2][&clk_reg_tc_mux]=&dbg_mux_mss_cc_q6 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x2][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x3][&clk_str_name]="mss_qdsp6ss_axi_m_clk" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x3][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x3][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x3][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x3][&clk_reg_tc_mux]=&dbg_mux_mss_cc_q6 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x3][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x4][&clk_str_name]="mss_qdsp6ss_q6_core_clk" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x4][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x4][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x4][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x4][&clk_reg_tc_mux]=&dbg_mux_mss_cc_q6 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x4][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x5][&clk_str_name]="mss_qdsp6ss_q6_core_div8_clk" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x5][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x5][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x5][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x5][&clk_reg_tc_mux]=&dbg_mux_mss_cc_q6 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x5][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x6][&clk_str_name]="mss_qdsp6ss_sleep_clk" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x6][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x6][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x6][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x6][&clk_reg_tc_mux]=&dbg_mux_mss_cc_q6 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x6][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x7][&clk_str_name]="mss_qdsp6ss_timestamp_clk" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x7][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x7][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x7][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x7][&clk_reg_tc_mux]=&dbg_mux_mss_cc_q6 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x7][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x8][&clk_str_name]="mss_qdsp6ss_xo_clk" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x8][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x8][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_q6][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x8][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x8][&clk_reg_tc_mux]=&dbg_mux_mss_cc_q6 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x8][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_q6][0x8][&clk_reg_mux_input_en_mask]=0x0 ; MSS_CC_VQ6 Controller Clock Names v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x0][&clk_str_name]="mss_vq6_qdsp6ss_ahb_m_clk" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x0][&clk_reg_tc_mux]=&dbg_mux_mss_cc_vq6 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x0][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x1][&clk_str_name]="mss_vq6_qdsp6ss_ahb_s_clk" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x1][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x1][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x1][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x1][&clk_reg_tc_mux]=&dbg_mux_mss_cc_vq6 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x1][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x2][&clk_str_name]="mss_vq6_qdsp6ss_apb_clk" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x2][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x2][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x2][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x2][&clk_reg_tc_mux]=&dbg_mux_mss_cc_vq6 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x2][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x3][&clk_str_name]="mss_vq6_qdsp6ss_axi_m_clk" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x3][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x3][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x3][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x3][&clk_reg_tc_mux]=&dbg_mux_mss_cc_vq6 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x3][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x4][&clk_str_name]="mss_vq6_qdsp6ss_q6_core_clk" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x4][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x4][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x4][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x4][&clk_reg_tc_mux]=&dbg_mux_mss_cc_vq6 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x4][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x5][&clk_str_name]="mss_vq6_qdsp6ss_q6_core_div8_clk" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x5][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x5][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x5][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x5][&clk_reg_tc_mux]=&dbg_mux_mss_cc_vq6 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x5][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x6][&clk_str_name]="mss_vq6_qdsp6ss_sleep_clk" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x6][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x6][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x6][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x6][&clk_reg_tc_mux]=&dbg_mux_mss_cc_vq6 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x6][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x7][&clk_str_name]="mss_vq6_qdsp6ss_timestamp_clk" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x7][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x7][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x7][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x7][&clk_reg_tc_mux]=&dbg_mux_mss_cc_vq6 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x7][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x8][&clk_str_name]="mss_vq6_qdsp6ss_xo_clk" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x8][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x8][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_mss_cc_vq6][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x8][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x8][&clk_reg_tc_mux]=&dbg_mux_mss_cc_vq6 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x8][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_mss_cc_vq6][0x8][&clk_reg_mux_input_en_mask]=0x0 ; NAV_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_nav_cc][0x0][&clk_str_name]="nav_cc_bb_core_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0x0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0x0][&clk_str_regname]="MSS_NAV_CC_BB_CORE_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0x0][&clk_reg_cbc]=0x4301a18 v.a \a_clock_data[&dbg_mux_nav_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0x0][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_nav_cc][0x0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0x1][&clk_str_name]="nav_cc_bb_core_dbg_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0x1][&clk_str_regname]="MSS_NAV_CC_BB_CORE_DBG_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0x1][&clk_reg_cbc]=0x4301a48 v.a \a_clock_data[&dbg_mux_nav_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0x1][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_nav_cc][0x1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0x2][&clk_str_name]="nav_cc_bb_main_clk_src" v.a \a_clock_str[&dbg_mux_nav_cc][0x2][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_nav_cc][0x2][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_nav_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0x2][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0x2][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0x2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0x3][&clk_str_name]="nav_cc_bb_qlink_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0x3][&clk_str_regname]="MSS_NAV_CC_BB_QLINK_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0x3][&clk_reg_cbc]=0x4301a2c v.a \a_clock_data[&dbg_mux_nav_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0x3][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_nav_cc][0x3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0x4][&clk_str_name]="nav_cc_cp_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0x4][&clk_str_regname]="MSS_NAV_CC_CP_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0x4][&clk_reg_cbc]=0x4301a20 v.a \a_clock_data[&dbg_mux_nav_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0x4][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_nav_cc][0x4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0x5][&clk_str_name]="nav_cc_dma_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0x5][&clk_str_regname]="MSS_NAV_CC_DMA_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0x5][&clk_reg_cbc]=0x4301a24 v.a \a_clock_data[&dbg_mux_nav_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0x5][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_nav_cc][0x5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0x6][&clk_str_name]="nav_cc_dp_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0x6][&clk_str_regname]="MSS_NAV_CC_DP_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0x6][&clk_reg_cbc]=0x4301a28 v.a \a_clock_data[&dbg_mux_nav_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0x6][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_nav_cc][0x6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0x7][&clk_str_name]="nav_cc_dragonlink_slv_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0x7][&clk_str_regname]="MSS_NAV_CC_DRAGONLINK_SLV_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0x7][&clk_reg_cbc]=0x4301a3c v.a \a_clock_data[&dbg_mux_nav_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0x7][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_nav_cc][0x7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0x8][&clk_str_name]="nav_cc_qlbr_rx_dbg_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0x8][&clk_str_regname]="MSS_NAV_CC_QLBR_RX_DBG_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0x8][&clk_reg_cbc]=0x4301a40 v.a \a_clock_data[&dbg_mux_nav_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0x8][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_nav_cc][0x8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0x9][&clk_str_name]="nav_cc_snoc_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0x9][&clk_str_regname]="MSS_NAV_CC_SNOC_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0x9][&clk_reg_cbc]=0x4301a30 v.a \a_clock_data[&dbg_mux_nav_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0x9][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_nav_cc][0x9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0xa][&clk_str_name]="nav_cc_snoc_dbg_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0xa][&clk_str_regname]="MSS_NAV_CC_SNOC_DBG_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0xa][&clk_reg_cbc]=0x4301a44 v.a \a_clock_data[&dbg_mux_nav_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0xa][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_nav_cc][0xa][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0xb][&clk_str_name]="nav_cc_stmr_xo_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0xb][&clk_str_regname]="MSS_NAV_CC_STMR_XO_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0xb][&clk_reg_cbc]=0x4301a34 v.a \a_clock_data[&dbg_mux_nav_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0xb][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_nav_cc][0xb][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_nav_cc][0xc][&clk_str_name]="nav_cc_xo_src_clk" v.a \a_clock_str[&dbg_mux_nav_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_nav_cc][0xc][&clk_str_regname]="MSS_NAV_CC_XO_SRC_CBCR" v.a \a_clock_str[&dbg_mux_nav_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_nav_cc][0xc][&clk_reg_cbc]=0x4301a38 v.a \a_clock_data[&dbg_mux_nav_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_nav_cc v.a \a_clock_data[&dbg_mux_nav_cc][0xc][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_nav_cc][0xc][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_nav_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_nav_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_nav_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 ; NPU_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_npu_cc][0x0][&clk_str_name]="dsp_npu_cc_q6ss_dbg_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_npu_cc][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_npu_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x0][&clk_reg_tc_sel]=0x20 v.a \a_clock_data[&dbg_mux_npu_cc][0x0][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x1][&clk_str_name]="npu_cc_aon_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x1][&clk_str_regname]="NPU_CC_AON_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x1][&clk_reg_cbc]=0x9981050 v.a \a_clock_data[&dbg_mux_npu_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x1][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_npu_cc][0x1][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x2][&clk_str_name]="npu_cc_atb_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x2][&clk_str_regname]="NPU_CC_ATB_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x2][&clk_reg_cbc]=0x99810d0 v.a \a_clock_data[&dbg_mux_npu_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x2][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_npu_cc][0x2][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x3][&clk_str_name]="npu_cc_bto_core_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x3][&clk_str_regname]="NPU_CC_BTO_CORE_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x3][&clk_reg_cbc]=0x99810dc v.a \a_clock_data[&dbg_mux_npu_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x3][&clk_reg_tc_sel]=0x19 v.a \a_clock_data[&dbg_mux_npu_cc][0x3][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x4][&clk_str_name]="npu_cc_bwmon_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x4][&clk_str_regname]="NPU_CC_BWMON_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x4][&clk_reg_cbc]=0x99810d8 v.a \a_clock_data[&dbg_mux_npu_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x4][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_npu_cc][0x4][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x5][&clk_str_name]="npu_cc_cal_hm0_cdc_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x5][&clk_str_regname]="NPU_CC_CAL_HM0_CDC_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x5][&clk_reg_cbc]=0x9981098 v.a \a_clock_data[&dbg_mux_npu_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x5][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_npu_cc][0x5][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x6][&clk_str_name]="npu_cc_cal_hm0_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x6][&clk_str_regname]="NPU_CC_CAL_HM0_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x6][&clk_reg_cbc]=0x9981110 v.a \a_clock_data[&dbg_mux_npu_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x6][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x6][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x7][&clk_str_name]="npu_cc_cal_hm0_dpm_ip_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x7][&clk_str_regname]="NPU_CC_CAL_HM0_DPM_IP_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x7][&clk_reg_cbc]=0x998109c v.a \a_clock_data[&dbg_mux_npu_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x7][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_npu_cc][0x7][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x8][&clk_str_name]="npu_cc_cal_hm0_perf_cnt_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x8][&clk_str_regname]="NPU_CC_CAL_HM0_PERF_CNT_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x8][&clk_reg_cbc]=0x99810a0 v.a \a_clock_data[&dbg_mux_npu_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x8][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_npu_cc][0x8][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x9][&clk_str_name]="npu_cc_core_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x9][&clk_str_regname]="NPU_CC_CORE_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x9][&clk_reg_cbc]=0x9981030 v.a \a_clock_data[&dbg_mux_npu_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x9][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_npu_cc][0x9][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0xa][&clk_str_name]="npu_cc_dl_dpm_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0xa][&clk_str_regname]="NPU_CC_DL_DPM_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0xa][&clk_reg_cbc]=0x9981238 v.a \a_clock_data[&dbg_mux_npu_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0xa][&clk_reg_tc_sel]=0x23 v.a \a_clock_data[&dbg_mux_npu_cc][0xa][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0xb][&clk_str_name]="npu_cc_dl_llm_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0xb][&clk_str_regname]="NPU_CC_DL_LLM_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0xb][&clk_reg_cbc]=0x9981234 v.a \a_clock_data[&dbg_mux_npu_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0xb][&clk_reg_tc_sel]=0x22 v.a \a_clock_data[&dbg_mux_npu_cc][0xb][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0xc][&clk_str_name]="npu_cc_dpm_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0xc][&clk_str_regname]="NPU_CC_DPM_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0xc][&clk_reg_cbc]=0x998107c v.a \a_clock_data[&dbg_mux_npu_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0xc][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_npu_cc][0xc][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0xd][&clk_str_name]="npu_cc_dpm_temp_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0xd][&clk_str_regname]="NPU_CC_DPM_TEMP_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0xd][&clk_reg_cbc]=0x99810c4 v.a \a_clock_data[&dbg_mux_npu_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0xd][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_npu_cc][0xd][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0xe][&clk_str_name]="npu_cc_dpm_xo_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0xe][&clk_str_regname]="NPU_CC_DPM_XO_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0xe][&clk_reg_cbc]=0x9981094 v.a \a_clock_data[&dbg_mux_npu_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0xe][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_npu_cc][0xe][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0xf][&clk_str_name]="npu_cc_dsp_ahbm_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0xf][&clk_str_regname]="NPU_CC_DSP_AHBM_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0xf][&clk_reg_cbc]=0x9981214 v.a \a_clock_data[&dbg_mux_npu_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0xf][&clk_reg_tc_sel]=0x1c v.a \a_clock_data[&dbg_mux_npu_cc][0xf][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x10][&clk_str_name]="npu_cc_dsp_ahbs_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x10][&clk_str_regname]="NPU_CC_DSP_AHBS_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x10][&clk_reg_cbc]=0x9981210 v.a \a_clock_data[&dbg_mux_npu_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x10][&clk_reg_tc_sel]=0x1b v.a \a_clock_data[&dbg_mux_npu_cc][0x10][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x11][&clk_str_name]="npu_cc_dsp_axi_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x11][&clk_str_regname]="NPU_CC_DSP_AXI_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x11][&clk_reg_cbc]=0x998121c v.a \a_clock_data[&dbg_mux_npu_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x11][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_npu_cc][0x11][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x12][&clk_str_name]="npu_cc_dsp_bwmon_ahb_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x12][&clk_str_regname]="NPU_CC_DSP_BWMON_AHB_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x12][&clk_reg_cbc]=0x9981218 v.a \a_clock_data[&dbg_mux_npu_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x12][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_npu_cc][0x12][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x13][&clk_str_name]="npu_cc_dsp_bwmon_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x13][&clk_str_regname]="NPU_CC_DSP_BWMON_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x13][&clk_reg_cbc]=0x9981224 v.a \a_clock_data[&dbg_mux_npu_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x13][&clk_reg_tc_sel]=0x1f v.a \a_clock_data[&dbg_mux_npu_cc][0x13][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x14][&clk_str_name]="npu_cc_isense_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x14][&clk_str_regname]="NPU_CC_ISENSE_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x14][&clk_reg_cbc]=0x9981078 v.a \a_clock_data[&dbg_mux_npu_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x14][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_npu_cc][0x14][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x15][&clk_str_name]="npu_cc_llm_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x15][&clk_str_regname]="NPU_CC_LLM_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x15][&clk_reg_cbc]=0x9981074 v.a \a_clock_data[&dbg_mux_npu_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x15][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_npu_cc][0x15][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x16][&clk_str_name]="npu_cc_llm_curr_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x16][&clk_str_regname]="NPU_CC_LLM_CURR_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x16][&clk_reg_cbc]=0x99810d4 v.a \a_clock_data[&dbg_mux_npu_cc][0x16][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x16][&clk_reg_tc_sel]=0x21 v.a \a_clock_data[&dbg_mux_npu_cc][0x16][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x17][&clk_str_name]="npu_cc_llm_temp_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x17][&clk_str_regname]="NPU_CC_LLM_TEMP_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x17][&clk_reg_cbc]=0x99810c8 v.a \a_clock_data[&dbg_mux_npu_cc][0x17][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x17][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_npu_cc][0x17][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x18][&clk_str_name]="npu_cc_llm_xo_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x18][&clk_str_regname]="NPU_CC_LLM_XO_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x18][&clk_reg_cbc]=0x9981090 v.a \a_clock_data[&dbg_mux_npu_cc][0x18][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x18][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_npu_cc][0x18][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x19][&clk_str_name]="npu_cc_noc_ahb_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x19][&clk_str_regname]="NPU_CC_NOC_AHB_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x19][&clk_reg_cbc]=0x99810c0 v.a \a_clock_data[&dbg_mux_npu_cc][0x19][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x19][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_npu_cc][0x19][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x1a][&clk_str_name]="npu_cc_noc_axi_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x1a][&clk_str_regname]="NPU_CC_NOC_AXI_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x1a][&clk_reg_cbc]=0x99810b8 v.a \a_clock_data[&dbg_mux_npu_cc][0x1a][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x1a][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_npu_cc][0x1a][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x1b][&clk_str_name]="npu_cc_noc_dma_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x1b][&clk_str_regname]="NPU_CC_NOC_DMA_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x1b][&clk_reg_cbc]=0x99810b0 v.a \a_clock_data[&dbg_mux_npu_cc][0x1b][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x1b][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_npu_cc][0x1b][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x1c][&clk_str_name]="npu_cc_rsc_xo_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x1c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x1c][&clk_str_regname]="NPU_CC_RSC_XO_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x1c][&clk_reg_cbc]=0x99810e0 v.a \a_clock_data[&dbg_mux_npu_cc][0x1c][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x1c][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_npu_cc][0x1c][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x1d][&clk_str_name]="npu_cc_s2p_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x1d][&clk_str_regname]="NPU_CC_S2P_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x1d][&clk_reg_cbc]=0x99810cc v.a \a_clock_data[&dbg_mux_npu_cc][0x1d][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x1d][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_npu_cc][0x1d][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc][0x1e][&clk_str_name]="npu_cc_xo_clk" v.a \a_clock_str[&dbg_mux_npu_cc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_npu_cc][0x1e][&clk_str_regname]="NPU_CC_XO_CBCR" v.a \a_clock_str[&dbg_mux_npu_cc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc][0x1e][&clk_reg_cbc]=0x9981410 v.a \a_clock_data[&dbg_mux_npu_cc][0x1e][&clk_reg_tc_mux]=&dbg_mux_npu_cc v.a \a_clock_data[&dbg_mux_npu_cc][0x1e][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_npu_cc][0x1e][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc][0x1e][&clk_reg_mux_input_en_mask]=0x0 ; NPU_CC_Q6 Controller Clock Names v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x0][&clk_str_name]="npu_qdsp6ss_ahb_m_clk" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x0][&clk_reg_tc_mux]=&dbg_mux_npu_cc_q6 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x0][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x0][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x1][&clk_str_name]="npu_qdsp6ss_ahb_s_clk" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x1][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x1][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x1][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x1][&clk_reg_tc_mux]=&dbg_mux_npu_cc_q6 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x1][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x1][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x2][&clk_str_name]="npu_qdsp6ss_apb_clk" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x2][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x2][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x2][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x2][&clk_reg_tc_mux]=&dbg_mux_npu_cc_q6 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x2][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x2][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x3][&clk_str_name]="npu_qdsp6ss_axi_m_clk" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x3][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x3][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x3][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x3][&clk_reg_tc_mux]=&dbg_mux_npu_cc_q6 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x3][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x3][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x4][&clk_str_name]="npu_qdsp6ss_q6_core_clk" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x4][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x4][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x4][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x4][&clk_reg_tc_mux]=&dbg_mux_npu_cc_q6 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x4][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x4][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x5][&clk_str_name]="npu_qdsp6ss_q6_core_div8_clk" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x5][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x5][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x5][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x5][&clk_reg_tc_mux]=&dbg_mux_npu_cc_q6 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x5][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x5][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x6][&clk_str_name]="npu_qdsp6ss_sleep_clk" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x6][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x6][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x6][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x6][&clk_reg_tc_mux]=&dbg_mux_npu_cc_q6 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x6][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x6][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x7][&clk_str_name]="npu_qdsp6ss_timestamp_clk" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x7][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x7][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x7][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x7][&clk_reg_tc_mux]=&dbg_mux_npu_cc_q6 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x7][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x7][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x8][&clk_str_name]="npu_qdsp6ss_xo_clk" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x8][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x8][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_npu_cc_q6][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x8][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x8][&clk_reg_tc_mux]=&dbg_mux_npu_cc_q6 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x8][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x8][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_npu_cc_q6][0x8][&clk_reg_mux_input_en_mask]=0x0 ; SCC Controller Clock Names v.a \a_clock_str[&dbg_mux_scc][0x0][&clk_str_name]="scc_ahb2ahb_m_clk" v.a \a_clock_str[&dbg_mux_scc][0x0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x0][&clk_str_regname]="SSC_SCC_AHB2AHB_M_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x0][&clk_reg_cbc]=0x3802008 v.a \a_clock_data[&dbg_mux_scc][0x0][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x0][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_scc][0x0][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_scc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x1][&clk_str_name]="scc_ahb_timeout_clk" v.a \a_clock_str[&dbg_mux_scc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x1][&clk_str_regname]="SSC_SCC_AHB_TIMEOUT_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x1][&clk_reg_cbc]=0x380201c v.a \a_clock_data[&dbg_mux_scc][0x1][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x1][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_scc][0x1][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_scc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x2][&clk_str_name]="scc_crif_clk" v.a \a_clock_str[&dbg_mux_scc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x2][&clk_str_regname]="SSC_SCC_CRIF_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x2][&clk_reg_cbc]=0x3802004 v.a \a_clock_data[&dbg_mux_scc][0x2][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x2][&clk_reg_tc_sel]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x2][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_scc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x3][&clk_str_name]="scc_csr_h_clk" v.a \a_clock_str[&dbg_mux_scc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x3][&clk_str_regname]="SSC_SCC_CSR_H_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x3][&clk_reg_cbc]=0x380200c v.a \a_clock_data[&dbg_mux_scc][0x3][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x3][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x3][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_scc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x4][&clk_str_name]="scc_mpu_client_clk" v.a \a_clock_str[&dbg_mux_scc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x4][&clk_str_regname]="SSC_SCC_MPU_CLIENT_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x4][&clk_reg_cbc]=0x3802030 v.a \a_clock_data[&dbg_mux_scc][0x4][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x4][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_scc][0x4][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_scc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x5][&clk_str_name]="scc_mpu_config_clk" v.a \a_clock_str[&dbg_mux_scc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x5][&clk_str_regname]="SSC_SCC_MPU_CONFIG_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x5][&clk_reg_cbc]=0x3802038 v.a \a_clock_data[&dbg_mux_scc][0x5][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x5][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_scc][0x5][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_scc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x6][&clk_str_name]="scc_qupv3_2xcore_clk" v.a \a_clock_str[&dbg_mux_scc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x6][&clk_str_regname]="SSC_SCC_QUPV3_2XCORE_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x6][&clk_reg_cbc]=0x380401c v.a \a_clock_data[&dbg_mux_scc][0x6][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x6][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_scc][0x6][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x6][&clk_reg_vote_bit]=0xb v.a \a_clock_data[&dbg_mux_scc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x7][&clk_str_name]="scc_qupv3_core_clk" v.a \a_clock_str[&dbg_mux_scc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x7][&clk_str_regname]="SSC_SCC_QUPV3_CORE_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x7][&clk_reg_cbc]=0x3804024 v.a \a_clock_data[&dbg_mux_scc][0x7][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x7][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_scc][0x7][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x7][&clk_reg_vote_bit]=0xc v.a \a_clock_data[&dbg_mux_scc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x8][&clk_str_name]="scc_qupv3_m_hclk_clk" v.a \a_clock_str[&dbg_mux_scc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x8][&clk_str_regname]="SSC_SCC_QUPV3_M_HCLK_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x8][&clk_reg_cbc]=0x3802028 v.a \a_clock_data[&dbg_mux_scc][0x8][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x8][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_scc][0x8][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x8][&clk_reg_vote_bit]=0x1 v.a \a_clock_data[&dbg_mux_scc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x9][&clk_str_name]="scc_qupv3_s_hclk_clk" v.a \a_clock_str[&dbg_mux_scc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x9][&clk_str_regname]="SSC_SCC_QUPV3_S_HCLK_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x9][&clk_reg_cbc]=0x3802024 v.a \a_clock_data[&dbg_mux_scc][0x9][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x9][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_scc][0x9][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x9][&clk_reg_vote_bit]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0xa][&clk_str_name]="scc_qupv3_se0_clk" v.a \a_clock_str[&dbg_mux_scc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0xa][&clk_str_regname]="SSC_SCC_QUPV3_SE0_CBCR" v.a \a_clock_str[&dbg_mux_scc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0xa][&clk_reg_cbc]=0x3805130 v.a \a_clock_data[&dbg_mux_scc][0xa][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0xa][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_scc][0xa][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0xa][&clk_reg_vote_bit]=0x3 v.a \a_clock_data[&dbg_mux_scc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0xb][&clk_str_name]="scc_qupv3_se1_clk" v.a \a_clock_str[&dbg_mux_scc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0xb][&clk_str_regname]="SSC_SCC_QUPV3_SE1_CBCR" v.a \a_clock_str[&dbg_mux_scc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0xb][&clk_reg_cbc]=0x3806130 v.a \a_clock_data[&dbg_mux_scc][0xb][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0xb][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_scc][0xb][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0xb][&clk_reg_vote_bit]=0x4 v.a \a_clock_data[&dbg_mux_scc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0xc][&clk_str_name]="scc_qupv3_se2_clk" v.a \a_clock_str[&dbg_mux_scc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0xc][&clk_str_regname]="SSC_SCC_QUPV3_SE2_CBCR" v.a \a_clock_str[&dbg_mux_scc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0xc][&clk_reg_cbc]=0x3807130 v.a \a_clock_data[&dbg_mux_scc][0xc][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0xc][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_scc][0xc][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0xc][&clk_reg_vote_bit]=0x5 v.a \a_clock_data[&dbg_mux_scc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0xd][&clk_str_name]="scc_qupv3_se3_clk" v.a \a_clock_str[&dbg_mux_scc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0xd][&clk_str_regname]="SSC_SCC_QUPV3_SE3_CBCR" v.a \a_clock_str[&dbg_mux_scc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0xd][&clk_reg_cbc]=0x3808130 v.a \a_clock_data[&dbg_mux_scc][0xd][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0xd][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_scc][0xd][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0xd][&clk_reg_vote_bit]=0x6 v.a \a_clock_data[&dbg_mux_scc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0xe][&clk_str_name]="scc_qupv3_se4_clk" v.a \a_clock_str[&dbg_mux_scc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0xe][&clk_str_regname]="SSC_SCC_QUPV3_SE4_CBCR" v.a \a_clock_str[&dbg_mux_scc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0xe][&clk_reg_cbc]=0x3809130 v.a \a_clock_data[&dbg_mux_scc][0xe][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0xe][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_scc][0xe][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0xe][&clk_reg_vote_bit]=0x7 v.a \a_clock_data[&dbg_mux_scc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0xf][&clk_str_name]="scc_qupv3_se5_clk" v.a \a_clock_str[&dbg_mux_scc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0xf][&clk_str_regname]="SSC_SCC_QUPV3_SE5_CBCR" v.a \a_clock_str[&dbg_mux_scc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0xf][&clk_reg_cbc]=0x380a130 v.a \a_clock_data[&dbg_mux_scc][0xf][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0xf][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_scc][0xf][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0xf][&clk_reg_vote_bit]=0x8 v.a \a_clock_data[&dbg_mux_scc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x10][&clk_str_name]="scc_qupv3_se6_clk" v.a \a_clock_str[&dbg_mux_scc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x10][&clk_str_regname]="SSC_SCC_QUPV3_SE6_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x10][&clk_reg_cbc]=0x380b130 v.a \a_clock_data[&dbg_mux_scc][0x10][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x10][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_scc][0x10][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x10][&clk_reg_vote_bit]=0x9 v.a \a_clock_data[&dbg_mux_scc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x11][&clk_str_name]="scc_qupv3_se7_clk" v.a \a_clock_str[&dbg_mux_scc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x11][&clk_str_regname]="SSC_SCC_QUPV3_SE7_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x11][&clk_reg_cbc]=0x380c12c v.a \a_clock_data[&dbg_mux_scc][0x11][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x11][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_scc][0x11][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x11][&clk_reg_vote_bit]=0xa v.a \a_clock_data[&dbg_mux_scc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x12][&clk_str_name]="scc_sleep_clk" v.a \a_clock_str[&dbg_mux_scc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x12][&clk_str_regname]="SSC_SCC_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x12][&clk_reg_cbc]=0x380d004 v.a \a_clock_data[&dbg_mux_scc][0x12][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x12][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_scc][0x12][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_scc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_scc][0x13][&clk_str_name]="scc_smem_clk" v.a \a_clock_str[&dbg_mux_scc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_scc][0x13][&clk_str_regname]="SSC_SCC_SMEM_CBCR" v.a \a_clock_str[&dbg_mux_scc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_scc][0x13][&clk_reg_cbc]=0x3802014 v.a \a_clock_data[&dbg_mux_scc][0x13][&clk_reg_tc_mux]=&dbg_mux_scc v.a \a_clock_data[&dbg_mux_scc][0x13][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_scc][0x13][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_scc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_scc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_scc][0x13][&clk_reg_mux_input_en_mask]=0x0 ; TURING_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_turing_cc][0x0][&clk_str_name]="aon_clk_src" v.a \a_clock_str[&dbg_mux_turing_cc][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x0][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_turing_cc][0x0][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x1][&clk_str_name]="bto_sleep_clk_src" v.a \a_clock_str[&dbg_mux_turing_cc][0x1][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x1][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x1][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x1][&clk_reg_tc_sel]=0x20 v.a \a_clock_data[&dbg_mux_turing_cc][0x1][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x2][&clk_str_name]="i_camss_dsp_streaming_0_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x2][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x2][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x2][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x2][&clk_reg_tc_sel]=0x2e v.a \a_clock_data[&dbg_mux_turing_cc][0x2][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x3][&clk_str_name]="i_camss_dsp_streaming_1_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x3][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x3][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x3][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x3][&clk_reg_tc_sel]=0x2f v.a \a_clock_data[&dbg_mux_turing_cc][0x3][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x4][&clk_str_name]="q6_xo_clk_src" v.a \a_clock_str[&dbg_mux_turing_cc][0x4][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x4][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x4][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x4][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_turing_cc][0x4][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x5][&clk_str_name]="q6ss_ahbm_aon_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x5][&clk_str_regname]="TURING_Q6SS_AHBM_AON_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x5][&clk_reg_cbc]=0x8009000 v.a \a_clock_data[&dbg_mux_turing_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x5][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_turing_cc][0x5][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x6][&clk_str_name]="q6ss_ahbs_aon_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x6][&clk_str_regname]="TURING_Q6SS_AHBS_AON_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x6][&clk_reg_cbc]=0x8010000 v.a \a_clock_data[&dbg_mux_turing_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x6][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_turing_cc][0x6][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x7][&clk_str_name]="q6ss_alt_reset_aon_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x7][&clk_str_regname]="TURING_Q6SS_ALT_RESET_AON_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x7][&clk_reg_cbc]=0x8004000 v.a \a_clock_data[&dbg_mux_turing_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x7][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_turing_cc][0x7][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x8][&clk_str_name]="q6ss_axis2_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x8][&clk_str_regname]="TURING_Q6SS_AXIS2_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x8][&clk_reg_cbc]=0x801a000 v.a \a_clock_data[&dbg_mux_turing_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x8][&clk_reg_tc_sel]=0x1b v.a \a_clock_data[&dbg_mux_turing_cc][0x8][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x9][&clk_str_name]="q6ss_dbg_in_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x9][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x9][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x9][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x9][&clk_reg_tc_sel]=0x27 v.a \a_clock_data[&dbg_mux_turing_cc][0x9][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0xa][&clk_str_name]="q6ss_q6_axim_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0xa][&clk_str_regname]="TURING_Q6SS_Q6_AXIM_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0xa][&clk_reg_cbc]=0x800b000 v.a \a_clock_data[&dbg_mux_turing_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0xa][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_turing_cc][0xa][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0xb][&clk_str_name]="q6ss_sleep_clk_src" v.a \a_clock_str[&dbg_mux_turing_cc][0xb][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0xb][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0xb][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0xb][&clk_reg_tc_sel]=0x21 v.a \a_clock_data[&dbg_mux_turing_cc][0xb][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0xc][&clk_str_name]="qos_fixed_lat_counter_clk_src" v.a \a_clock_str[&dbg_mux_turing_cc][0xc][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0xc][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0xc][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0xc][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_turing_cc][0xc][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0xd][&clk_str_name]="qos_xo_clk_src" v.a \a_clock_str[&dbg_mux_turing_cc][0xd][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0xd][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0xd][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0xd][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_turing_cc][0xd][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0xe][&clk_str_name]="turing_cc_cam_cc_ife_0_dsp_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0xe][&clk_str_regname]="TURING_CAM_CC_IFE_0_DSP_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0xe][&clk_reg_cbc]=0x801d400 v.a \a_clock_data[&dbg_mux_turing_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0xe][&clk_reg_tc_sel]=0x1f v.a \a_clock_data[&dbg_mux_turing_cc][0xe][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0xf][&clk_str_name]="turing_cc_cam_cc_ife_1_dsp_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0xf][&clk_str_regname]="TURING_CAM_CC_IFE_1_DSP_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0xf][&clk_reg_cbc]=0x801d800 v.a \a_clock_data[&dbg_mux_turing_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0xf][&clk_reg_tc_sel]=0x22 v.a \a_clock_data[&dbg_mux_turing_cc][0xf][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x10][&clk_str_name]="turing_cc_im_sleep_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x10][&clk_str_regname]="TURING_IM_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x10][&clk_reg_cbc]=0x8003004 v.a \a_clock_data[&dbg_mux_turing_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x10][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_turing_cc][0x10][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x11][&clk_str_name]="turing_cc_q6ss_axis_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x11][&clk_str_regname]="TURING_Q6SS_AXIS_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x11][&clk_reg_cbc]=0x800b400 v.a \a_clock_data[&dbg_mux_turing_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x11][&clk_reg_tc_sel]=0x30 v.a \a_clock_data[&dbg_mux_turing_cc][0x11][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x12][&clk_str_name]="turing_cc_strm_ahbs_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x12][&clk_str_regname]="TURING_STRM_AHBS_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x12][&clk_reg_cbc]=0x8020000 v.a \a_clock_data[&dbg_mux_turing_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x12][&clk_reg_tc_sel]=0x2b v.a \a_clock_data[&dbg_mux_turing_cc][0x12][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x13][&clk_str_name]="turing_cc_strm_axim_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x13][&clk_str_regname]="TURING_STRM_AXIM_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x13][&clk_reg_cbc]=0x801f000 v.a \a_clock_data[&dbg_mux_turing_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x13][&clk_reg_tc_sel]=0x28 v.a \a_clock_data[&dbg_mux_turing_cc][0x13][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x14][&clk_str_name]="turing_cc_strm_common0_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x14][&clk_str_regname]="TURING_STRM_COMMON0_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x14][&clk_reg_cbc]=0x801f400 v.a \a_clock_data[&dbg_mux_turing_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x14][&clk_reg_tc_sel]=0x29 v.a \a_clock_data[&dbg_mux_turing_cc][0x14][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x15][&clk_str_name]="turing_cc_strm_common1_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x15][&clk_str_regname]="TURING_STRM_COMMON1_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x15][&clk_reg_cbc]=0x801f800 v.a \a_clock_data[&dbg_mux_turing_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x15][&clk_reg_tc_sel]=0x2a v.a \a_clock_data[&dbg_mux_turing_cc][0x15][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x16][&clk_str_name]="turing_cc_strm_prog_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x16][&clk_str_regname]="TURING_STRM_PROG_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x16][&clk_reg_cbc]=0x801fc00 v.a \a_clock_data[&dbg_mux_turing_cc][0x16][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x16][&clk_reg_tc_sel]=0x31 v.a \a_clock_data[&dbg_mux_turing_cc][0x16][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x17][&clk_str_name]="turing_cc_vapss_ahbs_timeout_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x17][&clk_str_regname]="TURING_VAPSS_AHBS_TIMEOUT_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x17][&clk_reg_cbc]=0x8014400 v.a \a_clock_data[&dbg_mux_turing_cc][0x17][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x17][&clk_reg_tc_sel]=0x2d v.a \a_clock_data[&dbg_mux_turing_cc][0x17][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x18][&clk_str_name]="turing_cc_vapss_dma_ahbs_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x18][&clk_str_regname]="TURING_VAPSS_DMA_AHBS_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x18][&clk_reg_cbc]=0x8014800 v.a \a_clock_data[&dbg_mux_turing_cc][0x18][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x18][&clk_reg_tc_sel]=0x32 v.a \a_clock_data[&dbg_mux_turing_cc][0x18][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x19][&clk_str_name]="turing_cc_vapss_vma_ahbs_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x19][&clk_str_regname]="TURING_VAPSS_VMA_AHBS_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x19][&clk_reg_cbc]=0x8014c00 v.a \a_clock_data[&dbg_mux_turing_cc][0x19][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x19][&clk_reg_tc_sel]=0x33 v.a \a_clock_data[&dbg_mux_turing_cc][0x19][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x1a][&clk_str_name]="turing_wrapper_aon_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x1a][&clk_str_regname]="TURING_TURING_WRAPPER_AON_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x1a][&clk_reg_cbc]=0x8005098 v.a \a_clock_data[&dbg_mux_turing_cc][0x1a][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x1a][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x1a][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x1b][&clk_str_name]="turing_wrapper_bus_timeout_aon_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x1b][&clk_str_regname]="TURING_TURING_WRAPPER_BUS_TIMEOUT_AON_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x1b][&clk_reg_cbc]=0x8014000 v.a \a_clock_data[&dbg_mux_turing_cc][0x1b][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x1b][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_turing_cc][0x1b][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x1c][&clk_str_name]="turing_wrapper_bus_timeout_time_base" v.a \a_clock_str[&dbg_mux_turing_cc][0x1c][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x1c][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x1c][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x1c][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x1c][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_turing_cc][0x1c][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x1d][&clk_str_name]="turing_wrapper_cnoc_ahbs_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x1d][&clk_str_regname]="TURING_TURING_WRAPPER_CNOC_AHBS_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x1d][&clk_reg_cbc]=0x800a400 v.a \a_clock_data[&dbg_mux_turing_cc][0x1d][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x1d][&clk_reg_tc_sel]=0x1c v.a \a_clock_data[&dbg_mux_turing_cc][0x1d][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x1e][&clk_str_name]="turing_wrapper_cnoc_sway_aon_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x1e][&clk_str_regname]="TURING_TURING_WRAPPER_CNOC_SWAY_AON_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x1e][&clk_reg_cbc]=0x8008000 v.a \a_clock_data[&dbg_mux_turing_cc][0x1e][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x1e][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_turing_cc][0x1e][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x1e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x1f][&clk_str_name]="turing_wrapper_qos_ahbs_aon_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x1f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x1f][&clk_str_regname]="TURING_TURING_WRAPPER_QOS_AHBS_AON_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x1f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x1f][&clk_reg_cbc]=0x8011014 v.a \a_clock_data[&dbg_mux_turing_cc][0x1f][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x1f][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_turing_cc][0x1f][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x1f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x1f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x1f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x20][&clk_str_name]="turing_wrapper_qos_danger_fixed_lat_counter_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x20][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x20][&clk_str_regname]="TURING_TURING_WRAPPER_QOS_DANGER_FIXED_LAT_COUNTER_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x20][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x20][&clk_reg_cbc]=0x8011020 v.a \a_clock_data[&dbg_mux_turing_cc][0x20][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x20][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_turing_cc][0x20][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x20][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x20][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x20][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x21][&clk_str_name]="turing_wrapper_qos_dmonitor_fixed_lat_counter_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x21][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x21][&clk_str_regname]="TURING_TURING_WRAPPER_QOS_DMONITOR_FIXED_LAT_COUNTER_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x21][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x21][&clk_reg_cbc]=0x801101c v.a \a_clock_data[&dbg_mux_turing_cc][0x21][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x21][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_turing_cc][0x21][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x21][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x21][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x21][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x22][&clk_str_name]="turing_wrapper_qos_xo_lat_counter_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x22][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x22][&clk_str_regname]="TURING_TURING_WRAPPER_QOS_XO_LAT_COUNTER_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x22][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x22][&clk_reg_cbc]=0x8011018 v.a \a_clock_data[&dbg_mux_turing_cc][0x22][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x22][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_turing_cc][0x22][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x22][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x22][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x22][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x23][&clk_str_name]="turing_wrapper_rscc_aon_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x23][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x23][&clk_str_regname]="TURING_TURING_WRAPPER_RSCC_AON_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x23][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x23][&clk_reg_cbc]=0x8021004 v.a \a_clock_data[&dbg_mux_turing_cc][0x23][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x23][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_turing_cc][0x23][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x23][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x23][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x23][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x24][&clk_str_name]="turing_wrapper_rscc_xo_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x24][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x24][&clk_str_regname]="TURING_TURING_WRAPPER_RSCC_XO_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x24][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x24][&clk_reg_cbc]=0x8021000 v.a \a_clock_data[&dbg_mux_turing_cc][0x24][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x24][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_turing_cc][0x24][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x24][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x24][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x24][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x25][&clk_str_name]="vapss_ahbs_aon_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x25][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x25][&clk_str_regname]="TURING_VAPSS_AHBS_AON_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x25][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x25][&clk_reg_cbc]=0x801700c v.a \a_clock_data[&dbg_mux_turing_cc][0x25][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x25][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_turing_cc][0x25][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x25][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x25][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x25][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x26][&clk_str_name]="vapss_axi_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x26][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x26][&clk_str_regname]="TURING_VAPSS_AXI_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x26][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x26][&clk_reg_cbc]=0x8017008 v.a \a_clock_data[&dbg_mux_turing_cc][0x26][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x26][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_turing_cc][0x26][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x26][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x26][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x26][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x27][&clk_str_name]="vapss_bus_timeout_time_base" v.a \a_clock_str[&dbg_mux_turing_cc][0x27][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x27][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc][0x27][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x27][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x27][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x27][&clk_reg_tc_sel]=0x26 v.a \a_clock_data[&dbg_mux_turing_cc][0x27][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x27][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x27][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x27][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x28][&clk_str_name]="vapss_gdsc_xo_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x28][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x28][&clk_str_regname]="TURING_VAPSS_GDSC_XO_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x28][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x28][&clk_reg_cbc]=0x8016010 v.a \a_clock_data[&dbg_mux_turing_cc][0x28][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x28][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_turing_cc][0x28][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x28][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x28][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x28][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x29][&clk_str_name]="vapss_qsm_axi_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x29][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x29][&clk_str_regname]="TURING_VAPSS_QSM_AXI_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x29][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x29][&clk_reg_cbc]=0x8017408 v.a \a_clock_data[&dbg_mux_turing_cc][0x29][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x29][&clk_reg_tc_sel]=0x23 v.a \a_clock_data[&dbg_mux_turing_cc][0x29][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x29][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x29][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x29][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x2a][&clk_str_name]="vapss_vap_dma_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x2a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x2a][&clk_str_regname]="TURING_VAPSS_VAP_DMA_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x2a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x2a][&clk_reg_cbc]=0x8018014 v.a \a_clock_data[&dbg_mux_turing_cc][0x2a][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x2a][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_turing_cc][0x2a][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x2a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x2a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x2a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x2b][&clk_str_name]="vapss_vap_tcms_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x2b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x2b][&clk_str_regname]="TURING_VAPSS_VAP_TCMS_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x2b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x2b][&clk_reg_cbc]=0x8019014 v.a \a_clock_data[&dbg_mux_turing_cc][0x2b][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x2b][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_turing_cc][0x2b][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x2b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x2b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x2b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc][0x2c][&clk_str_name]="vapss_vap_vma_clk" v.a \a_clock_str[&dbg_mux_turing_cc][0x2c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_turing_cc][0x2c][&clk_str_regname]="TURING_VAPSS_VAP_VMA_CBCR" v.a \a_clock_str[&dbg_mux_turing_cc][0x2c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc][0x2c][&clk_reg_cbc]=0x8018114 v.a \a_clock_data[&dbg_mux_turing_cc][0x2c][&clk_reg_tc_mux]=&dbg_mux_turing_cc v.a \a_clock_data[&dbg_mux_turing_cc][0x2c][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_turing_cc][0x2c][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc][0x2c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc][0x2c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc][0x2c][&clk_reg_mux_input_en_mask]=0x0 ; TURING_CC_Q6 Controller Clock Names v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x0][&clk_str_name]="turing_qdsp6ss_ahb_m_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x0][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x0][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x0][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x0][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x0][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x0][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x1][&clk_str_name]="turing_qdsp6ss_ahb_s_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x1][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x1][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x1][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x1][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x1][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x1][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x2][&clk_str_name]="turing_qdsp6ss_apb_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x2][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x2][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x2][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x2][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x2][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x2][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x3][&clk_str_name]="turing_qdsp6ss_axi_m_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x3][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x3][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x3][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x3][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x3][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x3][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x4][&clk_str_name]="turing_qdsp6ss_llm_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x4][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x4][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x4][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x4][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x4][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x4][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x5][&clk_str_name]="turing_qdsp6ss_llm_curr_ssc_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x5][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x5][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x5][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x5][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x5][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x5][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x6][&clk_str_name]="turing_qdsp6ss_llm_temp_ssc_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x6][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x6][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x6][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x6][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x6][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x6][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x7][&clk_str_name]="turing_qdsp6ss_q6_core_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x7][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x7][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x7][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x7][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x7][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x7][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x8][&clk_str_name]="turing_qdsp6ss_q6_core_div8_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x8][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x8][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x8][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x8][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x8][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x8][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x9][&clk_str_name]="turing_qdsp6ss_sleep_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x9][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x9][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x9][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x9][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x9][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x9][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc_q6][0xa][&clk_str_name]="turing_qdsp6ss_timestamp_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0xa][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0xa][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xa][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xa][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xa][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xa][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_turing_cc_q6][0xb][&clk_str_name]="turing_qdsp6ss_xo_clk" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0xb][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0xb][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_turing_cc_q6][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xb][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xb][&clk_reg_tc_mux]=&dbg_mux_turing_cc_q6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xb][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xb][&clk_reg_total_div]=0x2 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_turing_cc_q6][0xb][&clk_reg_mux_input_en_mask]=0x0 ; VIDEO_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_video_cc][0x0][&clk_str_name]="video_cc_apb_clk" v.a \a_clock_str[&dbg_mux_video_cc][0x0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0x0][&clk_str_regname]="VIDEO_CC_APB_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0x0][&clk_reg_cbc]=0xab00a4c v.a \a_clock_data[&dbg_mux_video_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0x0][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_video_cc][0x0][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0x1][&clk_str_name]="video_cc_at_clk" v.a \a_clock_str[&dbg_mux_video_cc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0x1][&clk_str_regname]="VIDEO_CC_AT_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0x1][&clk_reg_cbc]=0xab00aac v.a \a_clock_data[&dbg_mux_video_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0x1][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_video_cc][0x1][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0x2][&clk_str_name]="video_cc_mvs0_axi_clk" v.a \a_clock_str[&dbg_mux_video_cc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0x2][&clk_str_regname]="VIDEO_CC_MVS0_AXI_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0x2][&clk_reg_cbc]=0xab009ec v.a \a_clock_data[&dbg_mux_video_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0x2][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_video_cc][0x2][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0x3][&clk_str_name]="video_cc_mvs0_core_clk" v.a \a_clock_str[&dbg_mux_video_cc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0x3][&clk_str_regname]="VIDEO_CC_MVS0_CORE_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0x3][&clk_reg_cbc]=0xab00890 v.a \a_clock_data[&dbg_mux_video_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0x3][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_video_cc][0x3][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0x4][&clk_str_name]="video_cc_mvs0_core_slp_stg_clk" v.a \a_clock_str[&dbg_mux_video_cc][0x4][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_video_cc][0x4][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_video_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0x4][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0x4][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_video_cc][0x4][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0x5][&clk_str_name]="video_cc_mvs1_axi_clk" v.a \a_clock_str[&dbg_mux_video_cc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0x5][&clk_str_regname]="VIDEO_CC_MVS1_AXI_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0x5][&clk_reg_cbc]=0xab00a0c v.a \a_clock_data[&dbg_mux_video_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0x5][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_video_cc][0x5][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0x6][&clk_str_name]="video_cc_mvs1_core_clk" v.a \a_clock_str[&dbg_mux_video_cc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0x6][&clk_str_regname]="VIDEO_CC_MVS1_CORE_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0x6][&clk_reg_cbc]=0xab008d0 v.a \a_clock_data[&dbg_mux_video_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0x6][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0x6][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0x7][&clk_str_name]="video_cc_mvs1_core_slp_stg_clk" v.a \a_clock_str[&dbg_mux_video_cc][0x7][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_video_cc][0x7][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_video_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0x7][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0x7][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_video_cc][0x7][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0x8][&clk_str_name]="video_cc_mvsc_core_clk" v.a \a_clock_str[&dbg_mux_video_cc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0x8][&clk_str_regname]="VIDEO_CC_MVSC_CORE_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0x8][&clk_reg_cbc]=0xab00850 v.a \a_clock_data[&dbg_mux_video_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0x8][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_video_cc][0x8][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0x9][&clk_str_name]="video_cc_mvsc_core_slp_stg_clk" v.a \a_clock_str[&dbg_mux_video_cc][0x9][&clk_str_type]="None" v.a \a_clock_str[&dbg_mux_video_cc][0x9][&clk_str_regname]="None" v.a \a_clock_str[&dbg_mux_video_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0x9][&clk_reg_cbc]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0x9][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_video_cc][0x9][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0xa][&clk_str_name]="video_cc_mvsc_ctl_axi_clk" v.a \a_clock_str[&dbg_mux_video_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0xa][&clk_str_regname]="VIDEO_CC_MVSC_CTL_AXI_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0xa][&clk_reg_cbc]=0xab009cc v.a \a_clock_data[&dbg_mux_video_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0xa][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_video_cc][0xa][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0xb][&clk_str_name]="video_cc_qdss_trig_clk" v.a \a_clock_str[&dbg_mux_video_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0xb][&clk_str_regname]="VIDEO_CC_QDSS_TRIG_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0xb][&clk_reg_cbc]=0xab00a2c v.a \a_clock_data[&dbg_mux_video_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0xb][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_video_cc][0xb][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0xc][&clk_str_name]="video_cc_qdss_tsctr_div8_clk" v.a \a_clock_str[&dbg_mux_video_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0xc][&clk_str_regname]="VIDEO_CC_QDSS_TSCTR_DIV8_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0xc][&clk_reg_cbc]=0xab00a8c v.a \a_clock_data[&dbg_mux_video_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0xc][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_video_cc][0xc][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0xd][&clk_str_name]="video_cc_sleep_clk" v.a \a_clock_str[&dbg_mux_video_cc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0xd][&clk_str_regname]="VIDEO_CC_SLEEP_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0xd][&clk_reg_cbc]=0xab009a4 v.a \a_clock_data[&dbg_mux_video_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0xd][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_video_cc][0xd][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0xe][&clk_str_name]="video_cc_venus_ahb_clk" v.a \a_clock_str[&dbg_mux_video_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0xe][&clk_str_regname]="VIDEO_CC_VENUS_AHB_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0xe][&clk_reg_cbc]=0xab00a6c v.a \a_clock_data[&dbg_mux_video_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0xe][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_video_cc][0xe][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_video_cc][0xf][&clk_str_name]="video_cc_xo_clk" v.a \a_clock_str[&dbg_mux_video_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_video_cc][0xf][&clk_str_regname]="VIDEO_CC_XO_CBCR" v.a \a_clock_str[&dbg_mux_video_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_video_cc][0xf][&clk_reg_cbc]=0xab00980 v.a \a_clock_data[&dbg_mux_video_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_video_cc v.a \a_clock_data[&dbg_mux_video_cc][0xf][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_video_cc][0xf][&clk_reg_total_div]=0x5 v.a \a_clock_data[&dbg_mux_video_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_video_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_video_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 ; WCSS_CC Controller Clock Names v.a \a_clock_str[&dbg_mux_wcss_cc][0x0][&clk_str_name]="wcss_cc_ahb_tslv_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x0][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x0][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_AHB_TSLV_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x0][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x0][&clk_reg_cbc]=0x189d1028 v.a \a_clock_data[&dbg_mux_wcss_cc][0x0][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x0][&clk_reg_tc_sel]=0x5 v.a \a_clock_data[&dbg_mux_wcss_cc][0x0][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x0][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x0][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x0][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x1][&clk_str_name]="wcss_cc_css_apb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_CSS_APB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x1][&clk_reg_cbc]=0x189d1014 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x1][&clk_reg_tc_sel]=0x4 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x1][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x2][&clk_str_name]="wcss_cc_css_noc_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_CSS_NOC_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x2][&clk_reg_cbc]=0x189d1008 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x2][&clk_reg_tc_sel]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x2][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x3][&clk_str_name]="wcss_cc_css_phy1_t240_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_CSS_PHY1_T240_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x3][&clk_reg_cbc]=0x189d1044 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x3][&clk_reg_tc_sel]=0x40 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x3][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x4][&clk_str_name]="wcss_cc_css_phy2_t240_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x4][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x4][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_CSS_PHY2_T240_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x4][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x4][&clk_reg_cbc]=0x189d1048 v.a \a_clock_data[&dbg_mux_wcss_cc][0x4][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x4][&clk_reg_tc_sel]=0x41 v.a \a_clock_data[&dbg_mux_wcss_cc][0x4][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x4][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x4][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x4][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x5][&clk_str_name]="wcss_cc_css_wsi_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x5][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x5][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_CSS_WSI_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x5][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x5][&clk_reg_cbc]=0x189d6034 v.a \a_clock_data[&dbg_mux_wcss_cc][0x5][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x5][&clk_reg_tc_sel]=0x2d v.a \a_clock_data[&dbg_mux_wcss_cc][0x5][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x5][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x5][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x5][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x6][&clk_str_name]="wcss_cc_dac_sm_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x6][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x6][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_DAC_SM_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x6][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x6][&clk_reg_cbc]=0x189d604c v.a \a_clock_data[&dbg_mux_wcss_cc][0x6][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x6][&clk_reg_tc_sel]=0x43 v.a \a_clock_data[&dbg_mux_wcss_cc][0x6][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x6][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x6][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x6][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x7][&clk_str_name]="wcss_cc_dbg_apb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x7][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x7][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_DBG_APB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x7][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x7][&clk_reg_cbc]=0x189d2014 v.a \a_clock_data[&dbg_mux_wcss_cc][0x7][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x7][&clk_reg_tc_sel]=0x7 v.a \a_clock_data[&dbg_mux_wcss_cc][0x7][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x7][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x7][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x7][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x8][&clk_str_name]="wcss_cc_dbg_atb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x8][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x8][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_DBG_ATB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x8][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x8][&clk_reg_cbc]=0x189d2010 v.a \a_clock_data[&dbg_mux_wcss_cc][0x8][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x8][&clk_reg_tc_sel]=0x6 v.a \a_clock_data[&dbg_mux_wcss_cc][0x8][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x8][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x8][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x8][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x9][&clk_str_name]="wcss_cc_dbg_css_apb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x9][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x9][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_DBG_CSS_APB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x9][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x9][&clk_reg_cbc]=0x189d103c v.a \a_clock_data[&dbg_mux_wcss_cc][0x9][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x9][&clk_reg_tc_sel]=0x36 v.a \a_clock_data[&dbg_mux_wcss_cc][0x9][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x9][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x9][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x9][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0xa][&clk_str_name]="wcss_cc_dbg_css_atb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0xa][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0xa][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_DBG_CSS_ATB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0xa][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0xa][&clk_reg_cbc]=0x189d1038 v.a \a_clock_data[&dbg_mux_wcss_cc][0xa][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0xa][&clk_reg_tc_sel]=0x35 v.a \a_clock_data[&dbg_mux_wcss_cc][0xa][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0xa][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0xa][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0xa][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0xb][&clk_str_name]="wcss_cc_dbg_css_ts_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0xb][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0xb][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_DBG_CSS_TS_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0xb][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0xb][&clk_reg_cbc]=0x189d1040 v.a \a_clock_data[&dbg_mux_wcss_cc][0xb][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0xb][&clk_reg_tc_sel]=0x37 v.a \a_clock_data[&dbg_mux_wcss_cc][0xb][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0xb][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0xb][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0xb][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0xc][&clk_str_name]="wcss_cc_dbg_ts_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0xc][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0xc][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_DBG_TS_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0xc][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0xc][&clk_reg_cbc]=0x189d2018 v.a \a_clock_data[&dbg_mux_wcss_cc][0xc][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0xc][&clk_reg_tc_sel]=0x8 v.a \a_clock_data[&dbg_mux_wcss_cc][0xc][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0xc][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0xc][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0xc][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0xd][&clk_str_name]="wcss_cc_phy1_11ac_radio_adc_0_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0xd][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0xd][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_11AC_RADIO_ADC_0_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0xd][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0xd][&clk_reg_cbc]=0x189d6060 v.a \a_clock_data[&dbg_mux_wcss_cc][0xd][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0xd][&clk_reg_tc_sel]=0x2e v.a \a_clock_data[&dbg_mux_wcss_cc][0xd][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0xd][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0xd][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0xd][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0xe][&clk_str_name]="wcss_cc_phy1_11ac_radio_adc_1_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0xe][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0xe][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_11AC_RADIO_ADC_1_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0xe][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0xe][&clk_reg_cbc]=0x189d6064 v.a \a_clock_data[&dbg_mux_wcss_cc][0xe][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0xe][&clk_reg_tc_sel]=0x2f v.a \a_clock_data[&dbg_mux_wcss_cc][0xe][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0xe][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0xe][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0xe][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0xf][&clk_str_name]="wcss_cc_phy1_160_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0xf][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0xf][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_160_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0xf][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0xf][&clk_reg_cbc]=0x189d3048 v.a \a_clock_data[&dbg_mux_wcss_cc][0xf][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0xf][&clk_reg_tc_sel]=0x12 v.a \a_clock_data[&dbg_mux_wcss_cc][0xf][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0xf][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0xf][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0xf][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x10][&clk_str_name]="wcss_cc_phy1_20_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x10][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x10][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_20_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x10][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x10][&clk_reg_cbc]=0x189d3060 v.a \a_clock_data[&dbg_mux_wcss_cc][0x10][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x10][&clk_reg_tc_sel]=0x15 v.a \a_clock_data[&dbg_mux_wcss_cc][0x10][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x10][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x10][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x10][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x11][&clk_str_name]="wcss_cc_phy1_30_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x11][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x11][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_30_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x11][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x11][&clk_reg_cbc]=0x189d3078 v.a \a_clock_data[&dbg_mux_wcss_cc][0x11][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x11][&clk_reg_tc_sel]=0x19 v.a \a_clock_data[&dbg_mux_wcss_cc][0x11][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x11][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x11][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x11][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x12][&clk_str_name]="wcss_cc_phy1_320_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x12][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x12][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_320_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x12][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x12][&clk_reg_cbc]=0x189d301c v.a \a_clock_data[&dbg_mux_wcss_cc][0x12][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x12][&clk_reg_tc_sel]=0xd v.a \a_clock_data[&dbg_mux_wcss_cc][0x12][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x12][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x12][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x12][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x13][&clk_str_name]="wcss_cc_phy1_40_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x13][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x13][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_40_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x13][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x13][&clk_reg_cbc]=0x189d3058 v.a \a_clock_data[&dbg_mux_wcss_cc][0x13][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x13][&clk_reg_tc_sel]=0x14 v.a \a_clock_data[&dbg_mux_wcss_cc][0x13][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x13][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x13][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x13][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x14][&clk_str_name]="wcss_cc_phy1_80_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x14][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x14][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_80_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x14][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x14][&clk_reg_cbc]=0x189d3050 v.a \a_clock_data[&dbg_mux_wcss_cc][0x14][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x14][&clk_reg_tc_sel]=0x13 v.a \a_clock_data[&dbg_mux_wcss_cc][0x14][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x14][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x14][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x14][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x15][&clk_str_name]="wcss_cc_phy1_apb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x15][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x15][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_APB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x15][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x15][&clk_reg_cbc]=0x189d1020 v.a \a_clock_data[&dbg_mux_wcss_cc][0x15][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x15][&clk_reg_tc_sel]=0xa v.a \a_clock_data[&dbg_mux_wcss_cc][0x15][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x15][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x15][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x15][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x16][&clk_str_name]="wcss_cc_phy1_bw_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x16][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x16][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_BW_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x16][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x16][&clk_reg_cbc]=0x189d3024 v.a \a_clock_data[&dbg_mux_wcss_cc][0x16][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x16][&clk_reg_tc_sel]=0xe v.a \a_clock_data[&dbg_mux_wcss_cc][0x16][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x16][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x16][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x16][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x17][&clk_str_name]="wcss_cc_phy1_bwx2_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x17][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x17][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_BWX2_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x17][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x17][&clk_reg_cbc]=0x189d302c v.a \a_clock_data[&dbg_mux_wcss_cc][0x17][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x17][&clk_reg_tc_sel]=0xf v.a \a_clock_data[&dbg_mux_wcss_cc][0x17][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x17][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x17][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x17][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x18][&clk_str_name]="wcss_cc_phy1_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x18][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x18][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x18][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x18][&clk_reg_cbc]=0x189d3040 v.a \a_clock_data[&dbg_mux_wcss_cc][0x18][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x18][&clk_reg_tc_sel]=0x11 v.a \a_clock_data[&dbg_mux_wcss_cc][0x18][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x18][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x18][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x18][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x19][&clk_str_name]="wcss_cc_phy1_dfs_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x19][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x19][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_DFS_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x19][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x19][&clk_reg_cbc]=0x189d3038 v.a \a_clock_data[&dbg_mux_wcss_cc][0x19][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x19][&clk_reg_tc_sel]=0x33 v.a \a_clock_data[&dbg_mux_wcss_cc][0x19][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x19][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x19][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x19][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x1a][&clk_str_name]="wcss_cc_phy1_t240_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1a][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_T240_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x1a][&clk_reg_cbc]=0x189d3074 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1a][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x1a][&clk_reg_tc_sel]=0x18 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x1a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x1b][&clk_str_name]="wcss_cc_phy1_tadc_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1b][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_TADC_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x1b][&clk_reg_cbc]=0x189d3070 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1b][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x1b][&clk_reg_tc_sel]=0x17 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x1b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x1c][&clk_str_name]="wcss_cc_phy1_tdac_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1c][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_TDAC_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x1c][&clk_reg_cbc]=0x189d3068 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1c][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x1c][&clk_reg_tc_sel]=0x16 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x1c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x1d][&clk_str_name]="wcss_cc_phy1_x2_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1d][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY1_X2_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x1d][&clk_reg_cbc]=0x189d3030 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1d][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x1d][&clk_reg_tc_sel]=0x10 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x1d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x1e][&clk_str_name]="wcss_cc_phy2_11ac_radio_adc_0_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1e][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_11AC_RADIO_ADC_0_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x1e][&clk_reg_cbc]=0x189d6068 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1e][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x1e][&clk_reg_tc_sel]=0x30 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x1e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x1f][&clk_str_name]="wcss_cc_phy2_11ac_radio_adc_1_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1f][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_11AC_RADIO_ADC_1_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x1f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x1f][&clk_reg_cbc]=0x189d606c v.a \a_clock_data[&dbg_mux_wcss_cc][0x1f][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x1f][&clk_reg_tc_sel]=0x31 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x1f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x1f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x20][&clk_str_name]="wcss_cc_phy2_160_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x20][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x20][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_160_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x20][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x20][&clk_reg_cbc]=0x189d4048 v.a \a_clock_data[&dbg_mux_wcss_cc][0x20][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x20][&clk_reg_tc_sel]=0x23 v.a \a_clock_data[&dbg_mux_wcss_cc][0x20][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x20][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x20][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x20][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x21][&clk_str_name]="wcss_cc_phy2_20_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x21][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x21][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_20_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x21][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x21][&clk_reg_cbc]=0x189d4060 v.a \a_clock_data[&dbg_mux_wcss_cc][0x21][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x21][&clk_reg_tc_sel]=0x26 v.a \a_clock_data[&dbg_mux_wcss_cc][0x21][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x21][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x21][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x21][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x22][&clk_str_name]="wcss_cc_phy2_30_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x22][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x22][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_30_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x22][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x22][&clk_reg_cbc]=0x189d4080 v.a \a_clock_data[&dbg_mux_wcss_cc][0x22][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x22][&clk_reg_tc_sel]=0x2a v.a \a_clock_data[&dbg_mux_wcss_cc][0x22][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x22][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x22][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x22][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x23][&clk_str_name]="wcss_cc_phy2_320_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x23][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x23][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_320_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x23][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x23][&clk_reg_cbc]=0x189d401c v.a \a_clock_data[&dbg_mux_wcss_cc][0x23][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x23][&clk_reg_tc_sel]=0x1e v.a \a_clock_data[&dbg_mux_wcss_cc][0x23][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x23][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x23][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x23][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x24][&clk_str_name]="wcss_cc_phy2_40_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x24][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x24][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_40_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x24][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x24][&clk_reg_cbc]=0x189d4058 v.a \a_clock_data[&dbg_mux_wcss_cc][0x24][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x24][&clk_reg_tc_sel]=0x25 v.a \a_clock_data[&dbg_mux_wcss_cc][0x24][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x24][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x24][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x24][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x25][&clk_str_name]="wcss_cc_phy2_80_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x25][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x25][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_80_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x25][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x25][&clk_reg_cbc]=0x189d4050 v.a \a_clock_data[&dbg_mux_wcss_cc][0x25][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x25][&clk_reg_tc_sel]=0x24 v.a \a_clock_data[&dbg_mux_wcss_cc][0x25][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x25][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x25][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x25][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x26][&clk_str_name]="wcss_cc_phy2_apb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x26][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x26][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_APB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x26][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x26][&clk_reg_cbc]=0x189d1024 v.a \a_clock_data[&dbg_mux_wcss_cc][0x26][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x26][&clk_reg_tc_sel]=0x1b v.a \a_clock_data[&dbg_mux_wcss_cc][0x26][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x26][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x26][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x26][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x27][&clk_str_name]="wcss_cc_phy2_bw_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x27][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x27][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_BW_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x27][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x27][&clk_reg_cbc]=0x189d4024 v.a \a_clock_data[&dbg_mux_wcss_cc][0x27][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x27][&clk_reg_tc_sel]=0x1f v.a \a_clock_data[&dbg_mux_wcss_cc][0x27][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x27][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x27][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x27][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x28][&clk_str_name]="wcss_cc_phy2_bwx2_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x28][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x28][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_BWX2_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x28][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x28][&clk_reg_cbc]=0x189d402c v.a \a_clock_data[&dbg_mux_wcss_cc][0x28][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x28][&clk_reg_tc_sel]=0x20 v.a \a_clock_data[&dbg_mux_wcss_cc][0x28][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x28][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x28][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x28][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x29][&clk_str_name]="wcss_cc_phy2_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x29][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x29][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x29][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x29][&clk_reg_cbc]=0x189d4040 v.a \a_clock_data[&dbg_mux_wcss_cc][0x29][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x29][&clk_reg_tc_sel]=0x22 v.a \a_clock_data[&dbg_mux_wcss_cc][0x29][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x29][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x29][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x29][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x2a][&clk_str_name]="wcss_cc_phy2_dfs_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2a][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_DFS_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x2a][&clk_reg_cbc]=0x189d4038 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2a][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x2a][&clk_reg_tc_sel]=0x34 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x2a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x2b][&clk_str_name]="wcss_cc_phy2_t240_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2b][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_T240_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x2b][&clk_reg_cbc]=0x189d4078 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2b][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x2b][&clk_reg_tc_sel]=0x29 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x2b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x2c][&clk_str_name]="wcss_cc_phy2_tadc_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2c][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_TADC_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x2c][&clk_reg_cbc]=0x189d4070 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2c][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x2c][&clk_reg_tc_sel]=0x28 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x2c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x2d][&clk_str_name]="wcss_cc_phy2_tdac_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2d][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_TDAC_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x2d][&clk_reg_cbc]=0x189d4068 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2d][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x2d][&clk_reg_tc_sel]=0x27 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x2d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x2e][&clk_str_name]="wcss_cc_phy2_x2_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2e][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_PHY2_X2_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x2e][&clk_reg_cbc]=0x189d4030 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2e][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x2e][&clk_reg_tc_sel]=0x21 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x2e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x2f][&clk_str_name]="wcss_cc_rfactrl_apb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2f][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_RFACTRL_APB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x2f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x2f][&clk_reg_cbc]=0x189d60cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x2f][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x2f][&clk_reg_tc_sel]=0x39 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x2f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x2f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x30][&clk_str_name]="wcss_cc_rfactrl_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x30][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x30][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_RFACTRL_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x30][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x30][&clk_reg_cbc]=0x189d60e0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x30][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x30][&clk_reg_tc_sel]=0x32 v.a \a_clock_data[&dbg_mux_wcss_cc][0x30][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x30][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x30][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x30][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x31][&clk_str_name]="wcss_cc_rfactrl_dac_apb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x31][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x31][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_RFACTRL_DAC_APB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x31][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x31][&clk_reg_cbc]=0x189d60e4 v.a \a_clock_data[&dbg_mux_wcss_cc][0x31][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x31][&clk_reg_tc_sel]=0x3e v.a \a_clock_data[&dbg_mux_wcss_cc][0x31][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x31][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x31][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x31][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x32][&clk_str_name]="wcss_cc_rfactrl_phy1_11ac_radio_adc_0_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x32][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x32][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_RFACTRL_PHY1_11AC_RADIO_ADC_0_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x32][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x32][&clk_reg_cbc]=0x189d60d8 v.a \a_clock_data[&dbg_mux_wcss_cc][0x32][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x32][&clk_reg_tc_sel]=0x3c v.a \a_clock_data[&dbg_mux_wcss_cc][0x32][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x32][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x32][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x32][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x33][&clk_str_name]="wcss_cc_rfactrl_phy1_11ac_radio_adc_1_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x33][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x33][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_RFACTRL_PHY1_11AC_RADIO_ADC_1_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x33][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x33][&clk_reg_cbc]=0x189d60dc v.a \a_clock_data[&dbg_mux_wcss_cc][0x33][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x33][&clk_reg_tc_sel]=0x3d v.a \a_clock_data[&dbg_mux_wcss_cc][0x33][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x33][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x33][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x33][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x34][&clk_str_name]="wcss_cc_rfactrl_phy1_80_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x34][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x34][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_RFACTRL_PHY1_80_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x34][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x34][&clk_reg_cbc]=0x189d60d0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x34][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x34][&clk_reg_tc_sel]=0x3a v.a \a_clock_data[&dbg_mux_wcss_cc][0x34][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x34][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x34][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x34][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x35][&clk_str_name]="wcss_cc_rfactrl_phy2_80_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x35][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x35][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_RFACTRL_PHY2_80_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x35][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x35][&clk_reg_cbc]=0x189d60d4 v.a \a_clock_data[&dbg_mux_wcss_cc][0x35][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x35][&clk_reg_tc_sel]=0x3b v.a \a_clock_data[&dbg_mux_wcss_cc][0x35][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x35][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x35][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x35][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x36][&clk_str_name]="wcss_cc_top_ahb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x36][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x36][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_TOP_AHB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x36][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x36][&clk_reg_cbc]=0x189d1010 v.a \a_clock_data[&dbg_mux_wcss_cc][0x36][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x36][&clk_reg_tc_sel]=0x3 v.a \a_clock_data[&dbg_mux_wcss_cc][0x36][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x36][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x36][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x36][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x37][&clk_str_name]="wcss_cc_top_axi_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x37][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x37][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_TOP_AXI_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x37][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x37][&clk_reg_cbc]=0x189d100c v.a \a_clock_data[&dbg_mux_wcss_cc][0x37][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x37][&clk_reg_tc_sel]=0x2 v.a \a_clock_data[&dbg_mux_wcss_cc][0x37][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x37][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x37][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x37][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x38][&clk_str_name]="wcss_cc_top_dac_apb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x38][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x38][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_TOP_DAC_APB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x38][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x38][&clk_reg_cbc]=0x189d605c v.a \a_clock_data[&dbg_mux_wcss_cc][0x38][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x38][&clk_reg_tc_sel]=0x38 v.a \a_clock_data[&dbg_mux_wcss_cc][0x38][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x38][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x38][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x38][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x39][&clk_str_name]="wcss_cc_top_ref_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x39][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x39][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_TOP_REF_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x39][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x39][&clk_reg_cbc]=0x189d6024 v.a \a_clock_data[&dbg_mux_wcss_cc][0x39][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x39][&clk_reg_tc_sel]=0x2c v.a \a_clock_data[&dbg_mux_wcss_cc][0x39][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x39][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x39][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x39][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x3a][&clk_str_name]="wcss_cc_top_slp_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3a][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3a][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_TOP_SLP_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3a][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x3a][&clk_reg_cbc]=0x189d600c v.a \a_clock_data[&dbg_mux_wcss_cc][0x3a][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x3a][&clk_reg_tc_sel]=0x2b v.a \a_clock_data[&dbg_mux_wcss_cc][0x3a][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3a][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x3a][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3a][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x3b][&clk_str_name]="wcss_cc_wcssdbg_cfg_apb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3b][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3b][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_WCSSDBG_CFG_APB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3b][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x3b][&clk_reg_cbc]=0x189d2008 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3b][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x3b][&clk_reg_tc_sel]=0x3f v.a \a_clock_data[&dbg_mux_wcss_cc][0x3b][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3b][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x3b][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3b][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x3c][&clk_str_name]="wcss_cc_wcssdbg_trc_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3c][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3c][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_WCSSDBG_TRC_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3c][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x3c][&clk_reg_cbc]=0x189d200c v.a \a_clock_data[&dbg_mux_wcss_cc][0x3c][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x3c][&clk_reg_tc_sel]=0x42 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3c][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3c][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x3c][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3c][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x3d][&clk_str_name]="wcss_cc_wmac1_apb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3d][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3d][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_WMAC1_APB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3d][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x3d][&clk_reg_cbc]=0x189d1018 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3d][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x3d][&clk_reg_tc_sel]=0x9 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3d][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3d][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x3d][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3d][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x3e][&clk_str_name]="wcss_cc_wmac1_css_mac_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3e][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3e][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_WMAC1_CSS_MAC_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3e][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x3e][&clk_reg_cbc]=0x189d3008 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3e][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x3e][&clk_reg_tc_sel]=0xb v.a \a_clock_data[&dbg_mux_wcss_cc][0x3e][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3e][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x3e][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3e][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x3f][&clk_str_name]="wcss_cc_wmac1_mac_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3f][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3f][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_WMAC1_MAC_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x3f][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x3f][&clk_reg_cbc]=0x189d300c v.a \a_clock_data[&dbg_mux_wcss_cc][0x3f][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x3f][&clk_reg_tc_sel]=0xc v.a \a_clock_data[&dbg_mux_wcss_cc][0x3f][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3f][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x3f][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x3f][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x40][&clk_str_name]="wcss_cc_wmac2_apb_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x40][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x40][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_WMAC2_APB_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x40][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x40][&clk_reg_cbc]=0x189d101c v.a \a_clock_data[&dbg_mux_wcss_cc][0x40][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x40][&clk_reg_tc_sel]=0x1a v.a \a_clock_data[&dbg_mux_wcss_cc][0x40][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x40][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x40][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x40][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x41][&clk_str_name]="wcss_cc_wmac2_css_mac_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x41][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x41][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_WMAC2_CSS_MAC_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x41][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x41][&clk_reg_cbc]=0x189d4008 v.a \a_clock_data[&dbg_mux_wcss_cc][0x41][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x41][&clk_reg_tc_sel]=0x1c v.a \a_clock_data[&dbg_mux_wcss_cc][0x41][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x41][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x41][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x41][&clk_reg_mux_input_en_mask]=0x0 v.a \a_clock_str[&dbg_mux_wcss_cc][0x42][&clk_str_name]="wcss_cc_wmac2_mac_clk" v.a \a_clock_str[&dbg_mux_wcss_cc][0x42][&clk_str_type]="cbcr" v.a \a_clock_str[&dbg_mux_wcss_cc][0x42][&clk_str_regname]="WCSS_HM_A_WCSS_CLK_CTL_WMAC2_MAC_CBCR" v.a \a_clock_str[&dbg_mux_wcss_cc][0x42][&clk_str_aliases]="" v.a \a_clock_data[&dbg_mux_wcss_cc][0x42][&clk_reg_cbc]=0x189d400c v.a \a_clock_data[&dbg_mux_wcss_cc][0x42][&clk_reg_tc_mux]=&dbg_mux_wcss_cc v.a \a_clock_data[&dbg_mux_wcss_cc][0x42][&clk_reg_tc_sel]=0x1d v.a \a_clock_data[&dbg_mux_wcss_cc][0x42][&clk_reg_total_div]=0x1 v.a \a_clock_data[&dbg_mux_wcss_cc][0x42][&clk_reg_vote_bit]=-1. v.a \a_clock_data[&dbg_mux_wcss_cc][0x42][&clk_reg_mux_input_en_addr]=0x0 v.a \a_clock_data[&dbg_mux_wcss_cc][0x42][&clk_reg_mux_input_en_mask]=0x0 ;----------------------------------------------------------------------------- ; Init testclock ;----------------------------------------------------------------------------- local &AID local &opts local &create_area_param local &success local &testclock_main_area local &invoked_by_script local &launch_cmd_line local &log_output local &log_filename local &prev_clk_grp local &input_filename local &got_input_filename local &arg local &num_unread local &prev_cmd_line local &clk_err local &help_use_same_window local &tc_mode local &reset_window &reset_window=0 &input_filename="c:\temp\testclock.txt" &log_output=0 &prev_clk_grp="" &prev_cmd_line="" ; Grab the entire launch command line. ENTRY %LINE &launch_cmd_line ; Check if testclock was invoked in '__help_same_window__' mode. &help_use_same_window=string.scan("&launch_cmd_line", "__help_same_window__", 0) if (&help_use_same_window!=-1) ( &launch_cmd_line=string.replace("&launch_cmd_line", "__help_same_window__", "", 0) ) ; Detect '__tc__' mode. &tc_mode=string.scan("&launch_cmd_line", "__tc__", 0) if (&tc_mode!=-1) ( &tc_mode=1 &launch_cmd_line=string.replace("&launch_cmd_line", "__tc__", "", 0) ) else ( &tc_mode=0 ) ; Clear any leftover help/history windows. WINCLEAR testclock_help_window WINCLEAR testclock_hist_window ; Check if testclock was invoked by another script ('super_script_area' mode). &testclock_main_area=string.ScanAndExtract("&launch_cmd_line", "super_script_area=", "TESTCLOCK") ; Create new areas. &create_area_param="2 TESTCLOCK_HELP 130. 1000. TESTCLOCK_HIST , ," if ("&testclock_main_area"=="TESTCLOCK") ( local &area_exists &area_exists=1 &invoked_by_script=0 ; ; Allow 'tc' mode to avoid clearing the area ('area.create' clears areas if ; it is given row/col dimensions for the area buffer) ; if (&tc_mode!=0) ( gosub wa_does_area_exist TESTCLOCK entry &area_exists ) if ((&tc_mode==0)||(&area_exists==0)) ( &create_area_param="3 TESTCLOCK 180. 1000. TESTCLOCK_HELP 130. 1000. TESTCLOCK_HIST , ," ) ) else ( &invoked_by_script=1 ; cut the 'super_script_area' argument out of the launch command line. &launch_cmd_line=string.replace("&launch_cmd_line", "super_script_area=&testclock_main_area", "", 0) ) gosub wa_area_create_list &create_area_param entry &success if (&success==0) ( area.select print %ERROR "ERROR: Failed to create areas for testclock.cmm." enddo ) ; Create a new window if needed. if (WIN.EXIST("testclock_main_window")==FALSE()) ( local &x_start local &y_start local &x_len local &y_len ; Check if there are previously saved window settings. gosub wa_find_saved_window_settings testclock_main_window entry &x_start &y_start &x_len &y_len if (&x_start!=-1) ( ; Use the previous window settings. winpos &x_start &y_start &x_len &y_len 0. 0. testclock_main_window ) else ( gosub Default_WINPOS_Main ) ) area.view &testclock_main_area area.select &testclock_main_area ; Initialize the argument bufferer with the launch command line. gosub args_main create_client clk_drv &testclock_main_area &launch_cmd_line entry &AID if ("&AID"=="ARGS_ERR") ( gosub args_main get_error entry &clk_err print %ERROR "ERROR: Failed to create an ARGS client:" print %ERROR " '&clk_err'." enddo ) ; Set bufferer options. &opts="print_errors=1 help_cmd=? help_sub=Display_Help" &opts="&opts hist_cmd=hist hist_sub=Display_Hist" gosub args_main set_opts &AID &opts entry &clk_err if ("&clk_err"=="ARGS_ERR") ( gosub args_main get_error entry &clk_err print %ERROR "ERROR: Failed to set ARGS options:" print %ERROR " '&clk_err'." enddo ) ; Set generic testclock error handler. ON ERROR gosub ( print %ERROR ERROR.ADDRESS() print %ERROR "ERROR: Testclock error occurred:" print %ERROR " Last command='&arg'. Last clock group='&clk'." return ) ; Print banner before entering main loop. print "" print "[-------------------- [&chipset_name] TEST CLOCK TOOL --------------------]" print "" ;----------------------------------------------------------------------------- ; Argument handler main loop ;----------------------------------------------------------------------------- Main_Loop: ( &clk_err="" ; ; Reset testclock argument handler state. ; &repeat_prev_cmd=0 &header_printed=0 &state_change="" &got_input_filename=0 ; ; Get next command header arg. ; gosub args_main get_num_unread &AID entry &num_unread if (&num_unread==0) ( local &line gosub args_main get_cmd_line &AID entry %LINE &line if (("&line"!=".")&&("&line"!="")) ( &prev_cmd_line="&line" ) ; If the history window is open, go ahead and update it. if (WIN.EXIST("testclock_hist_window")==TRUE()) ( gosub Display_Hist SKIP_VIEW ) print "" print "[testclock.cmm] Version: <&gendate>" ) gosub args_main get_arg &AID Enter command ('?' for help) > entry &arg gosub wa_save_window_settings testclock_hist_window gosub wa_save_window_settings testclock_main_window ; ; Pre-process the command header arg. ; if (("&arg"==".")||("&arg"=="")) ( if ("&prev_cmd_line"=="") ( print %ERROR "No previous command to repeat." goto Main_Loop ) ; Prepare to repeat the previous command line. gosub args_main reset_cmd_line &AID &prev_cmd_line gosub args_main get_arg &AID entry &arg &repeat_prev_cmd=1 ) if (("&arg"=="on")||("&arg"=="off")) ( ; Set state change command. &state_change="&arg" ; Check if a new clock selection is specified. gosub args_main get_num_unread &AID entry &num_unread if (&num_unread==0) ( ; Use previous clock selection for state change operation. if ("&prev_clk_grp"=="") ( print %ERROR "Command '&arg' failed. No clock(s) were previously selected." goto Main_Loop ) &arg="&prev_clk_grp" ) else ( ; Extract new clock selection from buffered command line. gosub args_main get_arg &AID entry &arg ) if ("&arg"=="file") ( ; Check if a new clock file input is specified. gosub args_main get_num_unread &AID entry &num_unread if (&num_unread!=0) ( ; Extract new clock file input from buffered command line. gosub args_main get_arg &AID entry &input_filename ) ; Record that the file name is already known. &got_input_filename=1 ) ) ; ; Execute the command operation. ; if ("&arg"=="x") ( goto Exit_Testclock ) else if ("&arg"=="wr") ( &reset_window=1 ; Reset the window size/position to default settings. winclear testclock_help_window winclear testclock_hist_window winclear testclock_main_window gosub Default_WINPOS_Main area.view &testclock_main_area ) else if ("&arg"=="gpio") ( gosub Configure_GPIO ) else if ("&arg"=="log") ( ; Check if output is already being logged. if (&log_output==0) ( ; Output not currently logged--prompt user for new log file name local &filename gosub args_main get_arg &AID Enter log output file (default 'c:\temp\testclock_out.log') > entry &filename if ("&filename"=="close") ( print %ERROR "No open output log to close." ) else ( if ("&filename"=="") ( &log_filename="c:\temp\testclock_out.log" ) else ( &log_filename="&filename" ) print "Logging testclock output to '&log_filename'." ; Open the output log file. ( ON ERROR gosub ( print %ERROR "ERROR: Failed to open clock output log '&log_filename'." &clk_err="failed_to_open_log_out" return ) AREA.open &testclock_main_area &log_filename ) if ("&clk_err"!="failed_to_open_log_out") ( &log_output=1 ) ) ) else ( local &log_arg gosub args_main get_arg &AID Stop logging output and close '&log_filename'? [close|n] > entry &log_arg if ("&log_arg"=="close") ( AREA.close &testclock_main_area &log_output=0 print "Closed '&log_filename' and stopped logging output." ) else ( print "Did not close the open output log '&log_filename'." ) ) ) else if ("&arg"=="file") ( local &input_line ; Get the input filename if necessary. if (&got_input_filename==0) ( local &prompt_filename gosub args_main get_arg &AID Enter input file (default 'c:\temp\testclock.txt') > entry &prompt_filename if ("&prompt_filename"!="") ( &input_filename="&prompt_filename" ) ) ; Open the clock input file ( ON ERROR gosub ( print %ERROR "ERROR: Failed to open clock list file '&input_filename'." &clk_err="failed_to_open_file_in" return ) OPEN #1 &input_filename /Read ) if ("&clk_err"!="failed_to_open_file_in") ( print "Operating on list of clocks from '&input_filename'." READ #1 %line &input_line WHILE !EOF() ( &input_line=string.trim("&input_line") if (STRING.SCAN("&input_line", "print", 0)==0) ( &input_line=string.cut("&input_line", 6) print "&input_line" ) else if ("&input_line"!="") ( gosub Find_Print_Clock &input_line ) READ #1 %line &input_line ) CLOSE #1 ) &prev_clk_grp="&arg" ) else if (("&arg"=="all")||("&arg"=="all_on")||("&arg"=="all_off")) ( &clk_state_filter="&arg" gosub Print_All &prev_clk_grp="&arg" ) else ( ; Assume argument is a clock group local &printed_ss_clock_info gosub Print_All_SS &arg entry &printed_ss_clock_info if (&printed_ss_clock_info==0) ( ; Didn't match a SS clock group--attempt to operate on non-SS clock group gosub Find_Print_Clock &arg ) &prev_clk_grp="&arg" ) goto Main_Loop ) ; ; Sets up the default window position/size for the main window. ; Default_WINPOS_Main: ( winpos 0. 0. 150. 100% 0. 0. testclock_main_window return ) ; ; Sets up the default window position/size for the history window. ; Default_WINPOS_Hist: ( winpos 155. 0. 50. 50% 0. 0. testclock_hist_window return ) ;----------------------------------------------------------------------------- ; Exit testclock ;----------------------------------------------------------------------------- Exit_Testclock: ( winclear testclock_help_window if ((&tc_mode==0)||(&reset_window!=0)) ; skip saving a second time for 'tc' mode. ( gosub wa_save_window_settings testclock_hist_window gosub wa_save_window_settings testclock_main_window ) ; Close the output log if needed. if (&log_output!=0) ( area.close &testclock_main_area ) winclear testclock_hist_window if (&tc_mode==0) ( winclear testclock_main_window ) area.select ; select default area print "Exited [&chipset_name] 'testclock.cmm'." enddo ) ;----------------------------------------------------------------------------- ; Display history ;----------------------------------------------------------------------------- Display_Hist: ( local &skip_view entry &skip_view ; Display the help area if required. if ("&skip_view"=="") ( if (WIN.EXIST("testclock_hist_window")==FALSE()) ( local &x_start local &y_start local &x_len local &y_len ; Check if there are previously saved window settings. gosub wa_find_saved_window_settings testclock_hist_window entry &x_start &y_start &x_len &y_len if (&x_start!=-1) ( ; Use the previous window settings. winpos &x_start &y_start &x_len &y_len 0. 0. testclock_hist_window ) else ( gosub Default_WINPOS_Hist ) ) area.view TESTCLOCK_HIST wintop testclock_hist_window ) area.clear TESTCLOCK_HIST area.select TESTCLOCK_HIST ; Print the history entries. print "" print "[--- [&chipset_name] testclock.cmm history: ---]" print "" gosub args_main print_hist &AID ; Switch back to the main demo window. area.select &testclock_main_area return ) ;----------------------------------------------------------------------------- ; Display help ;----------------------------------------------------------------------------- Display_Help: ( ;----------------------------------------------------------------------------- ; Display available clock sources that can be output to the clock test output ; and prompt for selection. ;----------------------------------------------------------------------------- ; If the history window is open, go ahead and update it. if (WIN.EXIST("testclock_hist_window")==TRUE()) ( gosub Display_Hist SKIP_VIEW ) if (&help_use_same_window==-1) ( if (WIN.EXIST("testclock_help_window")==FALSE()) ( WINPOS , , , , , , testclock_help_window ) area.view TESTCLOCK_HELP area.clear TESTCLOCK_HELP area.select TESTCLOCK_HELP winresize 130. 28. ) print "" print "" gosub Print_Clock_Help print "" print "" print "*** Commands ***" print "" print " - Print the status of a single clock or clock group." print " on/off [clks] - Modifies on/off state of clock(s). If a new clock group" print " isn't given, the previously selected clock group is used." print " gpio - Enable GPIO's for clock output." print " log - Begin/end logging output to a file (closes upon 'x' exit)." print " x [.] - Exit [and leave the main window displayed]." print " ? - Display help message." print " . - Repeat previous command. Entering an empty line will also" print " repeat the previous command." print " hist - Display a testclock history window." print " wr - Reset the script window size/position." print "" print "*** Clock Groups ***" print "" print " all - All clocks." print " all_on - All clocks that are on." print " all_off - All clocks that are off." print " _all - All subsystem clocks." print " - Search query." print " buses - All bus clocks." print " cpus - All cpu clocks." print " file - File specifying enumerated clocks (separated by newlines)." print " If a file name is not given, the previous input file is" print " used (default 'c:\temp\testclock.txt')." print "" area.select &testclock_main_area return ) ;----------------------------------------------------------------------------- ; Display help ;----------------------------------------------------------------------------- Help: ;----------------------------------------------------------------------------- ; Display available clock sources that can be output to the clock test output ; and prompt for selection. ;----------------------------------------------------------------------------- AREA.Create HELP 130. 1000. AREA.View HELP AREA.Select HELP winresize 130. 24. print " " print " " gosub Print_Clock_Help print "" print "*** Clock groups*** " print " all - all clocks" print " all_on - all clocks that are on" print " _all - all subsystem clocks" print " - search query" print " file - file specifying enumerated clocks (separated by newlines)" print " on/off - modifies on/off state of previously selected clock(s)" print " buses - show all bus clocks" print " cpus - show all cpu clocks" print "*** Other options ***" print " x - exit" print " ? - help" print " . - repeat (also carriage return without any arguments)" print "*** Debug options ***" print " gpio - enable GPIO's for clock output" print "" AREA.Select CLOCK return ;----------------------------------------------------------------------------- ; Determine clock frequency. ;----------------------------------------------------------------------------- Calc_Clock_Freq: local &l2cpucpselr_val local &l2cpucpcpdr_val ; Save current values &xo_div4_cbcr=data.long(&access_mode:&xo_div4_cbcr_addr) ; Measure a short run &tcxo_count=0x800 ; Config XO DIV4 comparator clock data.set &access_mode:&xo_div4_cbcr_addr %LONG data.long(&access_mode:&xo_div4_cbcr_addr)|0x1 ; Start with the counter disabled &measure_ctl=data.long(&access_mode:&frq_measure_ctl_addr) &measure_ctl=&measure_ctl&~0x1FFFFF data.set &access_mode:&frq_measure_ctl_addr %LONG &measure_ctl ; Program the starting counter value, high enough to get good accuracy &measure_ctl=&measure_ctl|&tcxo_count ; Start the counting &measure_ctl=&measure_ctl|0x100000 data.set &access_mode:&frq_measure_ctl_addr %LONG &measure_ctl ; Wait for the counters to finish wait 1.ms while (data.long(&access_mode:&frq_measure_status_addr)&0x2000000)==0 ( ) ; Turn off the test clock and read the clock count &measure_ctl=data.long(&access_mode:&frq_measure_ctl_addr) data.set &access_mode:&frq_measure_ctl_addr %LONG (&measure_ctl&~0x100000) &short_clock_count=data.long(&access_mode:&frq_measure_status_addr)&0x1FFFFFF ; Restore the registers data.set &access_mode:&xo_div4_cbcr_addr %LONG &xo_div4_cbcr ; Now do a longer count and compare ; Save current values &xo_div4_cbcr=data.long(&access_mode:&xo_div4_cbcr_addr) &tcxo_count=0x8000 ; Config XO DIV4 comparator clock data.set &access_mode:&xo_div4_cbcr_addr %LONG data.long(&access_mode:&xo_div4_cbcr_addr)|0x1 ; Start with the counter disabled &measure_ctl=data.long(&access_mode:&frq_measure_ctl_addr) &measure_ctl=&measure_ctl&~0x1FFFFF data.set &access_mode:&frq_measure_ctl_addr %LONG &measure_ctl ; Program the starting counter value, high enough to get good accuracy &measure_ctl=&measure_ctl|&tcxo_count ; Start the counting &measure_ctl=&measure_ctl|0x100000 data.set &access_mode:&frq_measure_ctl_addr %LONG &measure_ctl ; Wait for the counters to finish wait 1.ms while (data.long(&access_mode:&frq_measure_status_addr)&0x2000000)==0 ( ) ; Turn off the test clock and read the clock count &measure_ctl=data.long(&access_mode:&frq_measure_ctl_addr) data.set &access_mode:&frq_measure_ctl_addr %LONG (&measure_ctl&~0x100000) &clock_count=data.long(&access_mode:&frq_measure_status_addr)&0x1FFFFFF ; Calculate the frequency. Function is provided by ; Power Control 42.8.1.2 Measurement technique ; f ring = f tcxo/4 * (Nring + 1.5) / (TCtcxo + 3.5) ; ; The formula below is the equivalent one converted ; to integer arithmetic. ; ; We add half of the denominator value to the dividend ; to guard against rounding errors inherent to ; integer arithmetic. ; if &clock_count==&short_clock_count ( &clk_freq=0 ) else ( &clk_freq=4.8*(&clock_count+1.5)/(&tcxo_count+3.5) ) ; Restore the registers data.set &access_mode:&xo_div4_cbcr_addr %LONG &xo_div4_cbcr return ;----------------------------------------------------------------------------- ; Display clock info header ;----------------------------------------------------------------------------- Print_Header: if &header_printed==0 ( print "" print "Clock State Frequency (MHz) Debug Mux CBCR Addr Value CBCR Type Aliases " print "------------------------------------------------------------------------------------------------------------------------------------------------------" &header_printed=1 ) return ;----------------------------------------------------------------------------- ; Display clock info line ;----------------------------------------------------------------------------- Print_Clk_Info_Line: local &is_on &clk_freq &clk_reg_val &on_reg &on_mask &clk_access_mode &clk_access_mode=var.string(\a_dbg_mux_str[&clk_test_mux][&dbg_mux_str_access_mode]) ;----------------------------------------------------------------------------- ; Toggle clock state if requested ;----------------------------------------------------------------------------- if (&clk_reg!=0) ( if &clk_vote_bit!=-1. ( &vote_idx=&clk_vote_bit/32. &on_reg=v.value(\vote_regs[&vote_idx]) &on_mask=(1<<(&clk_vote_bit-(32.*&vote_idx))) ) else ( &on_reg="&clk_reg" &on_mask=0x1 ) if "&state_change"=="on" ( data.set &clk_access_mode:&on_reg %LONG (data.long(&clk_access_mode:&on_reg)|&on_mask) ) else if "&state_change"=="off" ( data.set &clk_access_mode:&on_reg %LONG (data.long(&clk_access_mode:&on_reg)&~(&on_mask)) ) ) ;----------------------------------------------------------------------------- ; Print the clock header ;----------------------------------------------------------------------------- gosub Print_Header ;----------------------------------------------------------------------------- ; Test if clock is on ;----------------------------------------------------------------------------- if (&clk_reg!=0) ( if (data.long(&clk_access_mode:&clk_reg)&(0x80000000))==0x0 ( &clk_state="ON " &is_on=1 ) else ( &clk_state="OFF" &is_on=0 ) ) else ( &clk_state=" ? " &is_on=-1 ) ; Always program the muxes, even if the clock is off and we're not ; going to actually calculate the frequency, since the mux configuration ; is still required for routing out to the test pad. gosub Program_Clk_Test ;----------------------------------------------------------------------------- ; Calculate the clock frequency based on the TCXO counter ;----------------------------------------------------------------------------- if ((&is_on==1)||(&is_on==-1)) ( ; Set dividers before calculation to ensure clock is within range of ; the frequency counter. Clear dividers after calculation so they ; don't affect frequency when probing with a scope. ;gosub Set_Dividers gosub Calc_Clock_Freq ;gosub Clear_Dividers if (&clk_freq==0) ( &clk_freq_str=FORMAT.FLOAT(12., 0x6, 0.0) ) else ( &clk_freq=&clk_freq*&clk_multiplier &clk_freq_str=FORMAT.FLOAT(12., 0x6, &clk_freq) ) if (&is_on==-1) ( if (&clk_freq==0) ( &is_on=0 ) else ( &is_on=1 ) ) ) else if (&is_on==0) ( &clk_freq_str=FORMAT.FLOAT(12., 0x6, 0.0) ) else ( &clk_freq_str=" Not Testable" ) if ((("&clk_state_filter"=="all_on")&&(&is_on==0))||(("&clk_state_filter"=="all_off")&&(&is_on==1))) ( return ) if (&clk_reg!=0) ( &clk_reg_val=FORMAT.HEX(0x8, data.long(&clk_access_mode:&clk_reg)) &clk_reg_val_str="0x&clk_reg_val" &clk_reg=FORMAT.HEX(0x8, &clk_reg) &clk_reg_str="0x&clk_reg" ) else ( &clk_reg_str="----------" &clk_reg_val_str="----------" ) ; Format clock name width &padding=STRING.CUT(" ", STRING.LEN("&clk_name")) &padding2=STRING.CUT(" ", STRING.LEN("&clk_state")) &padding3=STRING.CUT(" ", STRING.LEN("&clk_freq_str")) &printmux=var.string(\a_dbg_mux_str[&clk_test_mux][&dbg_mux_str_name]) &padding4=STRING.CUT(" ", STRING.LEN("&printmux")) &padding5=STRING.CUT(" ", STRING.LEN("&clk_reg_str")) &padding6=STRING.CUT(" ", STRING.LEN("&clk_reg_val_str")) &padding7=STRING.CUT(" ", STRING.LEN("&clk_reg_cbcr_type")) &padding8=STRING.CUT(" ", STRING.LEN("&clk_alias")) print "&clk_name&padding&clk_state&padding2&clk_freq_str&padding3&printmux&padding4&clk_reg_str&padding5:&clk_reg_val_str&padding6&clk_reg_cbcr_type&padding7&clk_alias&padding8" return ;----------------------------------------------------------------------------- ; Program the Parent Clock Mux ;----------------------------------------------------------------------------- Program_Parent_Mux: ENTRY &ppm_parent_idx &ppm_parent_sel &ie_addr &ie_mask LOCAL &mux_access_mode &mux_input_en_addr &mux_input_en_mask &mux_access_mode=var.string(\a_dbg_mux_str[&ppm_parent_idx][&dbg_mux_str_access_mode]) ; Set Mux Select &clock_ctl_reg=v.value(\a_dbg_mux_data[&ppm_parent_idx][&dbg_mux_reg_addr]) &clock_ctl_mask=v.value(\a_dbg_mux_data[&ppm_parent_idx][&dbg_mux_reg_mask]) &clock_ctl_shft=v.value(\a_dbg_mux_data[&ppm_parent_idx][&dbg_mux_reg_shft]) &clock_ctl_val=data.long(&mux_access_mode:&clock_ctl_reg) &clock_ctl_val=&clock_ctl_val&~(&clock_ctl_mask<<&clock_ctl_shft) data.set &mux_access_mode:&clock_ctl_reg %LONG &clock_ctl_val&~&clock_ctl_mask|((&ppm_parent_sel<<&clock_ctl_shft)&&clock_ctl_mask) ; Set Mux Divider &clock_div_reg=v.value(\a_dbg_mux_data[&ppm_parent_idx][&dbg_mux_reg_div_addr]) if &clock_div_reg!=0x0 ( &clock_div_mask=v.value(\a_dbg_mux_data[&ppm_parent_idx][&dbg_mux_reg_div_mask]) &clock_div_shft=v.value(\a_dbg_mux_data[&ppm_parent_idx][&dbg_mux_reg_div_shft]) &clock_div_hw_val=v.value(\a_dbg_mux_data[&ppm_parent_idx][&dbg_mux_reg_div_hw_val]) &clock_div_val=data.long(&mux_access_mode:&clock_div_reg) &clock_div_val=&clock_div_val&~(&clock_div_mask<<&clock_div_shft) data.set &mux_access_mode:&clock_div_reg %LONG &clock_div_val&~&clock_div_mask|((&clock_div_hw_val<<&clock_div_shft)&&clock_div_mask) ) &clock_en_reg=v.value(\a_dbg_mux_data[&ppm_parent_idx][&dbg_mux_reg_enable_addr]) &clock_en_enable_mask=v.value(\a_dbg_mux_data[&ppm_parent_idx][&dbg_mux_reg_enable_mask]) if &clock_en_reg!=0x0 ( &clock_en_val=data.long(&mux_access_mode:&clock_en_reg)|&clock_en_enable_mask data.set &mux_access_mode:&clock_en_reg %LONG &clock_en_val ) if &ie_addr!=0x0 ( &ie_val=data.long(&mux_access_mode:&ie_addr)|&ie_mask data.set &mux_access_mode:&ie_addr %LONG &ie_val ) &pidx=v.value(\a_dbg_mux_data[&ppm_parent_idx][&dbg_mux_reg_parent_idx]) &psel=v.value(\a_dbg_mux_data[&ppm_parent_idx][&dbg_mux_reg_parent_sel]) if &pidx!=&dbg_mux_none ( GOSUB Program_Parent_Mux &pidx &psel 0x0 0x0 ) return ;----------------------------------------------------------------------------- ; Program the clk_test register ;----------------------------------------------------------------------------- Program_Clk_Test: &testval=&clk_test_sel &dbg_mux=&clk_test_mux if (&dbg_mux==&dbg_mux_none) ( return ) GOSUB Program_Parent_Mux &dbg_mux &testval &mux_input_enable_addr &mux_input_enable_mask ; Frequency counter utility registers. &frq_measure_ctl_addr=v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_measure_ctl]) &frq_measure_status_addr=v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_measure_status]) &xo_div4_cbcr_addr=v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_xo_div4_addr]) return Configure_GPIO: &val=data.long(&access_mode:v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_plltestpad]))|0xA0000 data.set &access_mode:v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_plltestpad]) %LONG &val print "PLLTEST_PAD enabled in GCC_PLLTEST_PAD_CFG." return Set_Dividers: ®=v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_addr]) &shift=v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_shft]) &mask=v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_mask]) &divval=v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_hw_val]) &val=(data.long(&access_mode:®)&~&mask)|((&divval<<&shift)&mask) data.set &access_mode:® %LONG &val return Clear_Dividers: ®=v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_addr]) &shift=v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_shft]) &mask=v.value(\a_dbg_mux_data[&dbg_mux_gcc][&dbg_mux_reg_div_mask]) &val=(data.long(&access_mode:®)&~&mask) data.set &access_mode:® %LONG &val return Print_Clock_Help: &ch_ctlrs=0 while (&ch_ctlrs<&dbg_mux_max) ( &ch_clk=0 &clkctlr_name=v.string(\a_dbg_mux_str[&ch_ctlrs][&dbg_mux_str_name]) &printline="" print "" print "***************************************************** &clkctlr_name ******************************************************" while (&ch_clk0) ( &alias_num=string.scan("&clk_alias_in",",",0)+1 if (&alias_num==0) ( if (STRING.SCAN("&clk_alias_in", STRING.MID("&clk_in", 1, &clk_input_length-2), 0)!=-1) ( &match=1 ) ) else ( while (&alias_num>0) ( &alias_clk=string.split("&clk_alias_in",",",&alias_num) if (STRING.SCAN("&alias_clk", STRING.MID("&clk_in", 1, &clk_input_length-2), 0)!=-1) ( &match=1 &alias_num=1 ) &alias_num=&alias_num-1 ) ) ) ) else if (&wild_head==1) ( if (STRING.MID("&clk_ref", &clk_itr_length-&clk_input_length+1, &clk_input_length-1)==STRING.CUT("&clk_in", 1)) ( &match=1 ) else if (&clk_alias_length>0) ( &alias_num=string.scan("&clk_alias_in",",",0)+1 if (&alias_num==0) ( if (STRING.MID("&clk_alias_in", &clk_alias_length-&clk_input_length+1, &clk_input_length-1)==STRING.CUT("&clk_in", 1)) ( &match=1 ) ) else ( while (&alias_num>0) ( &alias_clk=string.split("&clk_alias_in",",",&alias_num) if (STRING.MID("&alias_clk", &clk_alias_length-&clk_input_length+1, &clk_input_length-1)==STRING.CUT("&clk_in", 1)) ( &match=1 &alias_num=1 ) &alias_num=&alias_num-1 ) ) ) ) else if (&wild_tail==1) ( if (STRING.MID("&clk_ref", 0, &clk_input_length-1)==STRING.CUT("&clk_in", -1)) ( &match=1 ) else if (string.length("&clk_alias_in")>0) ( &alias_num=string.scan("&clk_alias_in",",",0)+1 if (&alias_num==0) ( if (STRING.MID("&clk_alias_in", 0, &clk_input_length-1)==STRING.CUT("&clk_in", -1)) ( &match=1 ) ) else ( while (&alias_num>0) ( &alias_clk=string.split("&clk_alias_in",",",&alias_num) if (STRING.MID("&alias_clk", 0, &clk_input_length-1)==STRING.CUT("&clk_in", -1)) ( &match=1 &alias_num=1 ) &alias_num=&alias_num-1 ) ) ) ) else if ("&clk_ref"=="&clk_in") ( &match=1 ) else if ((&wild_head!=1)&&(&wild_tail!=1)) ( if (string.length("&clk_alias_in")>0) ( &alias_num=string.scan("&clk_alias_in",",",0)+1 if (&alias_num==0) ( if ("&clk_alias_in"=="&clk_in") ( &match=1 ) ) else ( while (&alias_num>0) ( &alias_clk=string.split("&clk_alias_in",",",&alias_num) if ("&alias_clk"=="&clk_in") ( &match=1 &alias_num=1 ) &alias_num=&alias_num-1 ) ) ) ) if (&match==1) ( &clk_test_mux=&testclkmux &clk_test_sel=&testclksel &clk_reg=&clk_reg_in &clk_reg_name="&clk_reg_name_in" &clk_name="&clk_ref" &clk_reg_cbcr_type="&clk_reg_cbcr_type_in" &clk_vote_bit=&clk_vote_bit_in &clk_multiplier=&clk_multiplier_in gosub Print_Clk_Info_Line ) return ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; Utility Subroutines ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; Lauterbach T32 "Window/Area" Utility Subs: ; ; bool wa_does_area_exist ( string area ) ; ; bool wa_try_area_create ( string area, [int cols, int rows] ) ; ; bool wa_area_create_list ( ; int num, [string area, int cols, int rows], ... ) ; ; string wa_get_substr_ws ( string src_str, int read_idx ) ; ; int[4] wa_extract_stored_win_dim ( string file_name, string window_name ) ; ; bool wa_save_window_settings ( string window_name, [flag print_error] ) ; ; int[4] wa_find_saved_window_settings ( string window_name ) ; ; bool wa_delete_saved_window_settings ( ; string window_name, [flag print_error] ) ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; bool wa_does_area_exist ( string area ) ; ; Returns non-zero if the given area currently exists. ; ; SIDE EFFECTS: Selects the tested area if it exists, or the default area. ; wa_does_area_exist: ( local &area_name entry &area_name ON ERROR gosub ( ; Clear the error message. area.select print "" &clk_err="!" return ) &clk_err="" area.select &area_name if ("&clk_err"=="") ( return 1 ) else ( return 0 ) ) ; ; bool wa_try_area_create ( string area, [int cols, int rows] ) ; ; Attempts to create an area (see 'area.create'). Returns non-zero if the ; area is successfully created. If the 'area.create' operation fails, the ; caller may run 'area.reset' then re-try creating the area. The 'rows' and ; 'cols' arguments can be bypassed by omitting both. ; ; T32 has a maximum number of concurrent areas (only 10 at the time of ; writing this sub). Unfortunately these areas can only be deleted in bulk ; with the highly destructive 'area.reset' (although some T32 documentation ; incorrectly states that 'area.close ' destroys the area, it ; doesn't--it only closes the area's output logging). ; ; Furthermore, areas aren't destroyed automatically upon script exit, so ; if a user were to run multiple scripts with multiple areas they could ; quickly exhaust the 10-area limit and then find that subsequent script ; launches always fail, potentially with confusing error messages. This ; utility sub is intended to mitigate this risk without having to immidiately ; resort to running a global 'area.reset' during script initialization. ; wa_try_area_create: ( local &area_name local &cols local &rows entry &area_name &cols &rows ON ERROR gosub ( &clk_err="!" return ) &clk_err="" area.create &area_name &cols &rows if ("&clk_err"=="") ( return 1 ) else ( return 0 ) ) ; ; bool wa_area_create_list ( int num, [string area, int cols, int rows], ... ) ; ; Attempts to create a list of areas. Will run the global 'area.reset' command ; upon the first failure, and return 0 upon the second failure. Otherwise ; returns non-zero upon success. ; wa_area_create_list: ( local &success local &already_failed local &area_name local &cols local &rows local &area_idx local &num local &input_line local &line_idx local &area_list_line_idx entry %LINE &input_line ; Get the number of areas to create. gosub wa_get_substr_ws "&input_line" 0. entry &num &area_list_line_idx if ("&num"=="") ( print %ERROR "ERROR: wa_area_create_list() detected invalid input: '&input_line'." return 0 ) &already_failed=0 wa_area_create_list_process_areas: ; Create each area. &area_idx=0 &line_idx=&area_list_line_idx while (&area_idx<&num) ( ; Read in the area information. gosub wa_get_substr_ws "&input_line" &line_idx entry &area_name &line_idx if ("&area_name"=="") ( goto wa_area_create_list_too_few_args ) gosub wa_get_substr_ws "&input_line" &line_idx entry &cols &line_idx if ("&cols"=="") ( goto wa_area_create_list_too_few_args ) gosub wa_get_substr_ws "&input_line" &line_idx entry &rows &line_idx if ("&rows"=="") ( goto wa_area_create_list_too_few_args ) ; Check if the row/col argument was bypassed. if (("&cols"==",")||("&rows"==",")) ( ; Apply a sanity check for row/col bypass. if (("&cols"!=",")||("&rows"!=",")) ( print %ERROR "ERROR: wa_area_create_list() detected invalid row/col settings for '&area_name'." print %ERROR " Row/col must both be an integer or both be ',' (got row='&row', col='&col'). " return 0 ) &cols="" &rows="" ) ; Attempt to create the area. gosub wa_try_area_create &area_name &cols &rows entry &success if (&success==0) ( ; Already failed => infinite impending failures. if (&already_failed!=0) ( print %ERROR %Decimal "ERROR: wa_area_create_list() failed to create &num areas." return 0 ) ; Delete all areas and try creating the area list once more. &already_failed=1 area.reset winclear goto wa_area_create_list_process_areas ) &area_idx=&area_idx+1 ) return 1 wa_area_create_list_too_few_args: print %ERROR "ERROR: wa_area_create_list() detected too few arguments (num_areas='&num')." return 0 ) ; ; string wa_get_substr_ws ( string src_str, int read_idx ) ; ; Returns the next sub-string word from a source string, or nothing if there ; is no such word. The words are split by spaces. ; ; Example: ; Returns "bc 5" (sans quotes). ; wa_get_substr_ws: ( local &src_str local &src_len local &read_idx local &sub_str local &start_idx entry &src_str &read_idx if (&read_idx<0) ( ; Negative read index--return empty string (and no index). return ) &src_len=string.length(&src_str) ; Find the start of non-whitespace segment. while (&read_idx<&src_len) ( if (string.char(&src_str, &read_idx)!=' ') ( &start_idx=&read_idx goto wa_get_substr_ws_find_end_idx ) &read_idx=&read_idx+1 ) ; No non-whitespace found--return empty string (and no index). return wa_get_substr_ws_find_end_idx: ; Find the end of non-whitespace segment. &read_idx=&read_idx+1 while (&read_idx<&src_len) ( if (string.char(&src_str, &read_idx)==' ') ( ; Cut out leading and trailing whitespace &sub_str=string.mid(&src_str, &start_idx, &read_idx-&start_idx) goto wa_get_substr_ws_return_substr ) &read_idx=&read_idx+1 ) ; No trailing white-space found--cut out any leading whitespace. &sub_str=string.cut(&src_str, &start_idx) wa_get_substr_ws_return_substr: return &sub_str &read_idx ) ; ; int[2] wa_extract_stored_win_dim ( string file_name, string window_name ) ; ; Returns the settings for the given window extracted from a previously ; stored file. Returns -1 if the window settings aren't found. ; ; Returns: {x_start, y_start, x_length, y_length} ; (all values are in row or column units). ; wa_extract_stored_win_dim: ( local &window_name local &file_name local &x_start local &y_start local &x_len local &y_len local &line_in local &idx entry &file_name &window_name &x_start=-1 &y_start=-1 &y_len=-1 &x_start=-1 ; Open the input file. ( &clk_err="" ON ERROR gosub ( print %ERROR "ERROR: wa_extract_stored_win_dim() failed to open '&file_name'." &clk_err="!" return ) OPEN #1 &file_name /Read ) if ("&clk_err"!="") ( goto wa_extract_stored_win_dim_error ) ; Scan the input file for "winpos ... window_name". WHILE TRUE() ( READ #1 %line &line_in if (EOF()==TRUE()) ( goto wa_extract_stored_win_dim_error ) &line_in=string.lower("&line_in") ; Search for 'winpos' line header and cut it out if found. &idx=string.scan("&line_in", "winpos", 0) if (&idx!=-1) ( &line_in=string.cut("&line_in", &idx+6.) ; Search for the specified window name. if (string.scan("&line_in", "&window_name", 0)!=-1) ( ; Extract the specified window's settings. gosub wa_get_substr_ws "&line_in" 0. entry &x_start &idx if ("&x_start"=="") ( goto wa_extract_stored_win_dim_error ) gosub wa_get_substr_ws "&line_in" &idx entry &y_start &idx if ("&y_start"=="") ( goto wa_extract_stored_win_dim_error ) gosub wa_get_substr_ws "&line_in" &idx entry &x_len &idx if ("&x_len"=="") ( goto wa_extract_stored_win_dim_error ) gosub wa_get_substr_ws "&line_in" &idx entry &y_len &idx if ("&y_len"=="") ( goto wa_extract_stored_win_dim_error ) CLOSE #1 return &x_start &y_start &x_len &y_len ) ) ) wa_extract_stored_win_dim_error: CLOSE #1 return -1 -1 -1 -1 ) ; ; bool wa_save_window_settings ( string window_name, [flag print_error] ) ; ; Saves a script's window configuration (position + size). ; See restore_window_settings() for the restore operation. ; Returns non-zero if the store operation succeeded. ; ; This is provided as a method to allow scripts to save/restore their window ; settings accross multiple script sessions. T32's "store win" tool ; is insufficient to do this since it will only save/restore *all* T32 windows, ; not targeted windows. ; wa_save_window_settings: ( local &file local &window_name local &script_name local &print_error &clk_err="" ON ERROR gosub ( &clk_err="!" return ) entry &window_name &print_error ; Store the full window configuration in a file under the temporary directory. &script_name=os.ppf() &script_name=os.file.name("&script_name") &file=os.ptd() &file="&(file)\__&(script_name)_&(window_name)_dim.cmm" store &file win if ("&clk_err"=="") ( return 1 ) else ( if ("&print_error"!="") ( print %ERROR "ERROR: wa_save_window_settings() failed to store settings for '&window_name'." ) return 0 ) ) ; ; int[4] wa_find_saved_window_settings ( string window_name ) ; ; Returns the settings for the given window extracted from a previously ; save. Returns -1 if the window settings aren't found. ; ; Returns: {x_start, y_start, x_length, y_length} ; (all values are in row or column units). ; ; This is provided as a method to allow scripts to save/restore their window ; settings accross multiple script sessions. T32's "store win" tool ; is insufficient to do this since it will only save/restore *all* T32 windows, ; not targeted windows. ; wa_find_saved_window_settings: ( local &x_start local &y_start local &x_len local &y_len local &window_name local &file local &script_name entry &window_name ; Check if the window's saved settings file exists. &script_name=os.ppf() &script_name=os.file.name("&script_name") &file=os.ptd() &file="&(file)\__&(script_name)_&(window_name)_dim.cmm" if (os.file.access("&file", "R")==FALSE()) ( return -1 -1 -1 -1 ) ; Search for previously saved settings for this window. gosub wa_extract_stored_win_dim &file &window_name entry &x_start &y_start &x_len &y_len return &x_start &y_start &x_len &y_len ) ; ; bool wa_delete_saved_window_settings ( string window_name, [flag print_error] ) ; ; Deletes a window settings file. ; wa_delete_saved_window_settings: ( local &success local &file local &script_name local &window_name local &print_error entry &window_name &print_error ; Check if the window's saved settings file exists. &script_name=os.ppf() &script_name=os.file.name("&script_name") &file=os.ptd() &file="&(file)\__&(script_name)_&(window_name)_dim.cmm" if (os.file.access("&file", "W")==TRUE()) ( ; Delete the file. del &file &success=1 ) else ( if ("&print_error"!="") ( print %ERROR "ERROR: wa_delete_saved_window_settings() failed to delete window settings for '&window_name'." ) &success=0 ) return &success ) ;;;;;;;;;;;;; End of "Lauterbach T32 "Window/Area" Utility Subs" ;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; ARGS Commands: ; ; "line" = PRACTICE macro string which isn't wrapped in double quotes. Full ; lines can be read with "entry %LINE &". ; ; See "args_:" subroutine headers for more information. ; ; (int) create_client [cmd_line] ; (int) switch_area ; (int) reset_cmd_line [cmd_line] ; (int) set_opts ; (int) clear_opts ; ; (string) get_arg [prompt_line] ; (string[2]) get_kwarg [prompt_line] ; (int) get_num_unread ; (line) get_cmd_line [unread_only_flag] ; ; (int) print_hist ; (line) get_hist_entry ; (int) get_hist_size ; ; (string) get_error [client_id] ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; ARGS Options: ; ; All options are disabled by default. ; ; help_cmd=[cmd] - Sets the command string for the help sub. Requires a ; help sub to call. ; help_sub=[sub] - Sets the subroutine for the help command. ; ; hist_cmd=[cmd] - Sets the command string for the history operation. ; Requries a history sub to call. ; hist_sub=[sub] - Sets the subroutine for the history command. ; ; nonempty_cmds=[0|1] - If set to one, repeats in-script prompts until a ; non-empty arg is received from the user. ; ; nonempty_vals=[0|1] - If set to one, "get_kwarg" returns an error ; upon detecting a value-less keyword argument (an ; error is always returned to key-less kwargs). ; ; print_errors=[0|1] - If set to one, error messages are printed to the ; I/O area automatically. ; ; ARGS Error Reporting: ; ; All ARGS commands return ARGS_ERR upon detecting failures. Clients may ; use the "get_error" ARGS command to query the error type that was ; generated by the previous command. ; ; ARGS Error Type Strings: ; ; NO_ERROR => No error generated by the previous command. ; NO_CMD => Missing command. ; INV_CMD => Invalid command. ; ; LONG_CMD_LINE => Overlength user command line. ; NO_CLIENT_ID => Missing client ID. ; INV_CLIENT_ID => Invalid client ID (for non-"get_error" commands). ; ; GET_ERR_INV_ID => Invalid "get_error" client ID. ; ; NO_CLIENT_NAME => Missing client name argument. ; INV_CLIENT_NAME => Overlength client name. ; NO_IO_AREA => Missing I/O area argument. ; INV_IO_AREA => Nonexistent area or overlength name. ; ; NO_OPT_KWARGS => Missing option keyword arguments. ; LONG_OPT_CMD => Overlength help/history/quit command option. ; DUP_OPT_KEY => Duplicate option keyword. ; INV_OPT_KEY => Invalid option keyword. ; INV_OPT_VAL => Invalid option value. ; OPT_CMD_NO_SUB => Missing sub for help/history/quit command option. ; ; NO_KWARG_KEY => Key-less keyword argument detected by "get_kwarg". ; NO_KWARG_VAL => Value-less keyword argument detected by "get_kwarg" ; and the "nonempty_vals" option is enabled. ; ; INV_HIST_AGE => Invalid "get_hist_entry" entry-age. ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;============================================================================; ; T32-GLOBAL MACROS ; ;============================================================================; ;============================================================================; ; SCRIPT-GLOBAL MACROS ; ;============================================================================; ;============================================================================; ; MAIN ; ;============================================================================; args_main: ( local &cmd_line local &cmd local &read_idx local &cmd_ret local &client_id &client_id="" ; Grab the entire launch line. entry %LINE &cmd_line ; Attempt to read the required command. gosub args_get_next_substr_ws "&cmd_line" 0. entry &cmd &read_idx if ("&cmd"=="") ( &args_latest_error="NO_CMD" &cmd_ret="ARGS_ERR" goto args_record_errors ) ; Cut the command word out of the command line. &cmd_line=string.cut("&cmd_line", &read_idx) ; ; Switch on the command. ; if ("&cmd"=="create_client") ; 'create_client' ( gosub args_create_client &cmd_line entry &cmd_ret goto args_record_errors ) ; Attempt to read the client ID. gosub args_get_next_substr_ws "&cmd_line" 0. entry &client_id &read_idx ; Validate the client ID. if ("&client_id"!="") ( ON ERROR gosub ( return ) if ((&client_id<0)||(&client_id>=&args_client_count)) ( ; Note that if 'client_id' isn't numeric, PRACTICE will still pass into ; this block as part of its behavior for invalid flow-control commands. &client_id="" if ("&cmd"=="get_error") ( &args_latest_error="GET_ERR_INV_ID" ) else ( &args_latest_error="INV_CLIENT_ID" ) &cmd_ret="ARGS_ERR" goto args_record_errors ) ) ; ; Continue switching on the command. ; if ("&cmd"=="get_error") ; 'get_error' ( ; Set the global variable names for the client. if ("&client_id"!="") ( gosub args_set_gvar_names &client_id ) gosub args_get_error &client_id entry &cmd_ret goto args_record_errors ) ; Require a client ID for all following commands. if ("&client_id"=="") ( &args_latest_error="NO_CLIENT_ID" &cmd_ret="ARGS_ERR" goto args_record_errors ) ; Cut the client ID out of the command line. &cmd_line=string.cut("&cmd_line", &read_idx) ; Set the global variable names for the client. gosub args_set_gvar_names &client_id ; ; Continue switching on the command. ; &cmd_ret="" if ("&cmd"=="switch_area") ; 'switch_area' ( gosub args_switch_area &cmd_line ) else if ("&cmd"=="reset_cmd_line") ; 'reset_cmd_line' ( gosub args_reset_cmd_line &cmd_line ) else if ("&cmd"=="set_opts") ; 'set_opts' ( gosub args_set_opts &cmd_line ) else if ("&cmd"=="clear_opts") ; 'clear_opts' ( gosub args_clear_opts ) else if ("&cmd"=="get_arg") ; 'get_arg' ( gosub args_get_arg &cmd_line ) else if ("&cmd"=="get_kwarg") ; 'get_kwarg' ( gosub args_get_kwarg &cmd_line ) else if ("&cmd"=="get_cmd_line") ; 'get_cmd_line' ( gosub args_get_cmd_line &cmd_line ) else if ("&cmd"=="get_num_unread") ; 'get_num_unread' ( gosub args_get_num_unread ) else if ("&cmd"=="print_hist") ; 'print_hist' ( gosub args_print_hist ) else if ("&cmd"=="get_hist_entry") ; 'get_hist_entry' ( gosub args_get_hist_entry &cmd_line ) else if ("&cmd"=="get_hist_size") ; 'get_hist_size' ( gosub args_get_hist_size ) else ( ; Invalid command. print %ERROR "ERROR [&ARGS_SCRIPT_FILE]:" print %ERROR " Unknown ARGS command detected ('&cmd')." &args_latest_error="INV_CMD" &cmd_ret="ARGS_ERR" ) if ("&cmd_ret"=="") ( entry %LINE &cmd_ret &cmd_ret=string.trim("&cmd_ret") ) ; ; Record error states. ; args_record_errors: if ("&cmd_ret"=="ARGS_ERR") ( if ("&client_id"!="") ; Non-empty 'client_id' => gvar names are set. ( var.if (\&gvar_name_print_errors_en) ( gosub args_print_error ) ) ) else ( &args_latest_error="NO_ERROR" ) if ("&client_id"!="") ; Non-empty 'client_id' => gvar names are set. ( var.assign \&gvar_name_client_error = "&args_latest_error" ) ; ; Return the command's status to the caller script. ; return &cmd_ret ) ;============================================================================; ; UTILITY SUB-ROUTINES ; ;============================================================================; ;----------------------------------------------------------------------------- ; ; SUB: void args_print_error ( void ) ; ; INFO: Prints the ARGS error type and a short description to the client's ; I/O area. ; ; RETURNS: Void. ; ;----------------------------------------------------------------------------- args_print_error: ( print %ERROR "ERROR [&ARGS_SCRIPT_FILE]:" ; ; Switch on the latest error type. ; if ("&args_latest_error"=="NO_CMD") ( print %ERROR " 'NO_CMD' => Missing command." ) else if ("&args_latest_error"=="INV_CMD") ( print %ERROR " 'INV_CMD' => Invalid command." ) else if ("&args_latest_error"=="LONG_CMD_LINE") ( print %ERROR " 'LONG_CMD_LINE' => Overlength user command line." ) else if ("&args_latest_error"=="NO_CLIENT_ID") ( print %ERROR " 'NO_CLIENT_ID' => Missing client ID." ) else if ("&args_latest_error"=="INV_CLIENT_ID") ( print %ERROR " 'INV_CLIENT_ID' => Invalid client ID (for non-'get_error' commands)." ) else if ("&args_latest_error"=="GET_ERR_INV_ID") ( print %ERROR " 'GET_ERR_INV_ID' => Invalid 'get_error' client ID." ) else if ("&args_latest_error"=="NO_CLIENT_NAME") ( print %ERROR " 'NO_CLIENT_NAME' => Missing client name argument." ) else if ("&args_latest_error"=="INV_CLIENT_NAME") ( print %ERROR " 'INV_CLIENT_NAME' => Overlength client name." ) else if ("&args_latest_error"=="NO_IO_AREA") ( print %ERROR " 'NO_IO_AREA' => Missing I/O area argument." ) else if ("&args_latest_error"=="INV_IO_AREA") ( print %ERROR " 'INV_IO_AREA' => Nonexistent area or overlength name." ) else if ("&args_latest_error"=="NO_OPT_KWARGS") ( print %ERROR " 'NO_OPT_KWARGS' => Missing option keyword arguments." ) else if ("&args_latest_error"=="LONG_OPT_CMD") ( print %ERROR " 'LONG_OPT_CMD' => Overlength help/history/quit command option." ) else if ("&args_latest_error"=="DUP_OPT_KEY") ( print %ERROR " 'DUP_OPT_KEY' => Duplicate option keyword." ) else if ("&args_latest_error"=="INV_OPT_KEY") ( print %ERROR " 'INV_OPT_KEY' => Invalid option keyword." ) else if ("&args_latest_error"=="INV_OPT_VAL") ( print %ERROR " 'INV_OPT_VAL' => Invalid option value." ) else if ("&args_latest_error"=="OPT_CMD_NO_SUB") ( print %ERROR " 'OPT_CMD_NO_SUB' => Missing sub for help/history/quit command option." ) else if ("&args_latest_error"=="NO_KWARG_KEY") ( print %ERROR " 'NO_KWARG_VAL' => Key-less keyword argument detected by 'get_kwarg'." ) else if ("&args_latest_error"=="NO_KWARG_VAL") ( print %ERROR " 'NO_KWARG_VAL' => Value-less keyword argument detected by 'get_kwarg'." ) else if ("&args_latest_error"=="INV_HIST_AGE") ( print %ERROR " 'INV_HIST_AGE' => Invalid 'get_hist_entry' entry-age." ) else ( print %ERROR " Unknown ARGS error!" ) return ) ;----------------------------------------------------------------------------- ; ; SUB: int args_var_assign_string ; ( ; string var_buf_name, ; int var_buf_len, ; line str_in ; ) ; ; INFO: Fills a character buffer with a zero-terminated string. Truncates ; the string to fit within the buffer variable if necessary. ; ; The 'str_in' line should not be wrapped in double quotes. ; ; RETURNS: -1 if the string is truncated or a parameter is missing, else 0. ; ; NOTES: Doubles all '\' for var.string() reads. Any time a user string may ; contain '\', this sub should be used instead of "var.assign". ; ; The paramaters are read as a single line to prevent "var.assign" ; issues with double quotes. ; ;----------------------------------------------------------------------------- args_var_assign_string: ( local &read_idx local &var_buf_name local &var_buf_len local &str_in local &str_in_len entry %LINE &str_in ; Extract the variable buffer symbol name. gosub args_get_next_substr_ws "&str_in" 0. entry &var_buf_name &read_idx if ("&var_buf_name"=="") ( return -1. ) ; Extract the buffer length. gosub args_get_next_substr_ws "&str_in" &read_idx entry &var_buf_len &read_idx if ("&var_buf_len"=="") ( return -1. ) ; Isolate the input string. &str_in=string.cut("&str_in", &read_idx) &str_in=string.trim("&str_in") ; Double each '\' to ensure proper var.string() read interpretation. &str_in=string.replace("&str_in", "\", "\\", 0.) ; Trim the string to prevent buffer overflow. &str_in_len=string.length("&str_in") &str_in=string.mid("&str_in", 0, &var_buf_len-1) ; Assign the input string to the buffer variable. var.assign \&var_buf_name = "&str_in" ; Return -1 iff the input string was truncated. if (&str_in_len>=&var_buf_len) ( return -1. ) else ( return 0. ) ) ;----------------------------------------------------------------------------- ; ; SUB: string args_get_client_name ( int client_id ) ; ; INFO: Gets the 'client-name' global variable name from the client ID. ; ; RETURNS: The ARGS client name global variable name. ; ; NOTES: Does not verify the client ID. ; ;----------------------------------------------------------------------------- args_get_client_name: ( local &gvar_name local &client_id entry &client_id ; ; Convert ID to decimal format to ensure consistency. ; &client_id=format.decimal(0, &client_id) ; ; Set the global variable names. ; &gvar_name="args_client_name_&client_id" return &gvar_name ) ;----------------------------------------------------------------------------- ; ; SUB: void args_set_gvar_names ( int client_id ) ; ; INFO: Sets the global T32 variable names for the client. ; ; RETURNS: Void. ; ; NOTES: Does not verify the client ID. ; ;----------------------------------------------------------------------------- args_set_gvar_names: ( local &suffix local &client_id entry &client_id ; ; Convert ID to decimal format to ensure consistency. ; &suffix=format.decimal(0, &client_id) ; ; Set the global variable names. ; gosub args_get_client_name &client_id entry &gvar_name_client_name &gvar_name_area_name="args_area_name_&suffix" &gvar_name_client_error="args_err_&suffix" &gvar_name_cmd_line="args_cmd_line_&suffix" &gvar_name_read_idx="args_read_idx_&suffix" &gvar_name_help_cmd="args_help_cmd_&suffix" &gvar_name_help_sub="args_help_sub_&suffix" &gvar_name_hist_cmd="args_hist_cmd_&suffix" &gvar_name_hist_sub="args_hist_sub_&suffix" &gvar_name_nonempty_cmds="args_non_empty_cmds_&suffix" &gvar_name_nonempty_vals="args_non_empty_vals_&suffix" &gvar_name_print_errors_en="args_print_errors_en_&suffix" &gvar_name_hist_en="args_hist_en_&suffix" &gvar_name_hist_tip_idx="args_hist_tip_idx_&suffix" &gvar_name_num_hist_entries="args_num_hist_entries_&suffix" &gvar_name_hist_buf="args_hist_buf_&suffix" return ) ;----------------------------------------------------------------------------- ; ; SUB: string args_verify_and_select_area ( int area_name ) ; ; INFO: Verifies that an area name is valid and the area exists. The area ; is selected as part of the verification. ; ; RETURNS: NO_ERROR => Valid area was selected. ; NO_IO_AREA => Missing area name parameter. ; INV_IO_AREA => Area doesn't exist or invalid/overlength name. ; ; NOTES: ARGS I/O area names must be less than 128 characters. ; If in invalid area is detected, 'args_latest_error' is updated. ; ;----------------------------------------------------------------------------- args_verify_and_select_area: ( local &area_name entry &area_name ; Verify area name length is valid. if ("&area_name"=="") ( return NO_IO_AREA ) &err=string.length("&area_name") if (&err>=128.) ( return INV_IO_AREA ) ; Verify that the given I/O area already exists. ON ERROR gosub ( &err="!" return ) &err="" area.select &area_name if ("&err"=="!") ( return INV_IO_AREA ) else ( return NO_ERROR ) ) ;----------------------------------------------------------------------------- ; ; SUB: string args_get_next_substr_ws ; ( ; string src_str, ; int read_idx ; ) ; ; INFO: Returns the next sub-string word from a source string, or nothing ; if there is no such word. The words are split by spaces. ; ; RETURNS: {sub_str, read_idx} -OR- Nothing. ; ; Example: ; Returns "bc 5" (sans quotes). ; ;----------------------------------------------------------------------------- args_get_next_substr_ws: ( local &src_str local &src_len local &read_idx local &sub_str local &start_idx entry &src_str &read_idx if (&read_idx<0) ( ; Negative read index--return empty string (and no index). return ) &src_len=string.length(&src_str) ; Find the start of non-whitespace segment. while (&read_idx<&src_len) ( if (string.char(&src_str, &read_idx)!=' ') ( &start_idx=&read_idx goto args__get_substr_ws_find_end ) &read_idx=&read_idx+1 ) ; No non-whitespace found--return empty string (and no index). return args__get_substr_ws_find_end: ; Find the end of non-whitespace segment. &read_idx=&read_idx+1 while (&read_idx<&src_len) ( if (string.char(&src_str, &read_idx)==' ') ( ; Cut out leading and trailing whitespace &sub_str=string.mid(&src_str, &start_idx, &read_idx-&start_idx) goto args__get_substr_ws_return ) &read_idx=&read_idx+1 ) ; No trailing white-space found--cut out any leading whitespace. &sub_str=string.cut(&src_str, &start_idx) args__get_substr_ws_return: return &sub_str &read_idx ) ;----------------------------------------------------------------------------- ; ; SUB: int args_get_circ_buf_idx ( int base_idx, int delta, int buf_len ) ; ; INFO: Returns the index of an entry in a circular buffer. ; ; RETURNS: Circular buffer index. ; ;----------------------------------------------------------------------------- args_get_circ_buf_idx: ( local &ret_idx local &base_idx local &delta local &buf_len entry &base_idx &delta &buf_len &base_idx=(&base_idx%&buf_len) &delta=(&delta%&buf_len) &ret_idx=(&base_idx+&delta) if (&ret_idx<0) ( &ret_idx=(&buf_len+&ret_idx) ) else if (&ret_idx>=&buf_len) ( &ret_idx=(&ret_idx-&buf_len) ) return &ret_idx ) ;----------------------------------------------------------------------------- ; ; SUB: void args_add_hist_entry ( string new_hist_entry ) ; ; INFO: Adds a history entry. Does not add redundant/empty entries. ; ; RETURNS: Void. ; ;----------------------------------------------------------------------------- args_add_hist_entry: ( local &idx local &youngest_idx local &match_idx local &match_hist_entry local &hist_entry_newer local &hist_entry_older local &num_entries local &tip_idx local &hist_cmd local &new_hist_entry entry &new_hist_entry ; Trim the line and short-circuit if the line is empty or a history command. &new_hist_entry=string.trim(&new_hist_entry) &hist_cmd=var.string(\&gvar_name_hist_cmd) if (("&new_hist_entry"=="")||("&new_hist_entry"=="&hist_cmd")) ( return ) &tip_idx=var.value(\&gvar_name_hist_tip_idx) ; Truncate history entries to fit within the buffer. &new_hist_entry=string.mid("&new_hist_entry", 0., 511.) ; Check if the exact entry is already stored in history. &match_idx=0 while (&match_idx<&ARGS_MAX_HIST_ENTRIES) ( &match_hist_entry=var.string(\&gvar_name_hist_buf[&match_idx]) if ("&match_hist_entry"=="&new_hist_entry") ( ; Match found--reorder entries. goto args__add_hist_entry_reorder ) &match_idx=&match_idx+1 ) ; Add a new entry to the history buffer. gosub args_var_assign_string &gvar_name_hist_buf[&tip_idx] 512. &new_hist_entry &num_entries=var.value(\&gvar_name_num_hist_entries) if (&num_entries<&ARGS_MAX_HIST_ENTRIES) ( ; Increment the number of history entries for the client. &num_entries=&num_entries+1 var.assign \&gvar_name_num_hist_entries = &num_entries ) gosub args_get_circ_buf_idx &tip_idx 1. &ARGS_MAX_HIST_ENTRIES entry &tip_idx var.assign \&gvar_name_hist_tip_idx = &tip_idx return args__add_hist_entry_reorder: gosub args_get_circ_buf_idx &tip_idx -1. &ARGS_MAX_HIST_ENTRIES entry &youngest_idx ; Shift the offset entries up in age. &idx=&youngest_idx &hist_entry_newer=var.string(\&gvar_name_hist_buf[&idx]) while (&idx!=&match_idx) ( gosub args_get_circ_buf_idx &idx -1. &ARGS_MAX_HIST_ENTRIES entry &idx &hist_entry_older=var.string(\&gvar_name_hist_buf[&idx]) gosub args_var_assign_string &gvar_name_hist_buf[&idx] 512. &hist_entry_newer &hist_entry_newer="&hist_entry_older" &idx=&idx ) ; Move the matched history entry to the youngest history entry. gosub args_var_assign_string &gvar_name_hist_buf[&youngest_idx] 512. &match_hist_entry return ) ;============================================================================; ; ARGS COMMAND SUB-ROUTINES ; ;============================================================================; ;----------------------------------------------------------------------------- ; ; SUB: int args_create_client ; ( ; string client_name_in, ; string initial_io_area_name, ; line initial_cmd_line ; ) ; ; INFO: Initializes an ARGS client. If the client already exists, it is ; re-initialized. ; ; Do not wrap any of the paramaters in double quotes. ; The given I/O area is selected in order to confirm that it exists. ; The client is responsible for creating this I/O area. ; ; RETURNS: A client ID upon success or "ARGS_ERR" upon failure. ; ; ERRORS: {NO_CLIENT_NAME, INV_CLIENT_NAME, ; NO_IO_AREA, INV_IO_AREA, LONG_CMD_LINE}. ; ; NOTES: The client and I/O area names must be less than 128 characters. ; The paramaters are read as a single line in order to avoid double ; quote issues which arise otherwise. ; ;----------------------------------------------------------------------------- args_create_client: ( local &resident_client_name local &client_id local &idx local &read_idx local &client_name_var local &client_is_new local &client_name_in local &initial_io_area_name local &initial_cmd_line entry %LINE &initial_cmd_line ; First extract the client name. gosub args_get_next_substr_ws "&initial_cmd_line" 0. entry &client_name_in &read_idx if ("&client_name_in"=="") ( &args_latest_error="NO_CLIENT_NAME" return ARGS_ERR ) ; Check for overlength client name. if (&read_idx>=128.) ( &args_latest_error="INV_CLIENT_NAME" return ARGS_ERR ) ; Next extract the I/O area name. gosub args_get_next_substr_ws "&initial_cmd_line" &read_idx entry &initial_io_area_name &read_idx ; Check that the area is valid. gosub args_verify_and_select_area &initial_io_area_name entry &args_latest_error if ("&args_latest_error"!="NO_ERROR") ( return ARGS_ERR ) ; Isolate and trim the initial command line. &initial_cmd_line=string.cut("&initial_cmd_line", &read_idx) &initial_cmd_line=string.trim("&initial_cmd_line") ; ; Check if the client already exists. ; &client_is_new=0. &client_id=0 while (&client_id<&args_client_count) ( gosub args_get_client_name &client_id entry &client_name_var &resident_client_name=var.string(\&client_name_var) if ("&client_name_in"=="&resident_client_name") ( goto args__create_client_gvar_names ) &client_id=&client_id+1 ) ; Client does not exist--increment the client count. &args_client_count=&args_client_count+1 &client_is_new=1. args__create_client_gvar_names: ; Set the global variable names for the client. gosub args_set_gvar_names &client_id if (&client_is_new!=0.) ( ; ; Client doesn't already exist--create new client global variables. ; var.newglobal char[128.] \&gvar_name_client_name var.newglobal char[128.] \&gvar_name_area_name var.newglobal char[64.] \&gvar_name_client_error var.newglobal char[512.] \&gvar_name_cmd_line var.newglobal int \&gvar_name_read_idx var.newglobal char[64.] \&gvar_name_help_cmd var.newglobal char[64.] \&gvar_name_help_sub var.newglobal char[64.] \&gvar_name_hist_cmd var.newglobal char[64.] \&gvar_name_hist_sub var.newglobal int \&gvar_name_nonempty_cmds var.newglobal int \&gvar_name_nonempty_vals var.newglobal int \&gvar_name_print_errors_en var.newglobal int \&gvar_name_hist_en var.newglobal int \&gvar_name_hist_tip_idx var.newglobal int \&gvar_name_num_hist_entries var.newglobal char[32.][512.] \&gvar_name_hist_buf ; Start clients with an empty history. var.assign \&gvar_name_hist_en = 0 var.assign \&gvar_name_hist_tip_idx = 0 var.assign \&gvar_name_num_hist_entries = 0 &idx=0. while (&idx<32.) ( var.assign \&gvar_name_hist_buf[&idx][0] = 0 &idx=&idx+1. ) ) ; ; Initialize the client's global state. ; gosub args_var_assign_string &gvar_name_client_name 128. &client_name_in entry &idx if (&idx==-1.) ; Need to double check length due to '\' doubling. ( &args_latest_error="INV_CLIENT_NAME" return ARGS_ERR ) gosub args_var_assign_string &gvar_name_area_name 128. &initial_io_area_name entry &idx if (&idx==-1.) ; Need to double check length due to '\' doubling. ( &args_latest_error="INV_IO_AREA" return ARGS_ERR ) gosub args_var_assign_string &gvar_name_cmd_line 512. &initial_cmd_line entry &idx if (&idx==-1.) ; Need to double check length due to '\' doubling. ( &args_latest_error="LONG_CMD_LINE" return ARGS_ERR ) var.assign \&gvar_name_client_error = "NO_ERROR" var.assign \&gvar_name_read_idx = 0 var.assign \&gvar_name_help_cmd[0] = 0 var.assign \&gvar_name_help_sub[0] = 0 var.assign \&gvar_name_hist_cmd[0] = 0 var.assign \&gvar_name_hist_sub[0] = 0 var.assign \&gvar_name_nonempty_cmds = 0 var.assign \&gvar_name_nonempty_vals = 0 var.assign \&gvar_name_print_errors_en = 0 ; Unconditionally record the launch line in history. gosub args_add_hist_entry "&initial_cmd_line" ; ; Return the initialized client's ID. ; return &client_id ) ;----------------------------------------------------------------------------- ; ; SUB: int args_switch_area ( string new_area ) ; ; INFO: Switches the client's I/O area. ; Do not wrap 'new_area' parameter in double quotes. ; ; RETURNS: Nothing upon success, else "ARGS_ERR". ; ; ERRORS: {NO_CLIENT_ID, INV_CLIENT_ID, NO_IO_AREA, INV_IO_AREA}. ; ; NOTES: Client ID is pre-verified by main. ; Client global variable names are pre-assigned by main. ; ;----------------------------------------------------------------------------- args_switch_area: ( local &new_area entry &new_area ; Verify and select the area. gosub args_verify_and_select_area &new_area entry &args_latest_error if ("&args_latest_error"!="NO_ERROR") ( return ARGS_ERR ) ; Record the new client I/O area. gosub args_var_assign_string &gvar_name_area_name 128. &new_area entry &idx if (&idx==-1.) ; Need to double check length due to '\' doubling. ( &args_latest_error="INV_IO_AREA" return ARGS_ERR ) ; ; Return success. ; return ) ;----------------------------------------------------------------------------- ; ; SUB: int args_reset_cmd_line ( [line new_cmd_line] ) ; ; INFO: Resets the buffered ARGS command line. ; Do not wrap the 'new_cmd_line' parameter in double quotes. ; ; RETURNS: Nothing upon success, else "ARGS_ERR". ; ; ERRORS: {NO_CLIENT_ID, INV_CLIENT_ID, LONG_CMD_LINE}. ; ; NOTES: Client ID is pre-verified by main. ; Client global variable names are pre-assigned by main. ; ;----------------------------------------------------------------------------- args_reset_cmd_line: ( local &idx local &new_cmd_line entry %LINE &new_cmd_line ; ; Set the command line buffer state. ; gosub args_var_assign_string &gvar_name_cmd_line 512. &new_cmd_line entry &idx if (&idx==-1.) ( &args_latest_error="LONG_CMD_LINE" return ARGS_ERR ) ; ; Record the new command line in history. ; &new_cmd_line=string.trim("&new_cmd_line") if ("&new_cmd_line"!="") ( var.if (\&gvar_name_hist_en!=0) ( gosub args_add_hist_entry "&new_cmd_line" ) ) var.assign \&gvar_name_read_idx = 0 ; ; Return success. ; return ) ;----------------------------------------------------------------------------- ; ; SUB: int args_set_opts ( line opts ) ; ; INFO: Sets ARGS options. Any unspecified options are left unmodified. ; All options are initially disabled by default. ; ; Do not wrap the 'opts' parameter in double quotes. ; See "ARGS Options:" for more information. ; ; RETURNS: Nothing upon success, else "ARGS_ERR". ; ; ERRORS: {NO_CLIENT_ID, INV_CLIENT_ID, NO_OPT_KWARGS, DUP_OPT_KEY ; INV_OPT_KEY, INV_OPT_VAL, LONG_OPT_CMD, OPT_CMD_NO_SUB}. ; ; NOTES: Client ID is pre-verified by main. ; Client global variable names are pre-assigned by main. ; Help/history/quit commands must be less than 64 characters. ; ;----------------------------------------------------------------------------- args_set_opts: ( local &idx local &help_cmd local &help_sub local &hist_cmd local &hist_sub local &nonempty_cmds local &nonempty_vals local &print_errors local &opts entry %LINE &opts ; ; Return failure if no options are given. ; &opts=string.trim("&opts") if ("&opts"=="") ( &args_latest_error="NO_OPT_KWARGS" return ARGS_ERR ) ; ; Attempt to extract option keword arguments. ; &help_cmd=string.ScanAndExtract("&opts", "help_cmd=", "INV_OPT") &help_sub=string.ScanAndExtract("&opts", "help_sub=", "INV_OPT") &hist_cmd=string.ScanAndExtract("&opts", "hist_cmd=", "INV_OPT") &hist_sub=string.ScanAndExtract("&opts", "hist_sub=", "INV_OPT") &nonempty_cmds=string.ScanAndExtract("&opts", "nonempty_cmds=", "INV_OPT") &nonempty_vals=string.ScanAndExtract("&opts", "nonempty_vals=", "INV_OPT") &print_errors=string.ScanAndExtract("&opts", "print_errors=", "INV_OPT") ; ; Process options. ; if ("&help_sub"!="INV_OPT") ( ; Record the client's option. gosub args_var_assign_string &gvar_name_help_sub 64. &help_sub entry &idx if (&idx==-1.) ( &args_latest_error="LONG_OPT_CMD" return ARGS_ERR ) ; Remove the option from the options line. &opts=string.replace("&opts", "help_sub=&help_sub", "", 1) ; Check for duplicate option. &idx=string.scan("&opts", "help_sub=", 0) if (&idx!=-1.) ( &args_latest_error="DUP_OPT_KEY" return ARGS_ERR ) ) if ("&help_cmd"!="INV_OPT") ( ; Require a subroutine for the command option. &help_sub=var.string(\&gvar_name_help_sub) if (("&help_cmd"!="")&&("&help_sub"=="")) ( print %ERROR "ERROR [&ARGS_SCRIPT_FILE]:" print %ERROR " Help sub is required for help command option (help_cmd='&help_cmd')." &args_latest_error="OPT_CMD_NO_SUB" return ARGS_ERR ) ; Record the client's option. gosub args_var_assign_string &gvar_name_help_cmd 64. &help_cmd entry &idx if (&idx==-1.) ( &args_latest_error="LONG_OPT_CMD" return ARGS_ERR ) ; Remove the option from the options line. &opts=string.replace("&opts", "help_cmd=&help_cmd", "", 1) ; Check for duplicate option. &idx=string.scan("&opts", "help_cmd=", 0) if (&idx!=-1.) ( &args_latest_error="DUP_OPT_KEY" return ARGS_ERR ) ) if ("&hist_sub"!="INV_OPT") ( ; Record the client's option. gosub args_var_assign_string &gvar_name_hist_sub 64. &hist_sub entry &idx if (&idx==-1.) ( &args_latest_error="LONG_OPT_CMD" return ARGS_ERR ) ; Remove the option from the options line. &opts=string.replace("&opts", "hist_sub=&hist_sub", "", 1) ; Check for duplicate option. &idx=string.scan("&opts", "hist_sub=", 0) if (&idx!=-1.) ( &args_latest_error="DUP_OPT_KEY" return ARGS_ERR ) ) if ("&hist_cmd"!="INV_OPT") ( ; Require a subroutine for the command option. &hist_sub=var.string(\&gvar_name_hist_sub) if (("&hist_cmd"!="")&&("&hist_sub"=="")) ( print %ERROR "ERROR [&ARGS_SCRIPT_FILE]:" print %ERROR " History sub is required for history command option (hist_cmd='&hist_cmd')." &args_latest_error="OPT_CMD_NO_SUB" return ARGS_ERR ) ; Start recording command history. if ("&hist_cmd"!="") ( var.assign \&gvar_name_hist_en = 1 ) ; Record the client's option. gosub args_var_assign_string &gvar_name_hist_cmd 64. &hist_cmd entry &idx if (&idx==-1.) ( &args_latest_error="LONG_OPT_CMD" return ARGS_ERR ) ; Remove the option from the options line. &opts=string.replace("&opts", "hist_cmd=&hist_cmd", "", 1) ; Check for duplicate option. &idx=string.scan("&opts", "hist_cmd=", 0) if (&idx!=-1.) ( &args_latest_error="DUP_OPT_KEY" return ARGS_ERR ) ) if ("&nonempty_cmds"!="INV_OPT") ( ; Mandate binary 'nonempty' option. if (("&nonempty_cmds"!="0")&&("&nonempty_cmds"!="1")) ( print %ERROR "ERROR [&ARGS_SCRIPT_FILE]:" print %ERROR " Option 'nonempty_cmds' must be 1 or 0 (got '&nonempty_cmds')." &args_latest_error="INV_OPT_VAL" return ARGS_ERR ) ; Record the client's option. var.assign \&gvar_name_nonempty_cmds = &nonempty_cmds ; Remove the option from the options line. &opts=string.replace("&opts", "nonempty_cmds=&nonempty_cmds", "", 1) ; Check for duplicate option. &idx=string.scan("&opts", "nonempty_cmds=", 0) if (&idx!=-1.) ( &args_latest_error="DUP_OPT_KEY" return ARGS_ERR ) ) if ("&nonempty_vals"!="INV_OPT") ( ; Mandate binary 'nonempty' option. if (("&nonempty_vals"!="0")&&("&nonempty_vals"!="1")) ( print %ERROR "ERROR [&ARGS_SCRIPT_FILE]:" print %ERROR " Option 'nonempty_vals' must be 1 or 0 (got '&nonempty_vals')." &args_latest_error="INV_OPT_VAL" return ARGS_ERR ) ; Record the client's option. var.assign \&gvar_name_nonempty_vals = &nonempty_vals ; Remove the option from the options line. &opts=string.replace("&opts", "nonempty_vals=&nonempty_vals", "", 1) ; Check for duplicate option. &idx=string.scan("&opts", "nonempty_vals=", 0) if (&idx!=-1.) ( &args_latest_error="DUP_OPT_KEY" return ARGS_ERR ) ) if ("&print_errors"!="INV_OPT") ( ; Mandate binary 'nonempty' option. if (("&print_errors"!="0")&&("&print_errors"!="1")) ( print %ERROR "ERROR [&ARGS_SCRIPT_FILE]:" print %ERROR " Option 'print_errors' must be 1 or 0 (got '&print_errors')." &args_latest_error="INV_OPT_VAL" return ARGS_ERR ) ; Record the client's option. var.assign \&gvar_name_print_errors_en = &print_errors ; Remove the option from the options line. &opts=string.replace("&opts", "print_errors=&print_errors", "", 1) ; Check for duplicate option. &idx=string.scan("&opts", "print_errors=", 0) if (&idx!=-1.) ( &args_latest_error="DUP_OPT_KEY" return ARGS_ERR ) ) ; ; Detect unknown option keywords. ; &opts=string.trim("&opts") if ("&opts"!="") ( &args_latest_error="INV_OPT_KEY" return ARGS_ERR ) ; ; Return success. ; return ) ;----------------------------------------------------------------------------- ; ; SUB: int args_clear_opts ( void ) ; ; INFO: Sets all ARGS options to their default disabled state. ; ; RETURNS: Nothing upon success, else "ARGS_ERR". ; ; ERRORS: {NO_CLIENT_ID, INV_CLIENT_ID}. ; ; NOTES: Client ID is pre-verified by main. ; Client global variable names are pre-assigned by main. ; ;----------------------------------------------------------------------------- args_clear_opts: ( ; Clear every option. var.assign \&gvar_name_help_cmd[0] = 0 var.assign \&gvar_name_help_sub[0] = 0 var.assign \&gvar_name_hist_cmd[0] = 0 var.assign \&gvar_name_hist_sub[0] = 0 var.assign \&gvar_name_nonempty_cmds = 0 var.assign \&gvar_name_nonempty_vals = 0 var.assign \&gvar_name_print_errors_en = 0 ; ; Return success. ; return ) ;----------------------------------------------------------------------------- ; ; SUB: string args_get_arg ( [line prompt] ) ; ; INFO: Returns the next user argument, separated by spaces. Does not ; provide special handling of keyword arguments. Only prints a ; prompt line if all buffered arguments have been read previously. ; Selects the client's I/O area before/after user entry prompts. ; ; Do not wrap the 'prompt' parameter in double quotes. Note that the ; 'prompt' line will automatically be trimmed as a consequence of ; PRACTICE parameter-passing complications. ; ; RETURNS: "ARGS_ERR" => Error occured. ; => Success. ; ; ERRORS: {NO_CLIENT_ID, INV_CLIENT_ID, INV_IO_AREA, LONG_CMD_LINE}. ; ; NOTES: Client ID is pre-verified by main. ; Client global variable names are pre-assigned by main. ; ;----------------------------------------------------------------------------- args_get_arg: ( local &help_cmd local &help_sub local &hist_cmd local &hist_sub local &area_name local &arg local &read_idx local &cmd_line local &idx local &prompt local &prompt_printed entry %LINE &prompt args__get_arg_buffered: ; Read in the client's help/history/quit commands and subroutines. &help_cmd=var.string(\&gvar_name_help_cmd) &help_sub=var.string(\&gvar_name_help_sub) &hist_cmd=var.string(\&gvar_name_hist_cmd) &hist_sub=var.string(\&gvar_name_hist_sub) ; Read in the client's buffered command line and read position. &cmd_line=var.string(\&gvar_name_cmd_line) &read_idx=var.value(\&gvar_name_read_idx) &prompt_printed=0 ; ; Attempt to read next argument word from the buffered command line. ; gosub args_get_next_substr_ws "&cmd_line" &read_idx entry &arg &read_idx if ("&arg"=="") ( &read_idx=0 ; ; Read and verify the client's I/O area. ; &area_name=var.string(\&gvar_name_area_name) gosub args_verify_and_select_area &area_name entry &args_latest_error if ("&args_latest_error"!="NO_ERROR") ( &arg="INV_IO_AREA" var.assign \&gvar_name_read_idx = 0 var.assign \&gvar_name_cmd_line[0] = 0 return ) args__get_arg_user_prompt: ; ; Get the next command line from the user. ; area.select &area_name if (&prompt_printed==0) ( if ("&prompt"!="") ( print "&prompt" ) &prompt_printed=1 ) enter %LINE &cmd_line area.select &area_name ; Read the first argument word from the new command line. gosub args_get_next_substr_ws "&cmd_line" 0. entry &arg &read_idx if ("&arg"=="") ( &read_idx=0 ; Apply 'nonempty' command option. var.if (\&gvar_name_nonempty_cmds!=0) ( goto args__get_arg_user_prompt ) ) else ( ; Record the new command line in history. var.if (\&gvar_name_hist_en!=0) ( gosub args_add_hist_entry "&cmd_line" ) ) ) ; ; Update the client's buffered command line and read position. ; var.assign \&gvar_name_read_idx = &read_idx gosub args_var_assign_string &gvar_name_cmd_line 512. &cmd_line entry &idx if (&idx==-1.) ( &args_latest_error="LONG_CMD_LINE" return ARGS_ERR ) ; ; Check for optional help/history/quit commands. ; if (("&help_cmd"!="")&&("&arg"=="&help_cmd")) ( ; Call the help sub. gosub &help_sub ; Get the next argument. goto args__get_arg_buffered ) else if (("&hist_cmd"!="")&&("&arg"=="&hist_cmd")) ( ; Call the history sub. gosub &hist_sub ; Get the next argument. goto args__get_arg_buffered ) return &arg ) ;----------------------------------------------------------------------------- ; ; SUB: string[2] args_get_kwarg ( [line prompt] ) ; ; INFO: Returns the next user argument, separated by spaces. Treats any ; argument containing '=' as a keyword argument in format "key=val". ; Only prints a prompt line if all buffered arguments have been ; read previously. Can be interleaved with "get_arg" commands. ; Selects the client's I/O area before/after user entry prompts. ; ; Do not wrap the 'prompt' parameter in double quotes. Note that the ; 'prompt' line will automatically be trimmed as a consequence of ; PRACTICE parameter-passing complications. ; ; RETURNS: {"ARGS_ERR"} => A failure occured. ; {"NO_KEY", } => A non-keyword arg was found (no '='). ; {, } => A valid keyword arg was found. ; ; ERRORS: {NO_CLIENT_ID, INV_CLIENT_ID, INV_IO_AREA, LONG_CMD_LINE, ; NO_KWARG_KEY, [NO_KWARG_VAL]}. ; ; NOTES: Client ID is pre-verified by main. ; Client global variable names are pre-assigned by main. ; ; The 'NO_KWARG_VAL' error only occurs if the "nonempty_vals" option ; is enabled. ; ;----------------------------------------------------------------------------- args_get_kwarg: ( local &val local &key local &key_temp local &eq_char_idx local &arg local &prompt entry %LINE &prompt ; ; Get the next raw argument. ; gosub args_get_arg &prompt entry &arg if ("&arg"=="ARGS_ERR") ( return ARGS_ERR ) &eq_char_idx=string.scan("&arg", "=", 0) if (&eq_char_idx==-1.) ( ; ; Non-keyword argument detected. ; &key="NO_KEY" &val="&arg" ) else ( ; ; Keyword argument detected--spit it by '='. ; &val=string.cut("&arg", &eq_char_idx+1) &key=string.mid("&arg", 0, &eq_char_idx) &key_temp="&key" ; ; Require key/val pair to be adjacent to the '=' separator ; if ("&val"=="") ( ; Check if the non-empty kwarg value option is enabled. var.if (\&gvar_name_nonempty_vals!=0) ( print %ERROR "ERROR [&ARGS_SCRIPT_FILE]:" print %ERROR " Expected a value just after '=' (arg: '&arg')." &key="ARGS_ERR" &val="" &args_latest_error="NO_KWARG_VAL" ) ) if ("&key_temp"=="") ( print %ERROR "ERROR [&ARGS_SCRIPT_FILE]:" print %ERROR " Expected a key just before '=' (arg: '&arg')." &key="ARGS_ERR" &val="" &args_latest_error="NO_KWARG_KEY" ) ) return &key &val ) ;----------------------------------------------------------------------------- ; ; SUB: int args_get_num_unread ( void ) ; ; INFO: Scans the client's unread portion of its buffered command line, ; counting the number of unread arguments. ; ; RETURNS: The number of unread arguments, or "ARGS_ERR" upon failure. ; ; ERRORS: {NO_CLIENT_ID, INV_CLIENT_ID}. ; ; NOTES: Client ID is pre-verified by main. ; Client global variable names are pre-assigned by main. ; ;----------------------------------------------------------------------------- args_get_num_unread: ( local &count local &arg local &cmd_line local &read_idx &cmd_line=var.string(\&gvar_name_cmd_line) &read_idx=var.value(\&gvar_name_read_idx) ; ; Scan the unread portion of the buffered command line. ; &count=0 while TRUE() ( gosub args_get_next_substr_ws "&cmd_line" &read_idx entry &arg &read_idx if ("&arg"=="") ( ; ; Return the number of unread buffered arguments. ; return &count ) &count=&count+1 ) ) ;----------------------------------------------------------------------------- ; ; SUB: line args_get_cmd_line ( [flag unread] ) ; ; INFO: Returns the client's buffered command line. If the 'unread' flag ; is given, only the unread portion of the command line is returned. ; ; Callers can use "entry %LINE" to accept the entire return line. ; ; RETURNS: Command line or "ARGS_ERR" upon failure. ; ; ERRORS: {NO_CLIENT_ID, INV_CLIENT_ID}. ; ; NOTES: Client ID is pre-verified by main. ; Client global variable names are pre-assigned by main. ; ;----------------------------------------------------------------------------- args_get_cmd_line: ( local &cmd_line local &read_idx local &unread entry &unread &cmd_line=var.string(\&gvar_name_cmd_line) if ("&unread"!="") ( &read_idx=var.value(\&gvar_name_read_idx) &cmd_line=string.cut("&cmd_line", &read_idx) ) return &cmd_line ) ;----------------------------------------------------------------------------- ; ; SUB: int args_print_hist ( void ) ; ; INFO: Prints each history entry to the currently selected area. The ; oldest entry is printed at the top, with one entry per line. ; ; RETURNS: Nothing upon success, else "ARGS_ERR". ; ; ERRORS: {NO_CLIENT_ID, INV_CLIENT_ID}. ; ; NOTES: Client ID is pre-verified by main. ; Client global variable names are pre-assigned by main. ; ;----------------------------------------------------------------------------- args_print_hist: ( local &age local &hist_entry &age=var.value(\&gvar_name_num_hist_entries) &age=&age-1 ; ; Print each history entry with the oldest entry on top. ; while (&age>=0) ( gosub args_get_hist_entry &age entry %LINE &hist_entry print "&hist_entry " &age=&age-1 ) ; ; Return success. ; return ) ;----------------------------------------------------------------------------- ; ; SUB: line args_get_hist_entry ( int entry_age ) ; ; INFO: Gets the selected history entry (the youngest age is 0). ; Return value should be read with "entry %LINE". ; ; RETURNS: The history entry line upon success, else "ARGS_ERR". ; ; ERRORS: {NO_CLIENT_ID, INV_CLIENT_ID, INV_HIST_AGE}. ; ; NOTES: Client ID is pre-verified by main. ; Client global variable names are pre-assigned by main. ; ;----------------------------------------------------------------------------- args_get_hist_entry: ( local &entry_age local &hist_age local &hist_entry local &tip_idx entry &entry_age ; ; Validate the history entry age. ; &hist_age=var.value(\&gvar_name_num_hist_entries) if (&entry_age>&hist_age) ( &args_latest_error="INV_HIST_AGE" return ARGS_ERR ) ; Convert the entry age to a delta from the history tip index. &entry_age=(-1.-&entry_age) ; Get the history entry index. &tip_idx=var.value(\&gvar_name_hist_tip_idx) gosub args_get_circ_buf_idx &tip_idx &entry_age &ARGS_MAX_HIST_ENTRIES entry &entry_age ; ; Return the requested history entry line. ; &hist_entry=var.string(\&gvar_name_hist_buf[&entry_age]) return &hist_entry ) ;----------------------------------------------------------------------------- ; ; SUB: int args_get_hist_size( void ) ; ; INFO: Returns the client's number of command history entries. ; ; RETURNS: Client's history age (the youngest age is 0), or "ARGS_ERR" upon ; failure. ; ; ERRORS: {NO_CLIENT_ID, INV_CLIENT_ID}. ; ; NOTES: Client ID is pre-verified by main. ; Client global variable names are pre-assigned by main. ; ;----------------------------------------------------------------------------- args_get_hist_size: ( local &num_hist_entries ; ; Return the client's history age. ; &num_hist_entries=var.value(\&gvar_name_num_hist_entries) return &num_hist_entries ) ;----------------------------------------------------------------------------- ; ; SUB: string args_get_error ( [int client_id] ) ; ; INFO: Returns the error generated by the client's previous ARGS command. ; If no client ID is provided, the error generated by the globally- ; previous ARGS command is returned. ; ; See "ARGS Error Reporting:" for more information. ; ; RETURNS: An error type string (possibly "NO_ERROR"), or "ARGS_ERR" upon ; detecting an invalid client ID. ; ; ERRORS: {GET_ERR_INV_ID}. ; ; NOTES: Records the special 'GET_ERR_INV_ID' error upon failure in order ; to trouble-shoot improper "get_error" usage. ; ; Client ID is pre-verified by main. ; ;----------------------------------------------------------------------------- args_get_error: ( local &err_str local &client_id entry &client_id if ("&client_id"=="") ( ; ; Return the globally-previous error type string. ; return &args_latest_error ) else ( ; ; Return the client's previous error type string. ; gosub args_set_gvar_names &client_id &err_str=var.string(\&gvar_name_client_error) return &err_str ) ) ;################## ;END ARGS ;##################