#ifndef TARGJAFAANAAA_H
#define TARGJAFAANAAA_H
/* ========================================================================
FILE: TARGJAFAANAAA

Copyright (c) 2001-2020 by QUALCOMM Incorporated.  All Rights Reserved.        
=========================================================================== */

#define CONVERT_TO_MB_SHIFT 20
#define SD_PATH "/mmc1/"
#define REGION0_BASE 0x0
#define REGION0_SIZE 0x0020000
#define REGION1_BASE 0xFE800000
#define REGION1_SIZE 0x00040000
#define REGION2_BASE 0x2B000000
#define REGION2_SIZE 0x4000
#define REGION3_BASE SCL_RPM_CODE_RAM_BASE
#define REGION3_SIZE SCL_RPM_CODE_RAM_SIZE
#define REGION4_BASE 0x40000000
#define REGION4_SIZE 0x08000000
#define REGION5_BASE 0x00104000
#define REGION5_SIZE 0x4000
#define MEMORY_REGION1 {REGION1_BASE, REGION1_SIZE, "Q6 TCM region", "Q6_TCM.BIN"}
#define MEMORY_REGION2 {REGION2_BASE, REGION2_SIZE, "System IMEM region", "SYS_IMEM.BIN"}
#define MEMORY_REGION3 {REGION3_BASE, REGION3_SIZE, "RPM Code RAM region", "CODERAM.BIN"}
#define MEMORY_REGION4 {REGION4_BASE, REGION4_SIZE, "EBI 1 region", "EBI1.BIN"}
#define MEMORY_REGION5 {REGION5_BASE, REGION5_SIZE, "RPM msg region", "RPM_MSG.BIN"}
#define MEMORY_REGION_LAST {NULL, NULL, NULL, NULL}
#define MEMORY_REGION_TABLE MEMORY_REGION1,MEMORY_REGION2,MEMORY_REGION3,MEMORY_REGION4,MEMORY_REGION5,MEMORY_REGION_LAST
#define ADSP_RTOS_DMOV_ENABLE
#define T_CLKREGIM_BRINGUP 
#define FEATURE_SROC
#define FEATURE_QFUSE_PROGRAMMING
#define FEATURE_KARURA
#define FEATURE_MDP_ILCDC
#define FEATURE_MDP_NEW_ARCH
#define FEATURE_PBM_USE_EFS_PB
#define FEATURE_PA_ACCESS_PROBE_CONFIG
#define FEATURE_8K_STUFF_TO_BE_PURGED
#define FEATURE_MSMHWIO
#define IRAM_SIZE 0x2000
#define FEATURE_OSBL_LOAD_AND_BOOT_ADSP
#define ADSP_FW_ISOLATION_ENABLED
#define FEATURE_EBI0
#define FEATURE_DEDICATED_AXI_IMEM
#define SCL_RAM_PART_MEM_INFO_ADDR 0
#define FEATURE_ERR_HAS_F3_TRACE
#define ADIE_I_H "adie_sbi.h"
#define CLKRGM_H "clkregim.h"
#define CLKRGMI_H "clkregim.h"
#define CLKRGM_MSM_H "clkregim.h"
#define CPLD_MSM_H "cpld_t3.h"
#define DMOV_MSM_H "dmov_7500.h"
#define GPIO_H "comdef.h"
#define HS_H "hs_mb7500.h"
#define TSIF_DRV_MSM_H "tsif_drvi_7500.h"
#define PMEM_MSM_H "pmem_7500.h"
#define SBI_LIB_H "sbi_lib_api.h"
#define SBI_MSM_H "sbi.h"
#define TLMM_MSM_H "tlmm.h"
#define FEATURE_SATURN
#define USES_NVRUIM_NOT_FROM_NV
#define FEATURE_PWRDB
#define FEATURE_DLOAD_HW_RESET_DETECT
#define FEATURE_DLOAD_MEM_DEBUG
#define FEATURE_MODEM_HEAP
#define FEATURE_NPA
#define LEDS HWIO_ADDR(HAPPY_LED)
#define FEATURE_KEYPAD_MULTI_KEY
#define FEATURE_SLEEP_CLK_STABILITY
#define FEATURE_PMIC
#define FEATURE_PMIC_TCXO_CONTROL
#define FEATURE_PMIC_NO_RTC_ALARM 
#define FEATURE_PMIC_LCDKBD_LED_DRIVER
#define FEATURE_PMIC_LOW_POWER_MODE
#define FEATURE_IBATT
#define SBI_HAS_GPIO_BUS
#define FEATURE_TCXOMGR
#define FEATURE_SD_SUPPORTS_BASE_INFO
#define FEATURE_KEYPAD_OWNS_KEYPRESS_ISR
#define DISP_DEVICE_16BPP
#define FEATURE_TGL14_TIMING
#define FEATURE_CHG_TASK
#define FEATURE_CBSP_TEST
#define FEATURE_NV_ITEM_MGR
#define FEATURE_OSBL_USB_BATT_CHG
#define BOOT_WEAK_BATTERY_THRESHOLD 3400
#define BOOT_I_DEVICE_POWER_CONSUMPTION 60
#define ERR_DECOUPLE_ENC
#define FEATURE_I2C_CHIP_ENABLE
#define FEATURE_PMIC_HAS_SSBI
#define FEATURE_RDEVMAP_DS_DEFAULT_TO_USB
#define FEATURE_RDEVMAP_DIAG_DEFAULT_TO_USB
#define ADC_CHANNELS_H "adc_channels_surf7500.h"
#define USES_KARURATURBO
#define FEATURE_PMEM
#define FEATURE_PMEM_7K_COMBINE_HEAP1_HEAP2
#define BOOT_MODE_NAND
#define SHADOW_MODE
#define TCM_RAM_BASE 0x80000000
#define TCM_RAM_SIZE 0x0001000
#define IMEM_RAM_BASE 0xFE800000
#define IMEM_BANK_SIZE (64 * 1024)
#define IMEM_NUM_BANKS 4
#define IMEM_RAM_SIZE 0x20000
#define FEATURE_PMEM_REMOTE
#define SCL_MODEM_RELOCATABLE_CODE_BASE 0x90000000
#define SCL_MODEM_RELOCATABLE_CODE_SIZE 0x20000000
#define FEATURE_PMEM_7K_IMEM
#define FEATURE_QFUSE_PROGRAMMING
#define DEVICE_MEM_BASE 0x0004A000
#define DEVICE_MEM_SIZE (0x20000000-0x0004A000)
#define SCL_IMEM_BASE 0x14680000
#define SCL_IMEM_SIZE 0x002C000
#define SCL_PIMEM_BASE 0x1C000000
#define SCL_PIMEM_SIZE 0x4000000
#define SCL_RPM_CODE_RAM_BASE 0x0B000000
#define SCL_RPM_CODE_RAM_SIZE 0x18000
#define SCL_IRAM_BASE SCL_RPM_CODE_RAM_BASE
#define SCL_IRAM_SIZE SCL_RPM_CODE_RAM_SIZE
#define SCL_SDI_CODE_BASE 0x146A5000
#define SCL_SDI_TOTAL_SIZE 36KB
#define SCL_DDR_BASE 0x80000000
#define SCL_DDR_MAX_ALLOWABLE_ADDR 0x880000000
#define SCL_TZ_DDR_OFFSET 0x01E00000
#define SCL_TZ_DDR_RSRV_OFFSET 0x00BC0000
#define SCL_TZ_IMEM_BASE SCL_IMEM_BASE
#define SCL_TZ_DDR_BASE (SCL_DDR_BASE + SCL_TZ_DDR_OFFSET)
#define SCL_TZ_IMEM_TOTAL_SIZE 112KB
#define SCL_TZ_PIMEM_TOTAL_SIZE 0x0400000
#define SCL_TZ_DDR_RSRV_SIZE 0x0040000
#define SCL_TZ_DDR_SIZE SCL_TZ_PIMEM_TOTAL_SIZE
#define SCL_TZ_PIMEM_APP_REGION_BASE 0x1C400000
#define SCL_TZ_PIMEM_APP_REGION_SIZE 0x2200000
#define DEVCFG_DATA_TZ_OFFSET 0xD000
#define DEVCFG_DATA_TZ_ADDR (SCL_PIMEM_BASE + DEVCFG_DATA_TZ_OFFSET)
#define DEVCFG_DATA_TZ_SZ 0xA000
#define DEVCFG_DATA_HYP_ADDR 0x805FD000
#define DEVCFG_DATA_HYP_SZ 0x3000
#define SCL_TZBSP_TEST_BASE 0x80080000
#define GPU_DCVS_FIRST_LEVEL_JUMP
#define GPU_DCVS_FIRST_LEVEL_BUSY_PCNT 98
#define GPU_DCVS_NUMGAPS 5
#define GPU_DCVS_MINGAPCOUNT 25
#define GPU_DCVS_NUMBUSY 5
#define GPU_DCVS_PENALTY 90
#define GPU_DCVS_DOWN_PENALTY 90
#define GPU_DCVS_NUMPWRLEVELS 10
#define SHARED_IMEM_BASE 0x146AB000
#define SHARED_IMEM_SIZE 0x0001000
#define SHARED_IMEM_TZ_OFFSET 0x720
#define SHARED_IMEM_TZ_BASE (SHARED_IMEM_BASE + SHARED_IMEM_TZ_OFFSET)
#define SHARED_IMEM_BOOT_BASE SHARED_IMEM_BASE
#define SHARED_IMEM_BOOT_SIZE 0X00C8
#define DLOAD_ID_ADDR SHARED_IMEM_BOOT_BASE
#define SHARED_IMEM_BOOT_MAGIC_NUM_ADDR (SHARED_IMEM_BOOT_BASE+0x8)
#define SHARED_IMEM_BOOT_ETB_ADDR (SHARED_IMEM_BOOT_BASE+0x10)
#define SHARED_IMEM_USB_BASE (SHARED_IMEM_BOOT_BASE + SHARED_IMEM_BOOT_SIZE)
#define SHARED_IMEM_USB_SIZE 0X00C8
#define SHARED_IMEM_BOOT_CDT_BASE (SHARED_IMEM_USB_BASE + SHARED_IMEM_USB_SIZE)
#define SHARED_IMEM_BOOT_CDT_SIZE (0x400)
#define EFS_COOKIE_IMEM_START_ADDRESS (SHARED_IMEM_BOOT_CDT_BASE + SHARED_IMEM_BOOT_CDT_SIZE)
#define EFS_COOKIE_IMEM_SIZE_IN_BYTES (0x00C8)
#define SHARED_IMEM_HLOS_BASE (EFS_COOKIE_IMEM_START_ADDRESS + EFS_COOKIE_IMEM_SIZE_IN_BYTES)
#define SHARED_IMEM_HLOS_SIZE (0x00C8)
#define SHARED_IMEM_UNUSED_BASE (SHARED_IMEM_HLOS_BASE + SHARED_IMEM_HLOS_SIZE)
#define SHARED_IMEM_UNUSED_SIZE (SHARED_IMEM_SIZE - (SHARED_IMEM_HLOS_BASE - SHARED_IMEM_BASE))
#define TZBSP_PBL_SBL_RECLAIMED_END 0x14685000
#define TZBSP_PBL_SBL_RECLAIMED_SIZE_SECBOOT_EN 0x0005000
#define TZBSP_PBL_SBL_RECLAIMED_SIZE_SECBOOT_DIS 0x0002000
#define SCL_DLOAD_BUFFERS_BASE 0x80100000
#define SCL_DLOAD_BUFFERS_SIZE 0x0100000
#define SCL_SHARED_RAM_BASE 0x86000000
#define SCL_SHARED_RAM_SIZE 0x0200000
#define SCL_MODEM_EFS_RAM_SIZE 0x0300000
#define SCL_EBI1_MEM_TOTAL_SIZE 0x100000000ULL
#define SCL_EBI1_MEM_BASE 0x80000000
#define CUST_MOB_MODEL_ASSIGNED 4047
#define FEATURE_EFS_PROBE_NAND
#define FLASH_USES_DM
#define FEATURE_FLASH_ALIGN_DEST_BUFFER
#define FEATURE_FLASH_MPU
#define EFS_PAGE_SIZE 4096
#define NAND_PAGE_SIZE 4096
#define NAND_BLK_SIZE 64
#define NAND_DEVICE_SIZE 1024



#ifdef FEATURE_PMIC_MANAGED_LDO
   #undef FEATURE_PMIC_MANAGED_LDO
#endif
#ifdef FEATURE_BATTERY_CHARGER
   #undef FEATURE_BATTERY_CHARGER
#endif

#endif /* TARGJAFAANAAA_H */