; This file defines auxiliary register names for ARC cores ; The format of the input file: ; each device definition begins with a line like this: ; ; .devicename ; ; after it go the auxiliary register definitions in this format: ; ; aux NAME value description ; (extra spaces are ignored) ; ; lines beginning with a space are ignored. ; comment lines should be started with ';' character. ; ; the default device is specified at the start of the file ; ; .default device_name ; .default ARCompact ; ARCompact V1 .ARCompact aux STATUS 0x0000 (obsolete) Status Register aux SEMAPHORE 0x0001 Inter-process/Host semaphore register aux LP_START 0x0002 Loop Start Address aux LP_END 0x0003 Loop End Address aux IDENTITY 0x0004 Processor Identity Register aux DEBUG 0x0005 Debug Register aux PC 0x0006 Program Counter aux ADCR 0x0007 data or addresses comparison value for debugging aux APCR 0x0008 address at which the actionpoint was set aux ACR 0x0009 control register for setting actionpoints aux STATUS32 0x000a Status Register aux STATUS32_L1 0x000b Status Register save for level 1 aux STATUS32_L2 0x000c Status Register save for level 2 aux IC_IVIC 0x0010 ICACHE Invalidate Instruction Cache aux IC_CTRL 0x0011 ICACHE Instruction cache control aux MULHI 0x0012 High part of multiply to restore multiply state aux IC_LIL 0x0013 MULTI-WAY ICACHE cache lock instruction line aux DMC_CODE_RAM 0x0014 CACHE CONTROLLER start address of DMC code RAM aux TAG_ADDR_MASK 0x0015 Direct Mapped Instruction Cache (Virtual Cache) Mask for tag address aux TAG_DATA_MASK 0x0016 Direct Mapped Instruction Cache (Virtual Cache) Mask for tag data aux LINE_LENGTH_MASK 0x0017 Direct Mapped Instruction Cache Mask for line length counter aux AUX_LDST_RAM 0x0018 LOAD STORE RAM Address of local load store RAM aux IC_IVIL 0x0019 ICACHE : cache invalidate instruction line (unlocks as well) aux IC_RAM_ADDRESS 0x001A MULTI-WAY ICACHE cache ram access address aux IC_TAG 0x001B MULTI-WAY ICACHE tag ram access aux IC_WP 0x001C MULTI-WAY ICACHE Way pointer access aux IC_DATA 0x001D MULTI-WAY ICACHE data ram access aux SRAM_SEQ 0x0020 SRAM SEQUENCER SRAM sequencer mode control aux COUNT0 0x0021 Enhanced Timer 0 Timer 0 Count value aux CONTROL0 0x0022 Enhanced Timer 0 Timer 0 Control value aux LIMIT0 0x0023 Enhanced Timer 0 Timer 0 Limit value aux PCPORT 0x0024 PC PORT Control for PC_SEL line aux INT_VECTOR_BASE 0x0025 Basecase ARCompact Interrupt Vector Base address aux VBFDW_MODE 0x0026 Viterbi Instruction VBFDW Instruction Mode aux VBFDW_BM0 0x0027 Viterbi Instruction Branch Metric 0 aux VBFDW_BM1 0x0028 Viterbi Instruction Branch Metric 1 aux VBFDW_ACCU 0x0029 Viterbi Instruction VBFDW Accumulator aux VBFDW_OFST 0x002A Viterbi Instruction XY Memory path metric offset aux VBFDW_INTSTAT 0x002B Viterbi Instruction VBFDW Internal State aux XMAC0_24 0x002C XMAC DSP V3.1 Accumulator XTP aux XMAC1_24 0x002D XMAC DSP V3.1 Accumulator MSP aux XMAC2_24 0x002E XMAC DSP V3.1 Accumulator LSP aux FBF_STORE_16 0x002F XMAC FBF DSP V3.1 FBF OPERAND STORAGE aux AUX_CRC_POLY 0x0032 PROGRAMMABLE CRC POLYNOMIAL REGISTER aux AUX_CRC_MODE 0x0033 PROGRAMMABLE CRC MODE REGISTER aux XTP_NEWVAL 0x0040 MAC The 4-bit extended product of the multiply-accumulate result aux AUX_MACMODE 0x0041 XMAC DSP v2.1/DSP v3.0 aux LSP_NEWVAL 0x0042 MAC Low 32 bit register product aux AUX_IRQ_LV12 0x0043 Interrupt subsystem Sticky flags for interrupts levels 1 and 2 aux AUX_XMAC0 0x0044 XMAC DSP v3.0 Accumulator Extended Product aux AUX_XMAC1 0x0045 XMAC DSP v3.0 Accumulator Most Significant Part aux AUX_XMAC2 0x0046 XMAC DSP v3.0 Accumulator Least Significant Part aux DC_IVDC 0x0047 DATA CACHE Invalidate Data Cache aux DC_CTRL 0x0048 DATA CACHE Control register aux DC_LDL 0x0049 DATA CACHE Lock data line aux DC_IVDL 0x004A DATA CACHE Invalidate data line aux DC_FLSH 0x004B DATA CACHE Flush data cache aux DC_FLDL 0x004C DATA CACHE Flush data line aux AUX_LCD_DATA 0x0053 ARCangel 3 LCD LCD display write data aux AUX_LCD_CNTRL 0x0054 ARCangel 3 LCD LCD display control register final aux AUX_US_COUNT 0x0055 ARCangel 3 LCD LCD working frequency aux AUX_LCD_BUTTONISTER 0x0057 ARCangel 3 Front panel button auxiliary register aux DC_RAM_ADDR 0x0058 DATA CACHE Address for data cache RAM access aux DC_TAG 0x0059 DATA CACHE Tag data associated with dc_ram_addr aux DC_WP 0x005A DATA CACHE Way Pointer value associated with dc_ram_addr aux DC_DATA 0x005B DATA CACHE Data longword associated with dc_ram_addr aux DCCM_BASE_BUILD 0x0061 Base Address Data Closely Coupled Memory (DCCM) aux CRC_BUILD_BCR 0x0062 CRC instruction aux BTA_LINK_BUILD 0x0063 BTA_L1/BTA_L2 registers aux RTT_BUILD 0x0063 Real-Time Trace Unit aux DVBF_BUILD 0x0064 Dual viterbi butterfly instruction aux TEL_INSTR_BUILD 0x0065 DSP v3.0 instructions package aux DATASPACE 0x0066 Dataspace aux MEMSUBSYS 0x0067 Memory subsystem aux VECBASE_AC_BUILD 0x0068 ARCompact Interrupt Vector Base Address aux P_BASE_ADDR 0x0069 Peripheral base address aux DATA_UNCACHED_BUILD 0x006A Data Uncached Build Configuration Register aux RF_BUILD 0x006E RF_BUILD r Core Registers aux MMU_BUILD 0x006F MMU_BUILD r Memory Management Unit (MMU) aux D_CACHE_BUILD 0x0072 Data Cache aux MADI_BUILD 0x0073 Multiple ARC Debug Interface aux LDSTRAM_BUILD 0x0074 LD/ST RAM aux DCCM_BUILD 0x0074 Data Closely Coupled Memory (ARC 700) aux TIMER_BUILD 0x0075 Timer aux AP_BUILD 0x0076 Actionpoints aux I_CACHE_BUILD 0x0077 Instruction Cache aux ADDSUB_BUILD 0x0078 Saturated Add/Sub (obsolete) aux ICCM_BUILD 0x0078 Instruction Closely Coupled Memory (ARC 700) aux DSPRAM_BUILD 0x0079 Scratchpad and XY Memory Build Configuration Register (DSPRAM_BUILD) aux MAC_BUILD 0x007A MUL/MAC aux MULTIPLY_BUILD 0x007B Multiply aux SWAP_BUILD 0x007C Swap aux NORM_BUILD 0x007D Normalize aux MINMAX_BUILD 0x007E MIN/MAX aux BARREL_BUILD 0x007F Barrel shift .ARCv2 aux STATUS 0x0000 (obsolete) Status Register aux SEMAPHORE 0x0001 Inter-process/Host semaphore register aux LP_START 0x0002 Loop Start Address aux LP_END 0x0003 Loop End Address aux IDENTITY 0x0004 Processor Identity Register aux DEBUG 0x0005 Debug Register aux PC 0x0006 Program Counter aux STATUS32 0x000A Status Register aux STATUS32_P0 0x000B Status register priority 0 aux AUX_USER_SP 0x000D Saved User mode stack pointer aux AUX_IRQ_CTRL 0x000E Interrupt context saving control register aux IC_IVIC 0x0010 ICACHE Invalidate Instruction Cache aux IC_CTRL 0x0011 ICACHE Instruction cache control aux MULHI 0x0012 High part of multiply to restore multiply state aux IC_LIL 0x0013 MULTI-WAY ICACHE cache lock instruction line aux DMC_CODE_RAM 0x0014 CACHE CONTROLLER start address of DMC code RAM aux TAG_ADDR_MASK 0x0015 Direct Mapped Instruction Cache (Virtual Cache) Mask for tag address aux TAG_DATA_MASK 0x0016 Direct Mapped Instruction Cache (Virtual Cache) Mask for tag data aux LINE_LENGTH_MASK 0x0017 Direct Mapped Instruction Cache Mask for line length counter aux AUX_LDST_RAM 0x0018 LOAD STORE RAM Address of local load store RAM aux IC_IVIL 0x0019 ICACHE : cache invalidate instruction line (unlocks as well) aux IC_RAM_ADDRESS 0x001A MULTI-WAY ICACHE cache ram access address aux IC_TAG 0x001B MULTI-WAY ICACHE tag ram access aux IC_WP 0x001C MULTI-WAY ICACHE Way pointer access aux IC_DATA 0x001D MULTI-WAY ICACHE data ram access aux SRAM_SEQ 0x0020 SRAM SEQUENCER SRAM sequencer mode control aux COUNT0 0x0021 Enhanced Timer 0 Timer 0 Count value aux CONTROL0 0x0022 Enhanced Timer 0 Timer 0 Control value aux LIMIT0 0x0023 Enhanced Timer 0 Timer 0 Limit value aux PCPORT 0x0024 PC PORT Control for PC_SEL line aux INT_VECTOR_BASE 0x0025 Interrupt Vector Base address aux VBFDW_MODE 0x0026 Viterbi Instruction VBFDW Instruction Mode aux VBFDW_BM0 0x0027 Viterbi Instruction Branch Metric 0 aux VBFDW_BM1 0x0028 Viterbi Instruction Branch Metric 1 aux VBFDW_ACCU 0x0029 Viterbi Instruction VBFDW Accumulator aux VBFDW_OFST 0x002A Viterbi Instruction XY Memory path metric offset aux VBFDW_INTSTAT 0x002B Viterbi Instruction VBFDW Internal State aux XMAC0_24 0x002C XMAC DSP V3.1 Accumulator XTP aux XMAC1_24 0x002D XMAC DSP V3.1 Accumulator MSP aux XMAC2_24 0x002E XMAC DSP V3.1 Accumulator LSP aux FBF_STORE_16 0x002F XMAC FBF DSP V3.1 FBF OPERAND STORAGE aux AUX_CRC_POLY 0x0032 PROGRAMMABLE CRC POLYNOMIAL REGISTER aux AUX_CRC_MODE 0x0033 PROGRAMMABLE CRC MODE REGISTER aux XTP_NEWVAL 0x0040 MAC The 4-bit extended product of the multiply-accumulate result aux AUX_MACMODE 0x0041 XMAC DSP v2.1/DSP v3.0 aux LSP_NEWVAL 0x0042 MAC Low 32 bit register product aux AUX_IRQ_LV12 0x0043 Interrupt subsystem Sticky flags for interrupts levels 1 and 2 aux AUX_XMAC0 0x0044 XMAC DSP v3.0 Accumulator Extended Product aux AUX_XMAC1 0x0045 XMAC DSP v3.0 Accumulator Most Significant Part aux AUX_XMAC2 0x0046 XMAC DSP v3.0 Accumulator Least Significant Part aux DC_IVDC 0x0047 DATA CACHE Invalidate Data Cache aux DC_CTRL 0x0048 DATA CACHE Control register aux DC_LDL 0x0049 DATA CACHE Lock data line aux DC_IVDL 0x004A DATA CACHE Invalidate data line aux DC_FLSH 0x004B DATA CACHE Flush data cache aux DC_FLDL 0x004C DATA CACHE Flush data line aux AUX_LCD_DATA 0x0053 ARCangel 3 LCD LCD display write data aux AUX_LCD_CNTRL 0x0054 ARCangel 3 LCD LCD display control register final aux AUX_US_COUNT 0x0055 ARCangel 3 LCD LCD working frequency aux AUX_LCD_BUTTONISTER 0x0057 ARCangel 3 Front panel button auxiliary register aux DC_RAM_ADDR 0x0058 DATA CACHE Address for data cache RAM access aux DC_TAG 0x0059 DATA CACHE Tag data associated with dc_ram_addr aux DC_WP 0x005A DATA CACHE Way Pointer value associated with dc_ram_addr aux DC_DATA 0x005B DATA CACHE Data longword associated with dc_ram_addr aux BCR_VER 0x0060 Build Configuration Registers Version aux DCCM_BASE_BUILD 0x0061 Base Address Data Closely Coupled Memory (DCCM) aux CRC_BUILD_BCR 0x0062 CRC instruction aux BTA_LINK_BUILD 0x0063 BTA Configuration Register aux RTT_BUILD 0x0063 Real-Time Trace Unit aux DVBF_BUILD 0x0064 Dual viterbi butterfly instruction aux TEL_INSTR_BUILD 0x0065 DSP v3.0 instructions package aux DATASPACE 0x0066 Dataspace aux MEMSUBSYS 0x0067 Memory subsystem aux VECBASE_AC_BUILD 0x0068 Interrupt Vector Base Address Configuration aux P_BASE_ADDR 0x0069 Peripheral base address aux DATA_UNCACHED_BUILD 0x006A Data Uncached Build Configuration Register aux RF_BUILD 0x006E Core Register File Configuration Register aux MMU_BUILD 0x006F MMU Build Configuration Register aux D_CACHE_BUILD 0x0072 Data Cache aux MADI_BUILD 0x0073 Multiple ARC Debug Interface aux LDSTRAM_BUILD 0x0074 LD/ST RAM aux DCCM_BUILD 0x0074 Data Closely Coupled Memory (ARC 700) aux TIMER_BUILD 0x0075 Timer aux AP_BUILD 0x0076 Actionpoints aux I_CACHE_BUILD 0x0077 Instruction Cache aux ADDSUB_BUILD 0x0078 Saturated Add/Sub (obsolete) aux ICCM_BUILD 0x0078 Instruction Closely Coupled Memory (ARC 700) aux DSPRAM_BUILD 0x0079 Scratchpad and XY Memory Build Configuration Register (DSPRAM_BUILD) aux MAC_BUILD 0x007A MUL/MAC aux MULTIPLY_BUILD 0x007B Multiplier Configuration Register aux SWAP_BUILD 0x007C Swap Instruction Configuration Register aux NORM_BUILD 0x007D Normalize Instruction Configuration Register aux MINMAX_BUILD 0x007E Min/Max Instruction Configuration Register aux BARREL_BUILD 0x007F Barrel Shifter Configuration Register aux BPU_BUILD 0x00C0 Branch Prediction Unit Configuration Register aux ISA_CONFIG 0x00C1 ISA options register aux DMP_PP_BUILD 0x00C3 Peripheral Region Build Configuration Register aux STACK_REGION_BUILD 0x00C5 Stack Region Configuration Register aux ERP_BUILD 0x00C7 Error Protection Configuration Register aux FPU_BUILD 0x00C8 Floating-Point Unit Build Register aux AGU_BUILD 0x00CC AGU Build Configuration Register aux IRQ_BUILD 0x00F3 Interrupt Build Configuration Register aux ISA_PROFILE 0x00F8 ARCv2 ISA Profile Register aux MICRO_ARCH_BUILD 0x00F9 Micro Architecture Configuration Register aux IRQ_PRIORITY_PENDING 0x0200 Interrupt Priority Pending Register aux AUX_IRQ_HINT 0x0201 Software Interrupt Trigger aux IRQ_PRIORITY 0x0206 Interrupt Priority Register aux DATA_MEM_ATTR 0x020B Data Memory Attribute Register aux JLI_BASE 0x0290 Jump and Link Indexed Base Address aux LDI_BASE 0x0291 Load Indexed Base Address aux EI_BASE 0x0292 Execute Indexed Base Address aux FPU_CTRL 0x0300 Floating-Point Unit Control Register aux FPU_STATUS 0x0301 Floating-Point Unit Status Register aux AUX_DPFP1L 0x0302 Double Precision Floating Point D1 Lower Register aux AUX_DPFP1H 0x0303 Double Precision Floating Point D1 Higher Register aux AUX_DPFP2L 0x0304 Double Precision Floating Point D2 Lower Register aux AUX_DPFP2H 0x0305 Double Precision Floating Point D2 Higher Register aux ERET 0x0400 Exception Return Address aux ERBTA 0x0401 Exception Return Branch Target Address aux ERSTATUS 0x0402 Exception Return Status aux ECR 0x0403 Exception Cause Register aux EFA 0x0404 Exception Fault Address aux ICAUSE 0x040A Interrupt Cause Registers aux IRQ_SELECT 0x040B Interrupt Select aux IRQ_ENABLE 0x040C Interrupt Enable Register aux IRQ_TRIGGER 0x040D Interrupt Trigger Register aux IRQ_STATUS 0x040F Interrupt Status Register aux XPU 0x0410 User Mode Extension Enable Register aux BTA 0x0412 Branch Target Address aux IRQ_PULSE_CANCEL 0x0415 Interrupt Pulse Cancel Register aux IRQ_PENDING 0x0416 Interrupt Pending Register aux XFLAGS 0x044F User Extension Flags Register .ARC4 aux STATUS 0x0000 Status Register aux SEMAPHORE 0x0001 Inter-process/Host semaphore register aux LP_START 0x0002 Loop Start Address aux LP_END 0x0003 Loop End Address aux IDENTITY 0x0004 Processor Identity Register aux DEBUG 0x0005 Debug Register aux BPU_FLUSH 0x000f Read/Write register to cause a hardware flush of the BPU aux IC_IVIC 0x0010 ICACHE Invalidate Instruction Cache aux IC_CTRL 0x0011 ICACHE Instruction cache control aux MULHI 0x0012 High part of multiply to restore multiply state aux COUNT 0x0021 Enhanced Timer 0 Timer 0 Count value aux CONTROL 0x0022 Enhanced Timer 0 Timer 0 Control value aux DC_IVDC 0x0047 DATA CACHE Invalidate Data Cache aux DC_CTRL 0x0048 DATA CACHE Control register aux DC_LDL 0x0049 DATA CACHE Lock data line aux DC_IVDL 0x004A DATA CACHE Invalidate data line aux DC_FLSH 0x004B DATA CACHE Flush data cache aux DC_FLDL 0x004C DATA CACHE Flush data line